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2024-06-24brd: add missing MODULE_DESCRIPTION() macroJeff Johnson1-0/+1
make allmodconfig && make W=1 C=1 reports: modpost: missing MODULE_DESCRIPTION() in drivers/block/brd.o Add the missing invocation of the MODULE_DESCRIPTION() macro. Signed-off-by: Jeff Johnson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jens Axboe <[email protected]>
2024-06-24mmc: sdhci-brcmstb: Add ARCH_BCM2835 optionPeter Robinson1-1/+1
The Raspberry Pi devices have to date all used ARCH_BCM2835 as their SoC arch dependency so configurations that use this and not BRCMSTB won't end up with this module in their config. Signed-off-by: Peter Robinson <[email protected]> Reviewed-by: Andrea della Porta <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2024-06-24Merge tag 'pinctrl-v6.10-2' of ↵Linus Torvalds8-17/+65
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control fixes from Linus Walleij: - Use flag saving spinlocks in the Renesas rzg2l driver. This fixes up PREEMPT_RT problems. - Remove broken Qualcomm PM8008 that clearly was never working. A new version will arrive in the next merge window. - Add a quirk for LP8764 regmap that was missed and made the TI J7200 board unusable. - Fix persistance on the BCM2835 GPIO outputs kernel parameter so this remains consisten across a booted kernel. - Fix a potential deadlock in create_pinctrl() - Fix some erroneous bitfields and pinmux reset in the Rockchip RK3328 driver. * tag 'pinctrl-v6.10-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: rockchip: fix pinmux reset in rockchip_pmx_set pinctrl: rockchip: use dedicated pinctrl type for RK3328 pinctrl: rockchip: fix pinmux bits for RK3328 GPIO3-B pins pinctrl: rockchip: fix pinmux bits for RK3328 GPIO2-B pins pinctrl: fix deadlock in create_pinctrl() when handling -EPROBE_DEFER pinctrl: bcm2835: Fix permissions of persist_gpio_outputs pinctrl: tps6594: add missing support for LP8764 PMIC dt-bindings: pinctrl: qcom,pmic-gpio: drop pm8008 pinctrl: qcom: spmi-gpio: drop broken pm8008 support pinctrl: renesas: rzg2l: Use spin_{lock,unlock}_irq{save,restore}
2024-06-24dt-bindings: fuse: Document R-Car E-FUSE / OTP_MEMGeert Uytterhoeven1-0/+38
Document support for E-FUSE non-volatile memory accessible through OTP_MEM on R-Car V4H and V4M. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Reviewed-by: Rob Herring (Arm) <[email protected]> Link: https://lore.kernel.org/436506babe4ce468fda19380d9373470468e3752.1716974502.git.geert+renesas@glider.be
2024-06-24dt-bindings: fuse: Document R-Car E-FUSE / PFCGeert Uytterhoeven1-0/+55
Document support for E-FUSE non-volatile memory accessible through PFC on R-Car V3U and S4-8. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Reviewed-by: Rob Herring (Arm) <[email protected]> Link: https://lore.kernel.org/03e43e97941df238ef1a618852aecd7be68adbb0.1716974502.git.geert+renesas@glider.be
2024-06-24drm/i915: Nuke the TGL+ chroma plane tile row alignment stuffVille Syrjälä3-26/+1
I don't think the display hardware really has such chroma plane tile row alignment requirements as outlined in commit d156135e6a54 ("drm/i915/tgl: Make sure a semiplanar UV plane is tile row size aligned") Bspec had the same exact thing to say about earlier hardware as well, but we never cared and things work just fine. The one thing mentioned in that commit that is definitely true however is the fence alignment issue. But we don't deal with that on earlier hardware either. We do have code to deal with that issue for the first color plane, but not the chroma planes. So I think if we did want to check this more extensively we should do it in the same places where we already check the first color plane (namely convert_plane_offset_to_xy() and intel_fb_bo_framebuffer_init()). Reviewed-by: Imre Deak <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-24serial: bcm63xx-uart: fix tx after conversion to uart_port_tx_limited()Jonas Gorski1-2/+5
When bcm63xx-uart was converted to uart_port_tx_limited(), it implicitly added a call to stop_tx(). This causes garbage to be put out on the serial console. To fix this, pass UART_TX_NOSTOP in flags, and manually call stop_tx() ourselves analogue to how a similar issue was fixed in commit 7be50f2e8f20 ("serial: mxs-auart: fix tx"). Fixes: d11cc8c3c4b6 ("tty: serial: use uart_port_tx_limited()") Cc: [email protected] Signed-off-by: Jonas Gorski <[email protected]> Signed-off-by: Doug Brown <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-06-24serial: core: introduce uart_port_tx_limited_flags()Jonas Gorski1-0/+18
Analogue to uart_port_tx_flags() introduced in commit 3ee07964d407 ("serial: core: introduce uart_port_tx_flags()"), add a _flags variant for uart_port_tx_limited(). Fixes: d11cc8c3c4b6 ("tty: serial: use uart_port_tx_limited()") Cc: [email protected] Signed-off-by: Jonas Gorski <[email protected]> Signed-off-by: Doug Brown <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-06-24Revert "serial: core: only stop transmit when HW fifo is empty"Doug Brown1-2/+1
This reverts commit 7bfb915a597a301abb892f620fe5c283a9fdbd77. This commit broke pxa and omap-serial, because it inhibited them from calling stop_tx() if their TX FIFOs weren't completely empty. This resulted in these two drivers hanging during transmits because the TX interrupt would stay enabled, and a new TX interrupt would never fire. Cc: [email protected] Fixes: 7bfb915a597a ("serial: core: only stop transmit when HW fifo is empty") Signed-off-by: Doug Brown <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-06-24serial: imx: set receiver level before starting uartStefan Eichenberger1-1/+3
Set the receiver level to something > 0 before calling imx_uart_start_rx in rs485_config. This is necessary to avoid an interrupt storm that might prevent the system from booting. This was seen on an i.MX7 device when the rs485-rts-active-low property was active in the device tree. Fixes: 6d215f83e5fc ("serial: imx: warn user when using unsupported configuration") Cc: stable <[email protected]> Signed-off-by: Stefan Eichenberger <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-06-24tty: mcf: MCF54418 has 10 UARTSJean-Michel Hautbois1-1/+1
Most of the colfires have up to 5 UARTs but MCF54418 has up-to 10 ! Change the maximum value authorized. Signed-off-by: Jean-Michel Hautbois <[email protected]> Cc: stable <[email protected]> Fixes: 2545cf6e94b4 ("m68knommu: allow 4 coldfire serial ports") Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-06-24drm/i915: Update plane alignment requirements for TGL+Ville Syrjälä1-43/+56
Currently we still use the SKL+ PLANE_SURF alignment even for TGL+ even though the hardware no longer needs it. Introduce a separate tgl_plane_min_alignment() and update it to more accurately reflect the hardware requirements. v2: Don't screw up DPT+semiplanar 2MiB alignment Reviewed-by: Imre Deak <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-24drm/i915: Move intel_surf_alignment() into skl_univerals_plane.cVille Syrjälä3-80/+78
Now that all pre-skl platforms have their own .min_alignment() functions the remainder of intel_surf_alignment() can be hoisted into skl_univerals_plane.c (and renamed appropriately). Reviewed-by: Imre Deak <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-24serial: 8250_omap: Implementation of Errata i2310Udit Kumar1-5/+20
As per Errata i2310[0], Erroneous timeout can be triggered, if this Erroneous interrupt is not cleared then it may leads to storm of interrupts, therefore apply Errata i2310 solution. [0] https://www.ti.com/lit/pdf/sprz536 page 23 Fixes: b67e830d38fa ("serial: 8250: 8250_omap: Fix possible interrupt storm on K3 SoCs") Cc: [email protected] Signed-off-by: Udit Kumar <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-06-24drm/i915: Split pre-skl platforms out from intel_surf_alignment()Ville Syrjälä3-18/+96
Extract the necessary chunks from intel_surf_alignment() into per-platform variants for all pre-skl primary/sprite planes. Reviewed-by: Imre Deak <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-24drm/i915: Split cursor alignment to per-platform vfuncsVille Syrjälä3-21/+38
Split intel_cursor_alignment() into per-platform variants. Reviewed-by: Imre Deak <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-06-24tty: serial: 8250: Fix port count mismatch with the deviceCrescent Hsieh1-1/+12
Normally, the number of ports is indicated by the third digit of the device ID on Moxa PCI serial boards. For example, `0x1121` indicates a device with 2 ports. However, `CP116E_A_A` and `CP116E_A_B` are exceptions; they have 8 ports, but the third digit of the device ID is `6`. This patch introduces a function to retrieve the number of ports on Moxa PCI serial boards, addressing the issue described above. Fixes: 37058fd5d239 ("tty: serial: 8250: Add support for MOXA Mini PCIe boards") Cc: stable <[email protected]> Signed-off-by: Crescent Hsieh <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-06-24drm/i915: Introduce fb->min_alignmentVille Syrjälä4-20/+34
Different planes could have different alignment requirements even for the same format/modifier. Collect the alignment requirements across all planes capable of scanning out the fb such that the alignment is satisfactory to all those planes. So far this was sort of handled by making sure intel_surf_alignment() declares the superset of all planes' alignment requirements, but maintaining that manually is annoying. So we're going to move towards each plane declaring only its own requirements, and thus we need code to generate the superset. v2: Drop the borked per-plane vma optimization (Imre) Assert that the plane's declared alignment is POT (Imre) Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Imre Deak <[email protected]>
2024-06-24serial: sc16is7xx: hardware reset chip if reset-gpios is defined in DTHui Wang1-3/+28
Some boards connect a GPIO to the reset pin, and the reset pin needs to be set up correctly before accessing the chip. Add a function to handle the chip reset. If the reset-gpios is defined in the DT, do hardware reset through this GPIO, otherwise do software reset as before. Reviewed-by: Lech Perczak <[email protected]> Tested-by: Hugo Villeneuve <[email protected]> Reviewed-by: Hugo Villeneuve <[email protected]> Signed-off-by: Hui Wang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-06-24dt-bindings: serial: sc16is7xx: add reset-gpiosHui Wang1-0/+5
In some designs, the chip reset pin is connected to a GPIO, and this GPIO needs to be set correctly before probing the driver, so add a reset-gpios in the device tree. Acked-by: Conor Dooley <[email protected]> Reviewed-by: Lech Perczak <[email protected]> Tested-by: Hugo Villeneuve <[email protected]> Reviewed-by: Hugo Villeneuve <[email protected]> Signed-off-by: Hui Wang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-06-24dt-bindings: serial: vt8500-uart: convert to json-schemaKanak Shilledar2-27/+46
Convert the VIA VT8500 and WonderMedia WM8xxx UART Controller to newer DT schema. Created DT schema based on the .txt file which had `compatible`, `reg`, `interrupts` and `clocks` as required properties. Additions to the original binding - changed the file name from vt8500-uart to via,vt8500-uart.yaml - removed unnecessary alias from the example. Signed-off-by: Kanak Shilledar <[email protected]> Acked-by: Alexey Charkov <[email protected]> Reviewed-by: Rob Herring (Arm) <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-06-24serial: 8250_platform: Explicitly show we initialise ISA ports only onceAndy Shevchenko1-6/+7
serial8250_isa_init_ports() uses home grown approach to make itself a singleton. Instead, explicitly show that we initialise ISA ports once by providing a helper function which calls the original function via DO_ONCE() macro. Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-06-24tty: add missing MODULE_DESCRIPTION() macrosJeff Johnson15-0/+15
make allmodconfig && make W=1 C=1 reports: WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/tty/serial/8250/8250_base.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/tty/serial/8250/8250_pxa.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/tty/serial/8250/serial_cs.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/tty/serial/esp32_uart.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/tty/serial/esp32_acm.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/tty/serial/owl-uart.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/tty/n_hdlc.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/tty/n_gsm.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/tty/ttynull.o WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/tty/goldfish.o Add all missing invocations of the MODULE_DESCRIPTION() macro. Signed-off-by: Jeff Johnson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-06-24drm/i915: Introduce the plane->min_alignment() vfuncVille Syrjälä12-37/+89
Different hardware generations have different scanout alignment requirements. Introduce a new vfunc that will allow us to make that distinction without horrible if-ladders. For now we directly plug in the existing intel_surf_alignment() and intel_cursor_alignment() functions. For fbdev we (temporarily) introduce intel_fbdev_min_alignment() that simply queries the alignment from the primary plane of the first crtc. TODO: someone will need to fix xe's alignment handling Reviewed-by: Imre Deak <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Acked-by: Rodrigo Vivi <[email protected]>
2024-06-24dt-bindings: serial: mediatek,uart: add MT7988Rafał Miłecki1-0/+1
Add compatible string for serial on MT7988 SoC. Signed-off-by: Rafał Miłecki <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Acked-by: Conor Dooley <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-06-24serial: sh-sci: Add support for RZ/V2H(P) SoCLad Prabhakar2-5/+51
Add serial support for RZ/V2H(P) SoC with earlycon. The SCIF interface in the Renesas RZ/V2H(P) is similar to that available in the RZ/G2L (R9A07G044) SoC, with the following differences: - RZ/V2H(P) SoC has three additional interrupts: one for Tx end/Rx ready and two for Rx and Tx buffer full, all of which are edge-triggered. - RZ/V2H(P) supports asynchronous mode, whereas RZ/G2L supports both synchronous and asynchronous modes. - There are differences in the configuration of certain registers such as SCSMR, SCFCR, and SCSPTR between the two SoCs. To handle these differences on RZ/V2H(P) SoC SCIx_RZV2H_SCIF_REGTYPE is added. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-06-24dt-bindings: serial: Add documentation for Renesas RZ/V2H(P) (R9A09G057) ↵Lad Prabhakar1-0/+30
SCIF support Document support for the Serial Communication Interface with FIFO (SCIF) available in the Renesas RZ/V2H(P) (R9A09G057) SoC. The SCIF interface in the Renesas RZ/V2H(P) is similar to that available in the RZ/G2L (R9A07G044) SoC, with the following differences: - RZ/V2H(P) SoC has three additional interrupts: one for Tx end/Rx ready and two for Rx and Tx buffer full, all of which are edge-triggered. - RZ/V2H(P) supports asynchronous mode, whereas RZ/G2L supports both synchronous and asynchronous modes. - There are differences in the configuration of certain registers such as SCSMR, SCFCR, and SCSPTR between the two SoCs. To handle these differences in the driver, a new SoC-specific compatible string is added, ensuring proper handling of the unique features and register configurations of the RZ/V2H(P) SoC. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Conor Dooley <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-06-24dt-bindings: serial: renesas,scif: Make 'interrupt-names' property as requiredLad Prabhakar1-0/+3
As all the SoCs having multiple interrupts have 'interrupt-names' property in their respective DTSIs, make 'interrupt-names' property as required so that we can validate them using dtbs_check. Signed-off-by: Lad Prabhakar <[email protected]> Acked-by: Conor Dooley <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-06-24dt-bindings: serial: renesas,scif: Validate 'interrupts' and 'interrupt-names'Lad Prabhakar1-18/+55
This commit adds support to validate the 'interrupts' and 'interrupt-names' properties for every supported SoC. This ensures proper handling and configuration of interrupt-related properties across supported platforms. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Conor Dooley <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-06-24dt-bindings: serial: renesas,scif: Move ref for serial.yaml at the endLad Prabhakar1-15/+15
In preparation for adding more validation checks move the ref for 'serial.yaml' to the end and also move reset check in 'allOf' block. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-06-24riscv: dts: starfive: jh7110: Add the core reset and jh7110 compatible for uartsHal Feng1-12/+18
Add the core reset for uarts, which is necessary for uarts to work. Signed-off-by: Hal Feng <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-06-24serial: 8250_dw: Use reset array API to get resetsHal Feng1-1/+1
Some SoCs like StarFive JH7110 require two or more resets. So change to use the reset array API to get resets. Signed-off-by: Hal Feng <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-06-24dt-bindings: serial: snps-dw-apb-uart: Add one more reset signal for ↵Hal Feng1-1/+17
StarFive JH7110 SoC The UART of StarFive JH7110 has two reset signals. Both of them are necessary for JH7110 to initialize UART. Signed-off-by: Hal Feng <[email protected]> Reviewed-by: Conor Dooley <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-06-24drm: Export drm_plane_has_format()Ville Syrjälä3-2/+12
Export drm_plane_has_format() so that drivers can use it. v2: add kerneldoc Reviewed-by: Jani Nikula <[email protected]> Reviewed-by: Daniel Vetter <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Daniel Vetter <[email protected]> Acked-by: Daniel Stone <[email protected]> Acked-by: Thomas Zimmermann <[email protected]>
2024-06-24drm: Rename drm_plane_check_pixel_format() to drm_plane_has_format()Ville Syrjälä4-23/+16
Rename drm_plane_check_pixel_format() to drm_plane_has_format() and change the return type accordingly. Allows one to write more natural code. Also matches drm_any_plane_has_format() better. Reviewed-by: Jani Nikula <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Daniel Vetter <[email protected]> Acked-by: Thomas Zimmermann <[email protected]>
2024-06-24netfilter: fix undefined reference to 'netfilter_lwtunnel_*' when ↵Jianguo Wu1-0/+3
CONFIG_SYSCTL=n if CONFIG_SYSFS is not enabled in config, we get the below compile error, All errors (new ones prefixed by >>): csky-linux-ld: net/netfilter/core.o: in function `netfilter_init': core.c:(.init.text+0x42): undefined reference to `netfilter_lwtunnel_init' >> csky-linux-ld: core.c:(.init.text+0x56): undefined reference to `netfilter_lwtunnel_fini' >> csky-linux-ld: core.c:(.init.text+0x70): undefined reference to `netfilter_lwtunnel_init' csky-linux-ld: core.c:(.init.text+0x78): undefined reference to `netfilter_lwtunnel_fini' Fixes: a2225e0250c5 ("netfilter: move the sysctl nf_hooks_lwtunnel into the netfilter core") Reported-by: Mirsad Todorovac <[email protected]> Reported-by: kernel test robot <[email protected]> Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/ Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/ Signed-off-by: Jianguo Wu <[email protected]> Signed-off-by: Pablo Neira Ayuso <[email protected]>
2024-06-24fbdev: Drop explicit initialization of struct i2c_device_id::driver_data to 0Uwe Kleine-König2-5/+5
These drivers don't use the driver_data member of struct i2c_device_id, so don't explicitly initialize this member. This prepares putting driver_data in an anonymous union which requires either no initialization or named designators. But it's also a nice cleanup on its own. Signed-off-by: Uwe Kleine-König <[email protected]> Signed-off-by: Helge Deller <[email protected]>
2024-06-24pinctrl: renesas: rzg2l: Reorganize variable configuration macroLad Prabhakar1-12/+17
The `PIN_CFG_VARIABLE` macro did not indicate the capabilities of a pin but served as a flag indicating that the pins of a port have different capabilities. To better reflect its purpose, move the `PIN_CFG_VARIABLE` macro beside `RZG2L_SINGLE_PIN` and rename it to `RZG2L_VARIABLE_CFG`. Additionally, introduce new macros for packing variable port configurations: - `RZG2L_GPIO_PORT_PACK_VARIABLE(n, a)`: Combines `RZG2L_VARIABLE_CFG` with `RZG2L_GPIO_PORT_PACK` to handle variable pin configurations for a packed port. - `RZG2L_GPIO_PORT_SPARSE_PACK_VARIABLE(m, a)`: Combines `RZG2L_VARIABLE_CFG` with `RZG2L_GPIO_PORT_SPARSE_PACK` to handle variable pin configurations for a sparse port. Due to the above change the configuration macros have been reorganized as follows: - Shift the bit positions of `PIN_CFG_NOGPIO_INT`, `PIN_CFG_NOD`, `PIN_CFG_SMT`, `PIN_CFG_ELC`, and `PIN_CFG_IOLH_RZV2H` down by one to accommodate the removal of `PIN_CFG_VARIABLE`. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Tested-by: Claudiu Beznea <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-06-24pinctrl: renesas: rzg2l: Move RZG2L_SINGLE_PIN definition to top of the fileLad Prabhakar1-7/+7
Define `RZG2L_SINGLE_PIN` at the top of the file to clarify its use for dedicated pins for improved readability. While at it update the comment for `RZG2L_SINGLE_PIN_PACK` macro and place it just above the macro for clarity. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Tested-by: Claudiu Beznea <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-06-24pinctrl: renesas: rzg2l: Adjust bit masks for PIN_CFG_VARIABLE to use BIT(62)Lad Prabhakar1-2/+2
Shift the bit masks for `PIN_CFG_PIN_MAP_MASK` and `PIN_CFG_PIN_REG_MASK`, to accommodate `PIN_CFG_VARIABLE` using `BIT(62)`. Previously, these bit masks were placed higher up in the bit range, which did not leave room for `PIN_CFG_VARIABLE` at `BIT(62)`. By adjusting these masks, we ensure that `PIN_CFG_VARIABLE` can occupy `BIT(62)` without any conflicts. The updated masks are now: - `PIN_CFG_PIN_MAP_MASK`: `GENMASK_ULL(61, 54)` (was `GENMASK_ULL(62, 55)`) - `PIN_CFG_PIN_REG_MASK`: `GENMASK_ULL(53, 46)` (was `GENMASK_ULL(54, 47)`) Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Tested-by: Claudiu Beznea <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-06-24pinctrl: renesas: rzg2l: Update PIN_CFG_MASK() macro to be 32-bit wideLad Prabhakar1-6/+6
Modify the `PIN_CFG_MASK()` macro to be 32-bit wide. The current maximum value for `PIN_CFG_*` is `BIT(21)`, which fits within a 32-bit mask. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Tested-by: Claudiu Beznea <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-06-24dt-bindings: clock: rcar-gen2: Remove obsolete header filesGeert Uytterhoeven5-713/+0
The clock definitions in <dt-bindings/clock/r8a779?-clock.h> were superseded by those in <dt-bindings/clock/r8a779?-cpg-mssr.h> a long time ago. The last DTS user of these files was removed in commit 362b334b17943d84 ("ARM: dts: r8a7791: Convert to new CPG/MSSR bindings") in v4.15. Driver support for the old bindings was removed in commit 58256143cff7c2e0 ("clk: renesas: Remove R-Car Gen2 legacy DT clock support") in v5.5, so there is no point to keep on carrying these. Signed-off-by: Geert Uytterhoeven <[email protected]> Acked-by: Conor Dooley <[email protected]> Link: https://lore.kernel.org/d4abb688d666be35e99577a25b16958cbb4c3c98.1718796005.git.geert+renesas@glider.be
2024-06-24dt-bindings: clock: r8a7779: Remove duplicate newlineMarek Vasut1-1/+0
Drop duplicate newline. No functional change. Signed-off-by: Marek Vasut <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2024-06-24clk: renesas: Drop "Renesas" from individual driver descriptionsGeert Uytterhoeven1-2/+2
All configuration options are under the big "Renesas SoC clock support" umbrella, so there is no reason to repeat this for each driver. Hence drop "Renesas" from the few that do. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/185323de4d38b9b599775c1b64ce4171551b98d5.1718177124.git.geert+renesas@glider.be
2024-06-24clk: renesas: r8a779h0: Fix PLL2/PLL4 multipliers in commentsGeert Uytterhoeven1-3/+3
The multipliers for PLL2 and PLL4 as listed in the comments for the cpg_pll_configs[] array are incorrect. Fix them. Note that the actual values in the tables were correct. Fixes: f077cab34df3010d ("clk: renesas: cpg-mssr: Add support for R-Car V4M") Reported-by: Yoshihiro Shimoda <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Reviewed-by: Niklas Söderlund <[email protected]> Link: https://lore.kernel.org/07126b55807c1596422c9547e72f0a032487da1e.1718177076.git.geert+renesas@glider.be
2024-06-24staging: vc04_services: vchiq_arm: Fix initialisation checkKieran Bingham3-3/+13
The vchiq_state used to be obtained through an accessor which would validate that the VCHIQ had been initialised correctly with the remote, or return a null state. In commit 42a2f6664e18 ("staging: vc04_services: Move global g_state to vchiq_state") the global state was moved to the vchiq_mgnt structures stored as a vchiq instance specific context. This conversion removed the helpers and instead replaced users of this helper with the assumption that the state is always available and the remote connected. The conversion does ensure that the state is always available, so some remaining state null pointer checks that remain are unnecessary, but the assumption that the remote is present and initialised is incorrect. Fix this broken assumption by re-introducing the logic that was lost during the conversion. Fixes: 42a2f6664e18 ("staging: vc04_services: Move global g_state to vchiq_state") Signed-off-by: Kieran Bingham <[email protected]> Reviewed-by: Stefan Wahren <[email protected]> Reviewed-by: Umang Jain <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-06-24staging: vc04_services: Update testing instructionsStefan Wahren1-1/+44
Since the initial version of the testing instructions a few things has changed. So consider the latest arm64/defconfig changes and the new debugfs entry. Signed-off-by: Stefan Wahren <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-06-24staging: vchiq_arm: Don't cast scatter-gather elementsStefan Wahren1-3/+3
The kernel uses different types for DMA length & address, so better use them. Signed-off-by: Stefan Wahren <[email protected]> Reviewed-by: Laurent Pinchart <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-06-24staging: vchiq_core: Add hex prefix to debugfs outputStefan Wahren1-4/+4
The number format of VCHIQ debugfs isn't always clear. So let's add a prefix for all hex values, in order to make things clear. Signed-off-by: Stefan Wahren <[email protected]> Reviewed-by: Laurent Pinchart <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2024-06-24staging: vchiq_arm: Reduce indentation of service_callbackStefan Wahren1-29/+43
The service_callback has 5 levels of indentation, which makes it hard to read. Reduce this by splitting the code in a new function service_single_message() as suggested by Laurent Pinchart. Signed-off-by: Stefan Wahren <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>