aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2024-08-05pmdomain: core: Enable s2idle for CPU PM domains on PREEMPT_RTUlf Hansson2-2/+50
To allow a genpd provider for a CPU PM domain to enter a domain-idle-state during s2idle on a PREEMPT_RT based configuration, we can't use the regular spinlock, as they are turned into sleepable locks on PREEMPT_RT. To address this problem, let's convert into using the raw spinlock, but only for genpd providers that have the GENPD_FLAG_CPU_DOMAIN bit set. In this way, the lock can still be acquired/released in atomic context, which is needed in the idle-path for PREEMPT_RT. Do note that the genpd power-on/off notifiers may also be fired during s2idle, but these are already prepared for PREEMPT_RT as they are based on the raw notifiers. However, consumers of them may need to adopt accordingly to work properly on PREEMPT_RT. Signed-off-by: Ulf Hansson <[email protected]> Tested-by: Raghavendra Kakarla <[email protected]> # qcm6490 with PREEMPT_RT set Acked-by: Sebastian Andrzej Siewior <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2024-08-05pmdomain: amlogic: remove obsolete vpu domain driverJerome Brunet3-392/+0
meson-gx-pwrc-vpu has been superseded by meson-ee-pwrc since commit 53773f2dfd9c ("soc: amlogic: meson-ee-pwrc: add support for the Meson GX SoCs"), so v5.8. This driver is obsolete and no longer used or tested. There is no reason to keep it around so remove it. Signed-off-by: Jerome Brunet <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2024-08-05dt-bindings: can: fsl,flexcan: add common 'can-transceiver' for fsl,flexcanFrank Li1-0/+4
Add common 'can-transceiver' children node for fsl,flexcan. Fix below warning: arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dtb: can@2180000: 'can-transceiver' does not match any of the regexes: 'pinctrl-[0-9]+' from schema $id: http://devicetree.org/schemas/net/can/fsl,flexcan.yaml# Signed-off-by: Frank Li <[email protected]> Reviewed-by: Rob Herring (Arm) <[email protected]> Link: https://lore.kernel.org/all/[email protected] Signed-off-by: Marc Kleine-Budde <[email protected]>
2024-08-05pmdomain: imx: scu-pd: Remove duplicated clocksAlexander Stein1-5/+0
These clocks are already added to the list. Remove the duplicates ones. Fixes: a67d780720ff ("genpd: imx: scu-pd: add more PDs") Signed-off-by: Alexander Stein <[email protected]> Cc: [email protected] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2024-08-05net: usb: qmi_wwan: fix memory leak for not ip packetsDaniele Palmas1-0/+1
Free the unused skb when not ip packets arrive. Fixes: c6adf77953bc ("net: usb: qmi_wwan: add qmap mux protocol support") Signed-off-by: Daniele Palmas <[email protected]> Acked-by: Bjørn Mork <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-08-05Merge branch 'virtio-net-rq-coalescing' into mainDavid S. Miller1-2/+12
Heng Qi says: ==================== virtio-net: unbreak vq resizing if vq coalescing is not supported Currently, if the driver does not negotiate the vq coalescing feature but supports vq resize, the vq resize action, which could have been successfully executed, is interrupted due to the failure in configuring the vq coalescing parameters. This issue needs to be fixed. Changelog ========= v3->v4: - Add a comment for patch[2/2]. v2->v3: - Break out the feature check and the fix into separate patches. v1->v2: - Rephrase the subject. - Put the feature check inside the virtnet_send_{r,t}x_ctrl_coal_vq_cmd. ==================== Signed-off-by: David S. Miller <[email protected]>
2024-08-05virtio-net: unbreak vq resizing when coalescing is not negotiatedHeng Qi1-2/+6
Don't break the resize action if the vq coalescing feature named VIRTIO_NET_F_VQ_NOTF_COAL is not negotiated. Fixes: f61fe5f081cf ("virtio-net: fix the vq coalescing setting for vq resize") Signed-off-by: Heng Qi <[email protected]> Reviewed-by: Xuan Zhuo <[email protected]> Acked-by: Eugenio Pé rez <[email protected]> Acked-by: Jason Wang <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-08-05virtio-net: check feature before configuring the vq coalescing commandHeng Qi1-0/+6
Virtio spec says: The driver MUST have negotiated the VIRTIO_NET_F_VQ_NOTF_COAL feature when issuing commands VIRTIO_NET_CTRL_NOTF_COAL_VQ_SET and VIRTIO_NET_CTRL_NOTF_COAL_VQ_GET. So we add the feature negotiation check to virtnet_send_{r,t}x_ctrl_coal_vq_cmd as a basis for the next bugfix patch. Suggested-by: Michael S. Tsirkin <[email protected]> Signed-off-by: Heng Qi <[email protected]> Acked-by: Jason Wang <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-08-05gpio: vf610: add get_direction() supportHaibo Chen1-0/+19
For IP which do not contain PDDR, currently use the pinmux API pinctrl_gpio_direction_input() to config the output/input, pinmux currently do not support get_direction(). So here add the GPIO get_direction() support only for the IP which has Port Data Direction Register (PDDR). Signed-off-by: Haibo Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bartosz Golaszewski <[email protected]>
2024-08-05gpio: gpio-vf610: use u32 mask to handle 32 number gpiosHaibo Chen1-6/+6
This gpio controller support up to 32 pins per port. And all the register width is 32 bit. So here use u32 to replace the original unsigned long. Signed-off-by: Haibo Chen <[email protected]> Reviewed-by: Stefan Wahren <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bartosz Golaszewski <[email protected]>
2024-08-05drm/i915/display: correct dual pps handling for MTL_PCH+Dnyaneshwar Bhadane2-0/+6
On the PCH side the second PPS was introduced in ICP+.Add condition On MTL_PCH and greater platform also having the second PPS. Note that DG1/2 south block only has the single PPS, so need to exclude the fake DG1/2 PCHs Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11488 Fixes: 93cbc1accbce ("drm/i915/mtl: Add fake PCH for Meteor Lake") Cc: <[email protected]> # v6.9+ Signed-off-by: Dnyaneshwar Bhadane <[email protected]> Reviewed-by: Jani Nikula <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] (cherry picked from commit da1878b61c8d480c361ba6a39ce8a31c80b65826) Signed-off-by: Joonas Lahtinen <[email protected]>
2024-08-05wifi: ath12k: use 128 bytes aligned iova in transmit path for WCN7850Baochen Qiang4-0/+83
In transmit path, it is likely that the iova is not aligned to PCIe TLP max payload size, which is 128 for WCN7850. Normally in such cases hardware is expected to split the packet into several parts in a manner such that they, other than the first one, have aligned iova. However due to hardware limitations, WCN7850 does not behave like that properly with some specific unaligned iova in transmit path. This easily results in target hang in a KPI transmit test: packet send/receive failure, WMI command send timeout etc. Also fatal error seen in PCIe level: ... Capabilities: ... ... DevSta: ... FatalErr+ ... ... ... Work around this by manually moving/reallocating payload buffer such that we can map it to a 128 bytes aligned iova. The moving requires sufficient head room or tail room in skb: for the former we can do ourselves a favor by asking some extra bytes when registering with mac80211, while for the latter we can do nothing. Moving/reallocating buffer consumes additional CPU cycles, but the good news is that an aligned iova increases PCIe efficiency. In my tests on some X86 platforms the KPI results are almost consistent. Since this is seen only with WCN7850, add a new hardware parameter to differentiate from others. Tested-on: WCN7850 hw2.0 PCI WLAN.HMT.1.0.c5-00481-QCAHMTSWPL_V1.0_V2.0_SILICONZ-3 Signed-off-by: Baochen Qiang <[email protected]> Cc: <[email protected]> Tested-by: Mark Pearson <[email protected]> Signed-off-by: Kalle Valo <[email protected]> Link: https://patch.msgid.link/[email protected]
2024-08-05drm/i915/display: correct dual pps handling for MTL_PCH+Dnyaneshwar Bhadane2-0/+6
On the PCH side the second PPS was introduced in ICP+.Add condition On MTL_PCH and greater platform also having the second PPS. Note that DG1/2 south block only has the single PPS, so need to exclude the fake DG1/2 PCHs Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11488 Fixes: 93cbc1accbce ("drm/i915/mtl: Add fake PCH for Meteor Lake") Cc: <[email protected]> # v6.9+ Signed-off-by: Dnyaneshwar Bhadane <[email protected]> Reviewed-by: Jani Nikula <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-08-05firewire: ohci: use guard macro to serialize operations for isochronous contextsTakashi Sakamoto1-105/+77
The 1394 OHCI driver uses spinlock to serialize operations for isochronous contexts. This commit uses guard macro to maintain the spinlock. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Takashi Sakamoto <[email protected]>
2024-08-05firewire: ohci: use guard macro to maintain image of configuration ROMTakashi Sakamoto1-67/+49
The 1394 OHCI driver uses spinlock for the process to update local configuration ROM. This commit uses guard macro to maintain the spinlock. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Takashi Sakamoto <[email protected]>
2024-08-05firewire: ohci: use guard macro to maintain bus timeTakashi Sakamoto1-18/+12
The 1394 OHCI driver maintains bus time to respond to querying request. The concurrent access to the bus time is protected by spinlock. This commit uses guard macro to maintain the spinlock. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Takashi Sakamoto <[email protected]>
2024-08-05firewire: core: use guard macro to maintain properties of fw_cardTakashi Sakamoto6-33/+19
The core functions uses spinlock in instance of fw_card structure to protect concurrent access to properties in the instance. This commit uses guard macro to maintain the spinlock. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Takashi Sakamoto <[email protected]>
2024-08-05firewire: core: use guard macro to maintain list of asynchronous transactionTakashi Sakamoto1-51/+34
The core function maintains pending asynchronous transactions by list in the instance of fw_card. The concurrent access to the list is protected by spinlock in the instance. This commit uses guard macro to maintain the spinlock. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Takashi Sakamoto <[email protected]>
2024-08-05firewire: core: use guard macro to maintain list of receivers for phy ↵Takashi Sakamoto1-12/+5
configuration packets The core function maintains clients to receive phy configuration packets by list in the instance of fw_card. The concurrent access to the list is protected by spinlock in the instance. This commit uses guard macro to maintain the list. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Takashi Sakamoto <[email protected]>
2024-08-05firewire: core: use guard macro to maintain isochronous context for ↵Takashi Sakamoto1-14/+11
userspace client The core function allows one isochronous contexts per userspace client. The concurrent access to the context is protected by spinlock in the instance of client. This commit uses guard macro to maintain the spinlock. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Takashi Sakamoto <[email protected]>
2024-08-05firewire: core: use guard macro to maintain IDR of isochronous resources for ↵Takashi Sakamoto1-72/+59
userspace clients The core function provides UAPI to maintain isochronous resources allocated by userspace clients across bus resets automatically. The resources are maintained by IDR and the concurrent access to it is protected by spinlock in the instance of client. This commit uses guard macro to maintain the spinlock. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Takashi Sakamoto <[email protected]>
2024-08-05firewire: core: use guard macro to maintain list of events for userspace clientsTakashi Sakamoto1-15/+12
The core function maintains events to userspace by list in the instance of client. The concurrent access to the list is protected by spinlock in the instance. This commit uses guard macro to maintain the spinlock. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Takashi Sakamoto <[email protected]>
2024-08-05firewire: core: use guard macro to disable local IRQTakashi Sakamoto1-7/+5
The core function provides an operation for userspace application to retrieve current value of CYCLE_TIMER register with several types of system time. In the operation, local interrupt is disables so that the access of the register and ktime are done atomically. This commit uses guard macro to disable/enable local interrupts. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Takashi Sakamoto <[email protected]>
2024-08-05firewire: core: use guard macro to maintain the list of address handler for ↵Takashi Sakamoto1-6/+4
transaction The core function maintains address handlers by list. It is protected by spinlock to insert and remove entry to the list. This commit uses guard macro to maintain the spinlock. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Takashi Sakamoto <[email protected]>
2024-08-05firewire: core: use guard macro to access to IDR for fw_deviceTakashi Sakamoto2-56/+42
The core function maintains the instance of fw_device structure by IDR. The concurrent access to IDR is protected by static read/write semaphore. The semaphore is also utilized to protect concurrent access to the content of configuration ROM cached to the instance so that the cache is swapped to the latest one. This commit uses guard macro to maintain the mutex. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Takashi Sakamoto <[email protected]>
2024-08-05firewire: core: use guard macro to maintain RCU scope for transaction ↵Takashi Sakamoto1-20/+15
address handler The core function maintains address handlers by list. RCU is utilized for efficient read access to any entries in the list. This commit uses guard macro to maintain RCU locking and releasing. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Takashi Sakamoto <[email protected]>
2024-08-05firewire: ohci: use guard macro to serialize accesses to phy registersTakashi Sakamoto1-35/+36
The 1394 OHCI driver protects concurrent accesses to phy registers by mutex object in fw_ohci structure. This commit uses guard macro to maintain the mutex. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Takashi Sakamoto <[email protected]>
2024-08-05firewire: core: use guard macro to maintain the list of cdev clientsTakashi Sakamoto1-8/+5
The core function maintains userspace clients by the list in fw_device object associated to the operated character device. The concurrent access to the list is protected by mutex in the object. This commit uses guard macro to maintain the mutex. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Takashi Sakamoto <[email protected]>
2024-08-05firewire: core: use guard macro to maintain the list of cardTakashi Sakamoto1-26/+18
The core function maintains registered cards by list. The concurrent access to the list is protected by static mutex. This commit uses guard macro to maintain the mutex. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Takashi Sakamoto <[email protected]>
2024-08-05firewire: core: use guard macro to maintain static packet data for phy ↵Takashi Sakamoto1-3/+1
configuration The core function provide a kernel API to send phy configuration packet. Current implementation of the feature uses packet object allocated statically. The concurrent access to the object is protected by static mutex. This commit uses guard macro to maintain the mutex. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Takashi Sakamoto <[email protected]>
2024-08-05Merge tag 'drm-xe-next-2024-07-30' of ↵Dave Airlie94-1739/+3273
https://gitlab.freedesktop.org/drm/xe/kernel into drm-next drm-xe-next for 6.12 UAPI Changes: - Rename xe perf layer as xe observation layer, but was also made available via fixes to previous verison (Ashutosh) - Use write-back caching mode for system memory on DGFX, but was also mad available via fixes to previous version (Thomas) - Expose SIMD16 EU mask in topology query for userspace to know the type of EU, as available in PVC, Lunar Lake and Battlemage (Lucas) - Return ENOBUFS instead of ENOMEM in vm_bind if failure is tied to an array of binds (Matthew Brost) Driver Changes: - Log cleanup moving messages to debug priority (Michal Wajdeczko) - Add timeout to fences to adhere to dma_buf rules (Matthew Brost) - Rename old engine nomenclature to exec_queue (Matthew Brost) - Convert multiple bind ops to 1 job (Matthew Brost) - Add error injection for vm bind to help testing error path (Matthew Brost) - Fix error handling in page table to propagate correctly to userspace (Matthew Brost) - Re-organize and cleanup SR-IOV related registers (Michal Wajdeczko) - Make the device write barrier compatible with VF (Michal Wajdeczko) - New display workarounds for Battlemage (Matthew Auld) - New media workarounds for Lunar Lake and Battlemage (Ngai-Mint Kwan) - New graphics workarounds for Lunar Lake (Bommu Krishnaiah) - Tracepoint updates (Matthew Brost, Nirmoy Das) - Cleanup the header generation for OOB workarounds (Lucas De Marchi) - Fix leaking HDCP-related object (Nirmoy Das) - Serialize L2 flushes to avoid races (Tejas Upadhyay) - Log pid and comm on job timeout (José Roberto de Souza) - Simplify boilerplate code for live kunit (Michal Wajdeczko) - Improve kunit skips for live kunit (Michal Wajdeczko) - Fix xe_sync cleanup when handling xe_exec ioctl (Ashutosh Dixit) - Limit fair VF LMEM provisioning (Michal Wajdeczko) - New workaround to fence mmio writes in Lunar Lake (Tejas Upadhyay) - Warn on writes inaccessible register in VF (Michal Wajdeczko) - Fix register lookup in VF (Michal Wajdeczko) - Add GSC support for Battlemage (Alexander Usyskin) - Fix wedging only the GT in which timeout occurred (Matthew Brost) - Block device suspend when wedging (Matthew Brost) - Handle compression and migration changes for Battlemage (Akshata Jahagirdar) - Limit access of stolen memory for Lunar Lake (Uma Shankar) - Fail invalid addresses during user fence creation (Matthew Brost) - Refcount xe_file to safely and accurately store fdinfo stats (Umesh Nerlige Ramappa) - Cleanup and fix PM reference for TLB invalidation code (Matthew Brost) - Fix PM reference handling when communicating with GuC (Matthew Brost) - Add new BO flag for 2 MiB alignement and use in VF (Michal Wajdeczko) - Simplify MMIO setup for multi-tile platforms (Lucas De Marchi) - Add check for uninitialized access to OOB workarounds (Lucas De Marchi) - New GSC and HuC firmware blobs for Lunar Lake and Battlemage (Daniele Ceraolo Spurio) - Unify mmio wait logic (Gustavo Sousa) - Fix off-by-one when processing RTP rules (Lucas De Marchi) - Future-proof migrate logic with compressed PAT flag (Matt Roper) - Add WA kunit tests for Battlemage (Lucas De Marchi) - Test active tracking for workaorunds with kunit (Lucas De Marchi) - Add kunit tests for RTP with no actions (Lucas De Marchi) - Unify parse of OR rules in RTP (Lucas De Marchi) - Add performance tuning for Battlemage (Sai Teja Pottumuttu) - Make bit masks unsigned (Geert Uytterhoeven) Signed-off-by: Dave Airlie <[email protected]> From: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/k7xuktfav4zmtxxjr77glu2hszypvzgmzghoumh757nqfnk7kn@ccfi4ts3ytbk
2024-08-05arm64: dts: layerscape: fix thermal node names lengthKrzysztof Kozlowski6-9/+9
Linux kernel expects thermal zone node names to be maximum of 19 characters (see THERMAL_NAME_LENGTH, including terminating NUL byte) and bindings/dtbs_check points that: fsl-ls2088a-rdb.dtb: thermal-zones: 'core-cluster1-thermal', 'core-cluster2-thermal', 'core-cluster3-thermal', 'core-cluster4-thermal' do not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-]{1,10}-thermal$', 'pinctrl-[0-9]+' Name longer than 19 characters leads to driver probe errors when registering such thermal zone. Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-08-05pinctrl: s32cc: add update and overwrite options when setting pinconfAndrei Stefanescu1-7/+23
The previous pinconf settings(made by the bootloader) need to be overwritten when configuring the pinctrl of a driver during the boot process. Configuring the bias of a GPIO at runtime (e.g. pull-up) needs to preserve the other settings unaltered. This patch introduces changes to differentiate between the two cases. Signed-off-by: Radu Pirea <[email protected]> Signed-off-by: Florin Buica <[email protected]> Signed-off-by: Andrei Stefanescu <[email protected]> Link: https://lore.kernel.org/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-08-05pinctrl: s32cc: configure PIN_CONFIG_DRIVE_PUSH_PULLAndrei Stefanescu1-0/+4
Previously, it was possible to only configure the open-drain for a pin. However, after a pin got configured with open-drain, there wasn't any way to disable it. Add the push-pull configuration in order to reverse the open-drain configuration. Signed-off-by: Florin Buica <[email protected]> Signed-off-by: Andrei Stefanescu <[email protected]> Link: https://lore.kernel.org/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-08-05pinctrl: s32cc: enable the input buffer for a GPIOAndrei Stefanescu1-9/+8
The IBE (input buffer enable) should be enabled for a GPIO. Reading the value will return the one from the input register, writing the value will return the one from the output register. This offers the flexibility to check if the value intended to be set matches the actual physical one. Signed-off-by: Florin Buica <[email protected]> Signed-off-by: Andrei Stefanescu <[email protected]> Link: https://lore.kernel.org/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-08-05arm64: dts: imx8mm-venice-gw72xx-0x: Remove compatible from dtsoFabio Estevam3-12/+0
There is no need to describe the compatible string inside a dtso file. dt-schema produces super verbose warnings about that. Signed-off-by: Fabio Estevam <[email protected]> Acked-by: Parthiban Nallathambi <[email protected]> Acked-by: Tim Harvey <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-08-05arm64: dts: imx8mm-phygate-tauri-l: Remove compatible from dtsoFabio Estevam3-16/+0
There is no need to describe the compatible string inside a dtso file. dt-schema produces super verbose warnings about that. Signed-off-by: Fabio Estevam <[email protected]> Acked-by: Parthiban Nallathambi <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-08-05arm64: dts: imx95-19x19-evk: add pwm fan controlFrank Li1-0/+61
Add pwm fan and overwrite default thermal nodes. Signed-off-by: Frank Li <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-08-05arm64: dts: imx95: add thermal_zone labelFrank Li1-1/+1
Add thermal_zone label because it may be overwrite by board level dts file. Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Frank Li <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-08-05arm64: dts: imx95-19x19-evk: add flexspi and child nodeFrank Li1-0/+41
Add flexspi and child flash node. Signed-off-by: Frank Li <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-08-05arm64: dts: imx95: add flexspi nodeFrank Li1-0/+16
Add flexspi support. Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Frank Li <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-08-05arm64: dts: imx95-19x19-evk: Add audio related nodesFrank Li1-0/+238
Add sai1, sai2. Add i2c4 and wm8962 and other dependent nodes. Signed-off-by: Frank Li <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-08-05arm64: dts: imx95: add sai[1..6], xcvr and micfillFrank Li1-0/+111
Add sai[1..6], NXP Audio Transceiver (XCVR) Controller and MICFIL Digital Audio Interface (MICFIL). Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Frank Li <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-08-05arm64: dts: imx95: add edma[1..3] nodesFrank Li1-0/+235
Add eDMA1, eDMA2 and eDMA3 support for iMX95. Add dmas and dma-names for each peripheral, which use eDMA. Signed-off-by: Frank Li <[email protected]> Reviewed-by: Peng Fan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2024-08-05ALSA: hda: cs35l41: Stop creating ALSA Controls for firmware coefficientsStefan Binding1-13/+0
When the CS35L41 loads its firmware, it has a number of controls to affect its behaviour. Currently, these controls are exposed as ALSA Controls. These controls were never intended to be exposed to users but the firmware doesn't mark them hidden, so make the driver ignore them. Any changes in the coefficients handled by these controls needs to be matched to the individual system by SSID, which is already handled using the tuning file, when firmware is loaded, so UCM should not be setting these controls anyway. Signed-off-by: Stefan Binding <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Takashi Iwai <[email protected]>
2024-08-05ALSA: hda: cs35l56: Stop creating ALSA controls for firmware coefficientsSimon Trimmer2-38/+1
A number of laptops have gone to market with old firmware versions that export controls that have since been hidden, but we can't just install a newer firmware because the firmware for each product is customized and qualified by the OEM. The issue is that alsactl save and restore has no idea what controls are good to persist which can lead to misconfiguration. There is no reason that the UCM or user should need to interact with any of the ALSA controls for the firmware coefficients so they can be removed entirely, this also simplifies the driver. Signed-off-by: Simon Trimmer <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Takashi Iwai <[email protected]>
2024-08-05media: vivid: add <Vendor Command With ID> supportHans Verkuil1-3/+45
This makes it possible to test the new CEC_MSG_FL_REPLY_VENDOR_ID flag. The vivid driver will Feature Abort any messages that do not have exactly 1 payload byte. It ignores messages where the payload byte is even, and where it is odd it will reply with the payload byte incremented by 1. Basically a simple ping-pong command. Signed-off-by: Hans Verkuil <[email protected]> Signed-off-by: Mauro Carvalho Chehab <[email protected]>
2024-08-05media: cec: core: add new CEC_MSG_FL_REPLY_VENDOR_ID flagHans Verkuil6-16/+64
If this flag is set, then the reply is expected to consist of the CEC_MSG_VENDOR_COMMAND_WITH_ID opcode followed by the Vendor ID (as used in bytes 1-4 of the message), followed by the struct cec_msg reply field. Note that this assumes that the byte after the Vendor ID is a vendor-specific opcode. This flag makes it easier to wait for replies to vendor commands, using the same CEC framework support for waiting for regular replies. Support for this flag is indicated by setting the new CEC_CAP_REPLY_VENDOR_ID capability. Signed-off-by: Hans Verkuil <[email protected]> Signed-off-by: Mauro Carvalho Chehab <[email protected]>
2024-08-05pinctrl: nuvoton: npcm8xx: modify pins flagsTomer Maimon1-18/+18
Modify the following pins flags on the Nuvoton NPCM8XX BMC: - Add pins 110-113, 187, 191, 192, 194-199, 202 SLEW flag - Add pins 229 and 230 GPO flag. - Remove pin 233 SLEWLPC flag. - Remove pin 251 SLEW flag. Signed-off-by: Tomer Maimon <[email protected]> Link: https://lore.kernel.org/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2024-08-05pinctrl: nuvoton: npcm8xx: modify clkrun and serirq pin configurationTomer Maimon1-2/+2
Modify clkrun and serirq pin configuration on the Nuvoton NPCM8XX BMC SoC. Signed-off-by: Tomer Maimon <[email protected]> Link: https://lore.kernel.org/[email protected] Signed-off-by: Linus Walleij <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.