Age | Commit message (Collapse) | Author | Files | Lines |
|
Add atom_smc_dpm_info_v4_10 that defines board parameters for aldebaran
Signed-off-by: Lijo Lazar <[email protected]>
Reviewed-by: Kenneth Feng <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
Disable PCIe BAR resizing on A+A config. It's not needed because we won't use the
PCIe BAR, but it breaks the PCI BAR configuration with the current SBIOS.
Error message of FB BAR resize failure under A+A:
[ 154.913731] [drm:amdgpu_device_resize_fb_bar [amdgpu]] *ERROR* Problem resizing BAR0 (-22).
Signed-off-by: Oak Zeng <[email protected]>
Reviewed-by: Amber Lin <[email protected]>
Reviewed-by: Felix Kuehling <[email protected]>
Reviewed-by: Christian Koenig <[email protected]>
Tested-by: Amber Lin <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
For A+A configuration, device memory is supposed to be mapped as
cachable from CPU side. For kernel pre-map gpu device memory using
ioremap_cache
Signed-off-by: Oak Zeng <[email protected]>
Reviewed-by: Christian Koenig <[email protected]>
Tested-by: Amber Lin <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
v1: Added some pspbl parameters
v2: fix fallthrough issue
Signed-off-by: Feifei Xu <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Reviewed-by: Kevin Wang <[email protected]>
Reviewed-by: Lazar Lijo <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
for SMU config.
Signed-off-by: Feifei Xu <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
shall revisit the change later
Signed-off-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
replace vega10 ih block with vega20 ih block for
aldebaran.
Signed-off-by: Hawking Zhang <[email protected]>
Acked-by: Christian König <[email protected]>
Acked-by: Felix Kuehling <[email protected]>
Reviewed-by: Dennis Li <[email protected]>
Reviewed-by: Feifei Xu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
For aldebaran, psp firmware won't program IH_CHICKEN.
it now depends on driver to program it properly so
either bus address or gpu virtual address is just
working for ih ring.
Signed-off-by: Hawking Zhang <[email protected]>
Acked-by: Christian König <[email protected]>
Acked-by: Felix Kuehling <[email protected]>
Reviewed-by: Dennis Li <[email protected]>
Reviewed-by: Feifei Xu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
The callback will be invoked to query mmea error
status when needed.
Signed-off-by: Hawking Zhang <[email protected]>
Reviewed-by: Dennis Li<[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
The callback will be invoked to reset mmhub ras error
counters when needed.
Signed-off-by: Hawking Zhang <[email protected]>
Reviewed-by: Dennis Li<[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
The callback will be invoked to harvest all kinds
of mmhub ras error
Signed-off-by: Hawking Zhang <[email protected]>
Reviewed-by: Dennis Li<[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
The callback will be invoked to reset sdma ras error
counters when needed.
Signed-off-by: Hawking Zhang <[email protected]>
Reviewed-by: Dennis Li<[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
The callback will be invoked to harvest all kinds
of sdma ras error
Signed-off-by: Hawking Zhang <[email protected]>
Reviewed-by: Dennis Li<[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
sdma ras function is the main structure to support
sdma ras on aldebaran. the patch initializes late_init
late_fini callbacks.
Signed-off-by: Hawking Zhang <[email protected]>
Reviewed-by: Dennis Li<[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
perform one-time initialization for sdma registers
Signed-off-by: Hawking Zhang <[email protected]>
Reviewed-by: Kevin Wang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
Similar as xgmi connected gpu nodes, physical_node_id
* segment_size should be used to calculate the offset
of aper_base.
The asic type check is redundant. once physical_node_id
and segment_size are initialized, it should be count
on.
Signed-off-by: Hawking Zhang <[email protected]>
Reviewed-by: Kevin Wang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
there won't be any gds useage in either kernel or
pm4 anymore for aldebaran.
Signed-off-by: Hawking Zhang <[email protected]>
Reviewed-by: Feifei Xu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
aldebaran removed gds internal memory for atomic usage.
it only supports gws opcode in kernel like barrier,
semaphore.etc. there won't be usage of gds in either
kernel or pm4 packet. max_wave_id should also be marked
as deprecated for aldebaran.
Signed-off-by: Hawking Zhang <[email protected]>
Reviewed-by: Feifei Xu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
correct atom_vram_info_header_v2_6 and its vram_module.
Signed-off-by: Feifei Xu <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
Query vram_type, channel_num, channel_width
information through atomfirmware i/f
Signed-off-by: Hawking Zhang <[email protected]>
Reviewed-by: Feifei Xu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
Will remove once validation finished.
Signed-off-by: Feifei Xu <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
Use MSG_GfxDriverReset for mode reset and retire MSG_Mode1Reset.
Centralize soc15_asic_mode1_reset() and nv_asic_mode1_reset()functions.
Add mode2_reset_is_support() for smu->ppt_funcs.
Signed-off-by: Feifei Xu <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
Add 0x7408,0x740C,0x740F in pciidlist.
Signed-off-by: Feifei Xu <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
call host to psp cmd to load reg list
v2: update to latest interface (Alex)
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: John Clements <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
updated psp bin parsing and load register list
v2: update to latest interface (Alex)
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: John Clements <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
added host to psp cmd for register list
v2: update to new interface (Alex)
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: John Clements <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
fix -Wmissing-protoypes warning
Signed-off-by: Hawking Zhang <[email protected]>
Reviewed-by: Likun Gao <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
add exteranal rev_id for aldebaran
Signed-off-by: Hawking Zhang <[email protected]>
Reviewed-by: Kevin Wang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
declare sdma firmware binary file for aldebaran
Signed-off-by: Kevin Wang <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
Add initial swSMU support.
v1: add smu13 ip support for aldebaran asic (Kevin/Kenneth)
v2: switch to thm/mp v13_0 ip headers (Hawking)
v3: squash in updates (Alex)
Signed-off-by: Kevin Wang <[email protected]>
Signed-off-by: Kenneth Feng <[email protected]>
Reviewed-by: Kenneth Feng <[email protected]>
Signed-off-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
add aldebaran smu13 driver if header
v2: squash in updates
Signed-off-by: Kevin Wang <[email protected]>
Signed-off-by: Kenneth Feng <[email protected]>
Reviewed-by: Kenneth Feng <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
vcn fw front door loading is not functional. comments
out vcn/jpeg ip blocks so people can load amdgpu driver
without specify ip_mask module parameter.
Signed-off-by: Hawking Zhang <[email protected]>
Reviewed-by: Kevin Wang <[email protected]>
Reviewed-by: James Zhu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
only xgmi ta is supported at this stage
Signed-off-by: Hawking Zhang <[email protected]>
Reviewed-by: Kevin Wang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
switch to use register distance member for mmhub v1_7
instead of hardcode
Signed-off-by: Kevin Wang <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
Add more function pointers to amdgpu_mmhub_funcs. ASIC specific
implementation of most mmhub functions are called from a general
function pointer, instead of calling different function for
different ASIC.
V2: Split patch into upstreamable and aldebaran
Signed-off-by: Oak Zeng <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Rajneesh Bhardwaj <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
enable JPEG on aldebaran
Signed-off-by: James Zhu <[email protected]>
Reviewed-by: Leo Liu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
Enable VCN on aldebaran
Signed-off-by: James Zhu <[email protected]>
Reviewed-by: Leo Liu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
Aldebaran has a new mmBIF_MMSCH1_DOORBELL_RANGE setting.
Signed-off-by: James Zhu <[email protected]>
Reviewed-by: Leo Liu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
MEC2_JT is not supported
Signed-off-by: Hawking Zhang <[email protected]>
Reviewed-by: Le Ma <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
The macro is for memory mapped by GPU as uncached.
Signed-off-by: Eric Huang <[email protected]>
Reviewed-by: Oak Zeng <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
To support new cache coherence HW on A+A platform mainly in KFD.
Signed-off-by: Eric Huang <[email protected]>
Reviewed-by: Oak Zeng <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
Aldebaran is using jpeg2.6, and the main change is jpeg2.6 using
AMDGPU_MMHUB_0, and jpeg2.5 using AMDGPU_MMHUB_1.
Signed-off-by: James Zhu <[email protected]>
Reviewed-by: Leo Liu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
Aldebaran should be the same as Arcturus in the PTE SNOOPED bit handling.
Signed-off-by: Yong Zhao <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
Client ID 26 is reserved. Add it to the table.
Signed-off-by: Oak Zeng <[email protected]>
Reviewed-by: Le Ma <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
Aldebaran is using vcn2.6, and the main change is vcn2.6 using
AMDGPU_MMHUB_0, and vcn2.5 using AMDGPU_MMHUB_1
Signed-off-by: James Zhu <[email protected]>
Reviewed-by: Leo Liu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
including firmware support etc.
Signed-off-by: James Zhu <[email protected]>
Reviewed-by: Leo Liu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
Currently host-gpu io link is always reported as PCIe however, on some
A+A systems, there could be one xgmi link available. This change exposes
xgmi link via sysfs when it is present.
v2: fix includes (Alex)
Reviewed-by: Oak Zeng <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Rajneesh Bhardwaj <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
Aldebaran uses registers defined in header gc_9_4_2 but much of the xgmi
related functionality can be obtained by reusing the exisitng definition
from gfxhub_v1_1_get_xgmi_info. While adding support for Aldebaran, also
refactored code to better handle the new scenario.
Signed-off-by: Rajneesh Bhardwaj <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
This applies to AMD Accelerated Processing Platforms that support host
gpu interconnect throguh a special link (xgmi). Aldebaran systems will
support this special feature for utilizing the benefits of host-gpu
cache coherence. This change outlines the basic framework for mapping
the GPU VRAM (HBM) to system address space making it accesible to the
host but managed by the amdgpu driver since this region is marked as
reserved memory in host address space by the underlying system firmware.
v2: switch to smuio callback function to check the type
of host-gpu interface (Hawking)
v3: use hub callbacks rather than direct function calls (Alex)
Reviewed-by: Oak Zeng <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Rajneesh Bhardwaj <[email protected]>
Signed-off-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|
|
Like its predecessors Aldebran also supports advanced high bandwidth
GPU-GPU communication interface known as xgmi. This enables the basic
xgmi support while refactoring the code slightly.
Detection of xgmi link between host cpu and gpu will be introduced in a
different patch.
Reviewed-by: Oak Zeng <[email protected]>
Reviewed-by: Christian König <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Rajneesh Bhardwaj <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
|