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2020-09-17arm64: dts: qcom: sm8250: Add cpufreq hw nodeBjorn Andersson1-0/+22
Add cpufreq HW device node to scale 4-Silver/3-Gold/1-Gold+ cores on SM8250 SoCs. Signed-off-by: Bjorn Andersson <[email protected]> Signed-off-by: Manivannan Sadhasivam <[email protected]> Acked-by: Viresh Kumar <[email protected]> Reviewed-by: Amit Kucheria <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-09-16ARM: dts: s5pv210: replace deprecated "gpios" i2c-gpio property in GoniKrzysztof Kozlowski1-2/+2
"gpios" property is deprecated. Update the Goni DTS to fix dtbs_checks warnings like: i2c-pmic: 'sda-gpios' is a required property i2c-pmic: 'scl-gpios' is a required property Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-16ARM: dts: s5pv210: replace deprecated "gpios" i2c-gpio property in AquilaKrzysztof Kozlowski1-2/+2
"gpios" property is deprecated. Update the Aquila DTS to fix dtbs_checks warnings like: i2c-pmic: 'sda-gpios' is a required property i2c-pmic: 'scl-gpios' is a required property Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-16ARM: dts: s5pv210: move fixed regulators under root node in GoniKrzysztof Kozlowski1-37/+27
The fixed regulators are kept under dedicated "regulators" node but this causes multiple dtschema warnings: regulators: $nodename:0: 'regulators' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' regulators: #size-cells:0:0: 0 is not one of [1, 2] regulators: fixed-regulator@0:reg:0: [0] is too short regulators: fixed-regulator@1:reg:0: [1] is too short regulators: fixed-regulator@2:reg:0: [2] is too short regulators: fixed-regulator@3:reg:0: [3] is too short Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-16ARM: dts: s5pv210: move fixed regulators under root node in AquilaKrzysztof Kozlowski1-28/+19
The fixed regulators are kept under dedicated "regulators" node but this causes multiple dtschema warnings: regulators: $nodename:0: 'regulators' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' regulators: #size-cells:0:0: 0 is not one of [1, 2] regulators: fixed-regulator@0:reg:0: [0] is too short regulators: fixed-regulator@1:reg:0: [1] is too short regulators: fixed-regulator@2:reg:0: [2] is too short Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-16arm64: dts: exynos: Align OPP table name with dt-schemaKrzysztof Kozlowski1-1/+1
Device tree nodes should have hyphens instead of underscores. This is also expected by the bindings. Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-16ARM: dts: exynos: Align OPP table name with dt-schemaKrzysztof Kozlowski2-9/+9
Device tree nodes should have hyphens instead of underscores. This is also expected by the bindings. Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-16arm64: dts: sparx5: Add spi-nand devicesLars Povlsen5-0/+67
This patch add spi-nand DT nodes to the applicable Sparx5 boards. Signed-off-by: Lars Povlsen <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-16arm64: dts: sparx5: Add spi-nor supportLars Povlsen3-0/+80
This add spi-nor device nodes to the Sparx5 reference boards. Signed-off-by: Lars Povlsen <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-16ARM: dts: at91: sama5d2: add missing flexcom spi node propertiesAlexandre Belloni1-0/+10
SPI nodes require #address-cells and #size-cells add those properties in the flexcom spi nodes. Signed-off-by: Alexandre Belloni <[email protected]> Reviewed-by: Nicolas Ferre <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-16ARM: dts: at91: add unit-address to memory nodeAlexandre Belloni51-51/+51
The memory node requires a unit-address, add it. Signed-off-by: Alexandre Belloni <[email protected]> Reviewed-by: Nicolas Ferre <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-16ARM: dts: at91: move mmc pinctrl-names property to board dtsAlexandre Belloni20-8/+17
Having the pinctrl-names property in the dtsi leads to dtbs_check warnings when the board dts doesn't define pinctrl-0. Instead, move the property to the board dts actually using the mmc node. Signed-off-by: Alexandre Belloni <[email protected]> Reviewed-by: Nicolas Ferre <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-16arm64: dts: sparx5: Add SPI controller and associated mmio-muxLars Povlsen1-0/+30
This adds a SPI controller to the Microchip Sparx5 SoC, as well as the mmio-mux that is required to select the right SPI interface for a given SPI device. Signed-off-by: Lars Povlsen <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-16MAINTAINERS: Add git tree for Sparx5Lars Povlsen1-0/+1
This adds a git tree for maintaining the Sparx5 SoC from. Signed-off-by: Lars Povlsen <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-16arm64: dts: sparx5: Add hwmon temperature sensorLars Povlsen1-0/+7
This adds a hwmon temperature node sensor to the Sparx5 SoC. Signed-off-by: Lars Povlsen <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-16arm64: dts: sparx5: Add Sparx5 eMMC supportLars Povlsen4-0/+93
This adds eMMC support to the applicable Sparx5 board configuration files. Signed-off-by: Lars Povlsen <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-15arm64: dts: qcom: sdm845: Add interconnects property for displayGeorgi Djakov1-0/+4
Add the interconnect paths that are used by the display (MDSS). This will allow the driver to request the needed bandwidth and prevent display flickering. Signed-off-by: Georgi Djakov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-09-15arm64: dts: qcom: sm8250: Add EPSS L3 interconnect providerSibi Sankar1-0/+11
Add Epoch Subsystem (EPSS) L3 interconnect provider node on SM8250 SoCs. Signed-off-by: Sibi Sankar <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-09-15arm64: dts: qcom: sm8150: Add OSM L3 interconnect providerSibi Sankar1-0/+11
Add Operation State Manager (OSM) L3 interconnect provider node on SM8150 SoCs. Acked-by: Georgi Djakov <[email protected]> Signed-off-by: Sibi Sankar <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-09-15arm64: dts: qcom: sm8250: add interconnect nodesJonathan Marek1-0/+81
Add the interconnect dts nodes for sm8250. Signed-off-by: Jonathan Marek <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-09-15arm64: dts: qcom: sm8150: add interconnect nodesJonathan Marek1-0/+81
Add the interconnect dts nodes for sm8150. Reviewed-by: Sibi Sankar <[email protected]> Signed-off-by: Jonathan Marek <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-09-15arm64: dts: qcom: sc7180: Increase the number of interconnect cellsSibi Sankar1-109/+109
Increase the number of interconnect-cells, as now we can include the tag information. The consumers can specify the path tag as an additional argument to the endpoints. Signed-off-by: Sibi Sankar <[email protected]> Tested-by: Matthias Kaehlcke <[email protected]> Reviewed-by: Matthias Kaehlcke <[email protected]> Signed-off-by: Georgi Djakov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-09-15arm64: dts: qcom: sdm845: Increase the number of interconnect cellsGeorgi Djakov1-24/+24
Increase the number of interconnect-cells, as now we can include the tag information. The consumers can specify the path tag as an additional argument to the endpoints. Tested-by: Sibi Sankar <[email protected]> Reviewed-by: Sibi Sankar <[email protected]> Reviewed-by: Matthias Kaehlcke <[email protected]> Signed-off-by: Georgi Djakov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-09-15arm64: dts: qcom: Makefile: Sort linesStephan Gerhold1-5/+5
The Makefile is in a bit of a weird order at the moment. It's almost sorted alphabetically, but not entirely. Also, one element uses a space before the += instead of a tab. Fix this up and sort the lines alphabetically so we have a consistent order in the Makefile. Signed-off-by: Stephan Gerhold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-09-15arm64: dts: qcom: pm8916: Sort nodesStephan Gerhold1-30/+30
Sort nodes by unit address so we have a consistent order in pm8916.dtsi. Signed-off-by: Stephan Gerhold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-09-15arm64: dts: qcom: msm8916: Sort nodesStephan Gerhold1-1107/+1107
Just like in commit 50aa72ccb30b ("arm64: dts: qcom: msm8996: Sort all nodes in msm8996.dtsi"), sort all the nodes by unit address, then alphabetically by their name. Signed-off-by: Stephan Gerhold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-09-15arm64: dts: qcom: msm8916: Pad addressesStephan Gerhold1-69/+69
Just like in commit 86f6d6225e5e ("arm64: dts: qcom: msm8996: Pad addresses"), pad all addresses to 8 digits to make it easier to see the correct order of the nodes. Signed-off-by: Stephan Gerhold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-09-15arm64: dts: qcom: msm8916: Rename "x-smp2p" to "smp2p-x"Stephan Gerhold1-2/+2
This allows grouping them together when sorting nodes alphabetically. Signed-off-by: Stephan Gerhold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-09-15arm64: dts: qcom: msm8916: Use more generic node namesStephan Gerhold3-17/+17
Now that all MSM8916 boards are referencing nodes by label instead of name, we can easily make some more nodes use more generic names (as recommended in the device tree specification or the binding documentation). Signed-off-by: Stephan Gerhold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-09-15arm64: dts: qcom: msm8916: Add MSM8916-specific compatibles to SCM/MSSStephan Gerhold1-2/+2
Over the time, the SCM and MSS driver were refactored to use SoC-specific compatibles. While the generic compatibles still work correctly, add the MSM8916-specific compatibles so they are actually used somewhere. For SCM this will ensure that we actually manage to obtain all three of the specified clocks, since those are required on MSM8916. Signed-off-by: Stephan Gerhold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-09-15arm64: dts: qcom: msm8916: Minor style fixesStephan Gerhold1-13/+13
Fix usages of spaces for indentation, break a long line and remove duplicate new lines. Add some spaces where appropriate. Signed-off-by: Stephan Gerhold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-09-15arm64: dts: qcom: msm8916: Drop qcom,tcsr-mutex sysconStephan Gerhold1-8/+3
The hwlock device node does not (directly) use memory resources of the SoC, so we should move it outside the "soc" node. However, as of commit 7a1e6fb1c606 ("hwspinlock: qcom: Allow mmio usage in addition to syscon") we can now assign the memory region directly to the hwlock device node. This works because the register space used by it is actually separate and not used by any other components. Signed-off-by: Stephan Gerhold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-09-15arm64: dts: qcom: msm8916: Use IRQ defines, add IRQ typesStephan Gerhold1-18/+20
dt-bindings/interrupt-controller/arm-gic.h has a GIC_SPI define that allows specifying interrupts more clearly, but right now only some device nodes in msm8916.dtsi make use of it. Convert all others to use it. The same applies to the IRQ_TYPE_* defines in dt-bindings/interrupt-controller/irq.h. Some interrupts were defined with raw numbers, or even with IRQ_TYPE_NONE (0). Convert all these to use appropriate IRQ types. Signed-off-by: Stephan Gerhold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-09-15arm64: dts: qcom: msm8916: Fix MDP/DSI interruptsStephan Gerhold1-2/+2
The mdss node sets #interrupt-cells = <1>, so its interrupts should be referenced using a single cell (in this case: only the interrupt number). However, right now the mdp/dsi node both have two interrupt cells set, e.g. interrupts = <4 0>. The 0 is probably meant to say IRQ_TYPE_NONE (= 0), but with #interrupt-cells = <1> this is actually interpreted as a second interrupt line. Remove the IRQ flags from both interrupts to fix this. Fixes: 305410ffd1b2 ("arm64: dts: msm8916: Add display support") Signed-off-by: Stephan Gerhold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-09-15arm64: dts: qcom: pm8916: Remove invalid reg size from wcd_codecStephan Gerhold1-1/+1
Tha parent node of "wcd_codec" specifies #address-cells = <1> and #size-cells = <0>, which means that each resource should be described by one cell for the address and size omitted. However, wcd_codec currently lists 0x200 as second cell (probably the size of the resource). When parsing this would be treated like another memory resource - which is entirely wrong. To quote the device tree specification [1]: "If the parent node specifies a value of 0 for #size-cells, the length field in the value of reg shall be omitted." [1]: https://www.devicetree.org/specifications/ Fixes: 5582fcb3829f ("arm64: dts: apq8016-sbc: add analog audio support with multicodec") Signed-off-by: Stephan Gerhold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-09-15arm64: dts: qcom: msm8916: Remove one more thermal trip point unit nameStephan Gerhold1-3/+3
Commit fe2aff0c574d2 ("arm64: dts: qcom: msm8916: remove unit name for thermal trip points") removed the unit names for most of the thermal trip points defined in msm8916.dtsi, but missed to update the one for cpu0_1-thermal. So why wasn't this spotted by "make dtbs_check"? Apparently, the name of the thermal zone is already invalid: thermal-zones.yaml specifies a regex of ^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$, so it is not allowed to contain underscores. Therefore the thermal zone was never verified using the DTB schema. After replacing the underscore in the thermal zone name, the warning shows up: apq8016-sbc.dt.yaml: thermal-zones: cpu0-1-thermal:trips: 'trip-point@0' does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+' Fix up the thermal zone names and remove the unit name for the trip point. Cc: Amit Kucheria <[email protected]> Fixes: fe2aff0c574d2 ("arm64: dts: qcom: msm8916: remove unit name for thermal trip points") Signed-off-by: Stephan Gerhold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-09-15arm64: dts: qcom: msm8916: Configure DSI port with labelsStephan Gerhold2-17/+7
&dsi0 -> ports -> port@1 -> endpoint already has the "dsi0_out" label, so we can use it for configuring instead of replicating the entire node hierarchy. Looks like I missed that when converting the boards. Signed-off-by: Stephan Gerhold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-09-15arm64: dts: sm8250: Add OPP table for all qup devicesDmitry Baryshkov1-0/+69
qup has a requirement to vote on the performance state of the CX domain in sm8250 devices. Add OPP tables for these and also add power-domains property for all qup instances for uart and spi. i2c does not support scaling and uses a fixed clock. Acked-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-09-15arm64: dts: qcom: msm8996: Add VFE1_GDSC power domain to camss nodeRobert Foss1-1/+2
As the MSM8996 has two VFE IP-blocks, and each has a power domain, both of them have to be enabled. Previously only the power domain of VFE0 was enabled, but not the domain for VFE1. This patch adds the VFE1_GDSC power domain to the camss device tree node of the MSM8996 soc. Signed-off-by: Robert Foss <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-09-15arm64: dts: renesas: r8a77990: Add DRIF supportFabrizio Castro1-0/+120
Add the DRIF controller nodes for the r8a77990 (a.k.a. R-Car E3). Please note that R-Car E3 has register BITCTR located at offset 0x80 (this register is not available on the r8a77960 and r8a77951, whose support has already been upstreamed), and even though it is not dealt with just yet within the driver, we have to keep that into account with our device tree nodes. Also, please note that while testing it has emerged that the HW User Manual has the wrong DMA details for DRIF2 and DRIF3 on E3, as they are only allowed SYS-DMAC0 rather than SYS-DMAC1 and SYS-DMAC2. An errata addressing this issue will be available soon. Signed-off-by: Fabrizio Castro <[email protected]> Reviewed-by: Chris Paterson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2020-09-15ARM: dts: r8a7742-iwg21d-q7-dbcm-ca: Add can0 support to camera DBLad Prabhakar1-0/+11
This patch enables CAN0 interface exposed through connector J4 on the camera DB. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Chris Paterson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2020-09-15ARM: dts: r8a7742: Add VSP supportLad Prabhakar1-0/+36
Add VSP support to R8A7742 (RZ/G1H) SoC dtsi. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Chris Paterson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2020-09-15arm64: dts: renesas: Drop superfluous pin configuration containersGeert Uytterhoeven2-8/+4
As the pin configuration child nodes for EtherAVB on the Draak and Ebisu boards contain only a single configuration, there is no need to wrap them in additional grandchild containers. Hence remove the superfluous level. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-15arm64: dts: qcom: msm8916: Move common USB properties to msm8916.dtsiStephan Gerhold4-11/+3
Right now we define "hnp-disable", "srp-disable", "adp-disable" separately for every MSM8916 board that has USB working. They are needed for USB to work properly if CONFIG_USB_OTG_FSM is enabled. This is because the chipidea OTG FSM code waits for interrupts regarding the VBUS state (AVVIS). Those never happen on MSM8916 because VBUS is always connected to the PMIC instead of the USB controller. There was a patch [1] to work around this but ultimately it was decided that it's easier to disable the OTG FSM altogether using these properties. This works fine for most use cases, because the OTG FSM isn't needed for simple dual role host/gadget operation. Given that these properties are needed for every MSM8916 device, move them to msm8916.dtsi so we can avoid some more duplication. [1]: https://lore.kernel.org/lkml/[email protected]/ Signed-off-by: Stephan Gerhold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-09-15arm64: dts: qcom: msm8916: Set default pinctrl for blsp1_uart1/2Stephan Gerhold5-22/+9
Right now some device nodes set default pinctrl within msm8916.dtsi (e.g. I2C, SPI), but for others it needs to be explicitly set in the board-specific device tree (e.g. UART). While it is theoretically possible that some super special board needs different pinctrl for these, in practice pretty much every board ends up using the common pinctrl definitions. Make this consistent by also defining the common pinctrl properties for blsp1_uart1 and blsp1_uart2 so we don't need to copy this for every board. If there is really such a super special board it could just override these properties with custom pinctrl or make minor modifications to the common pinctrl configurations provided by msm8916-pins.dtsi. Also move #address-cells/#size-cells for &dsi0 to msm8916.dtsi since this is specific to the DSI node, not the board. Signed-off-by: Stephan Gerhold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-09-15arm64: dts: qcom: msm8916: Move more supplies to msm8916-pm8916.dtsiStephan Gerhold4-38/+24
So far we had some supplies defined for all boards in msm8916.dtsi, while others were duplicated into every board-specific device tree. Now that we have msm8916-pm8916.dtsi as a common include for all standard MSM8916 devices using PM8916, move the remaining common supplies to msm8916-pm8916.dtsi to reduce duplication a bit. Signed-off-by: Stephan Gerhold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-09-15arm64: dts: qcom: msm8916: Move PM8916-specific parts to msm8916-pm8916.dtsiStephan Gerhold6-48/+59
Device trees for newer SoCs avoid defining the regulator nodes directly in the SoC device tree (here: msm8916.dtsi). The reason for this is that theoretically it is possible to combine the SoC with a different PMIC, or to use all the regulators in a board-specific way. Therefore let's remove those from the SoC include (msm8916.dtsi). In practice, pretty much all MSM8916 boards were combined with PM8916, and use the regulators in similar ways. After looking at many different MSM8916 boards (mostly smartphones and tablets), I haven't seen a single device that isn't using the same regulators for components integrated into the SoC. If all boards end up defining all regulators and supplies in the same way then it is useful to have an include for that, so we can avoid duplicating it everywhere. If there is really a super special board that does it differently it could just override some properties or avoid using the include altogether. This patch moves the regulator and common supply definitions to a new include called "msm8916-pm8916.dtsi". This is also going to be useful when introducing CPR (Core Power Reduction) later because we can configure the CPU regulator (pm8916_spmi_s2) for all devices in this common include. Signed-off-by: Stephan Gerhold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-09-15arm64: dts: qcom: pm8916: Add resin nodeStephan Gerhold4-40/+23
Right now we define the entire pm8916 resin node separately in the board-specific device tree part, including the interrupt that belongs to PM8916. As a feature of the PMIC it should be declared in pm8916.dtsi, disabled by default. Like all other optional components it can then by enabled and configured in the board-specific device tree part. Signed-off-by: Stephan Gerhold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-09-15arm64: dts: qcom: msm8916: Use labels in board device treesStephan Gerhold4-546/+514
Device trees for newer SoCs avoid replicating the entire device hierarchy in the board-specific device tree part. Instead, they set additional properties only by referencing labels, sorted alphabetically. Now that we have labels for all relevant nodes, convert the MSM8916 board device trees to use the same style and remove the "soc" node entirely. Note: There is a large block of coresight nodes in apq8016-sbc.dtsi, which are enabled by setting status = "okay". I kept them grouped together (not alphabetically sorted with everything else), since that would be just unnecessarily verbose and hard to see. This commit only moves all existing properties to nodes that reference the respective label. The resulting binary DTBs are exactly the same. Signed-off-by: Stephan Gerhold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2020-09-15arm64: dts: qcom: msm8916: Add more labelsStephan Gerhold1-20/+20
Add a few more labels to device nodes declared in msm8916.dtsi so that we can set all needed properties using labels in the board-specific device tree part. Also rename the "otg" label to "usb" to allow grouping it with the USB PHY (usb_hs_phy) node when ordering referenced labels alphabetically. Signed-off-by: Stephan Gerhold <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
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