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2020-09-23ARM: dts: stm32: lxa-mc1: Fix kernel warning about PHY delaysHolger Assmann1-2/+0
The KSZ9031 PHY skew timings for rxc/txc, originally set to achieve the desired phase shift between clock- and data-signal, now trigger a kernel warning when used in rgmii-id mode: *-skew-ps values should be used only with phy-mode = "rgmii" This is because commit bcf3440c6dd7 ("net: phy: micrel: add phy-mode support for the KSZ9031 PHY") now configures own timings when phy-mode = "rgmii-id". Device trees wanting to set their own delays should use phy-mode "rgmii" instead as the warning prescribes. The "standard" timings now used with "rgmii-id" work fine on this board, so drop the explicit timings in the device tree and thereby silence the warning. Fixes: 666b5ca85cd3 ("ARM: dts: stm32: add STM32MP1-based Linux Automation MC-1 board") Signed-off-by: Holger Assmann <[email protected]> Acked-by: Ahmad Fatoum <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2020-09-23ARM: dts: stm32: Add USB OTG support to DH PDK2Marek Vasut1-2/+5
The DH PDK2 board is capable of USB OTG on the X14 USB Mini-AB connector, fill in the missing bits to make USB OTG possible instead of peripheral. Signed-off-by: Marek Vasut <[email protected]> Cc: Alexandre Torgue <[email protected]> Cc: Maxime Coquelin <[email protected]> Cc: Patrice Chotard <[email protected]> Cc: Patrick Delaunay <[email protected]> Cc: [email protected] To: [email protected] Signed-off-by: Alexandre Torgue <[email protected]>
2020-09-23ARM: dts: stm32: Fix sdmmc2 pins on AV96Marek Vasut1-3/+3
The AV96 uses sdmmc2_d47_pins_c and sdmmc2_d47_sleep_pins_c, which differ from sdmmc2_d47_pins_b and sdmmc2_d47_sleep_pins_b in one pin, SDMMC2_D5, which is PA15 in the former and PA9 in the later. The PA15 is correct on AV96, so fix this. This error is likely a result of rebasing across the stm32mp1 DT pinctrl rework. Fixes: 611325f68102 ("ARM: dts: stm32: Add eMMC attached to SDMMC2 on AV96") Signed-off-by: Marek Vasut <[email protected]> Cc: Alexandre Torgue <[email protected]> Cc: Maxime Coquelin <[email protected]> Cc: Patrice Chotard <[email protected]> Cc: Patrick Delaunay <[email protected]> Cc: [email protected] To: [email protected] Signed-off-by: Alexandre Torgue <[email protected]>
2020-09-23ARM: dts: stm32: Add DHSOM based DRC02 boardMarek Vasut4-2/+195
Add DT for DH DRC02 unit, which is a universal controller device. The system has two ethernet ports, two CANs, RS485 and RS232, USB, capacitive buttons and an OLED display. Signed-off-by: Marek Vasut <[email protected]> Cc: Alexandre Torgue <[email protected]> Cc: Maxime Coquelin <[email protected]> Cc: Patrice Chotard <[email protected]> Cc: Patrick Delaunay <[email protected]> Cc: [email protected] To: [email protected] Signed-off-by: Alexandre Torgue <[email protected]>
2020-09-23ARM: dts: stm32: Move ethernet PHY into DH SoM DTMarek Vasut2-33/+36
The PHY and the VIO regulator is populated on the SoM, move it into the SoM DT. Signed-off-by: Marek Vasut <[email protected]> Cc: Alexandre Torgue <[email protected]> Cc: Maxime Coquelin <[email protected]> Cc: Patrice Chotard <[email protected]> Cc: Patrick Delaunay <[email protected]> Cc: [email protected] To: [email protected] Signed-off-by: Alexandre Torgue <[email protected]>
2020-09-23arm64: dts: ti: Add support for J7200 Common Processor BoardLokesh Vutla3-0/+96
Add support for J7200 Common Processor Board. The EVM architecture is very similar to J721E as follows: +------------------------------------------------------+ | +-------------------------------------------+ | | | | | | | Add-on Card 1 Options | | | | | | | +-------------------------------------------+ | | | | | | +-------------------+ | | | | | | | SOM | | | +--------------+ | | | | | | | | | | | Add-on | +-------------------+ | | | Card 2 | | Power Supply | | Options | | | | | | | | | +--------------+ | <--- +------------------------------------------------------+ Common Processor Board Common Processor board is the baseboard that has most of the actual connectors, power supply etc. A SOM (System on Module) is plugged on to the common processor board and this contains the SoC, PMIC, DDR and basic high speed components necessary for functionality. Note: * The minimum configuration required to boot up the board is System On Module(SOM) + Common Processor Board. * Since there is just a single SOM and Common Processor Board, we are maintaining common processor board as the base dts and SOM as the dtsi that we include. In the future as more SOM's appear, we should move common processor board as a dtsi and include configurations as dts. * All daughter cards beyond the basic boards shall be maintained as overlays. Signed-off-by: Lokesh Vutla <[email protected]> Signed-off-by: Peter Ujfalusi <[email protected]> Signed-off-by: Nishanth Menon <[email protected]> Reviewed-by: Grygorii Strashko <[email protected]> Reviewed-by: Suman Anna <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-23arm64: dts: ti: Add support for J7200 SoCLokesh Vutla3-0/+503
The J7200 SoC is a part of the K3 Multicore SoC architecture platform. It is targeted for automotive gateway, vehicle compute systems, Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications. The SoC aims to meet the complex processing needs of modern embedded products. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, two clusters of lockstep capable dual Cortex-R5F MCUs and a Centralized Device Management and Security Controller (DMSC). * Configurable L3 Cache and IO-coherent architecture with high data throughput capable distributed DMA architecture under NAVSS. * Integrated Ethernet switch supporting up to a total of 4 external ports in addition to legacy Ethernet switch of up to 2 ports. * Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems, 20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C and I2C, eCAP/eQEP, eHRPWM among other peripherals. * One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL management. See J7200 Technical Reference Manual (SPRUIU1, June 2020) for further details: https://www.ti.com/lit/pdf/spruiu1 Signed-off-by: Lokesh Vutla <[email protected]> Signed-off-by: Nishanth Menon <[email protected]> Reviewed-by: Grygorii Strashko <[email protected]> Reviewed-by: Suman Anna <[email protected]> Reviewed-by: Vignesh Raghavendra <[email protected]> Reviewed-by: Kishon Vijay Abraham I <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-23dt-bindings: arm: ti: Add bindings for J7200 SoCLokesh Vutla1-0/+4
The J7200 SoC is a part of the K3 Multicore SoC architecture platform. It is targeted for automotive gateway, vehicle compute systems, Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications. The SoC aims to meet the complex processing needs of modern embedded products. Some highlights of this SoC are: * Dual Cortex-A72s in a single cluster, two clusters of lockstep capable dual Cortex-R5F MCUs and a Centralized Device Management and Security Controller (DMSC). * Configurable L3 Cache and IO-coherent architecture with high data throughput capable distributed DMA architecture under NAVSS. * Integrated Ethernet switch supporting up to a total of 4 external ports in addition to legacy Ethernet switch of up to 2 ports. * Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems, 20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C and I2C, eCAP/eQEP, eHRPWM among other peripherals. * One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL management. See J7200 Technical Reference Manual (SPRUIU1, June 2020) for further details: https://www.ti.com/lit/pdf/spruiu1 Signed-off-by: Lokesh Vutla <[email protected]> Signed-off-by: Nishanth Menon <[email protected]> Reviewed-by: Grygorii Strashko <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Suman Anna <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-23dt-bindings: arm: ti: Convert K3 board/soc bindings to DT schemaLokesh Vutla3-27/+32
Convert TI K3 Board/SoC bindings to DT schema format. Signed-off-by: Lokesh Vutla <[email protected]> Signed-off-by: Nishanth Menon <[email protected]> Reviewed-by: Grygorii Strashko <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Suman Anna <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-23arm64: dts: ti: Makefile: Use ARCH_K3 for building dtbsLokesh Vutla1-3/+3
To allow lesser dependency and better maintainability use CONFIG_ARCH_K3 for building dtbs for all K3 based devices. This is as per the discussion in [0]. [0] https://lore.kernel.org/linux-arm-kernel/20200908112534.t5bgrjf7y3a6l2ss@akan/ Signed-off-by: Lokesh Vutla <[email protected]> Signed-off-by: Nishanth Menon <[email protected]> Reviewed-by: Suman Anna <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-23arm64: dts: rockchip: add ir-receiver node to rk3399-khadas-edgeArtem Lapkin1-0/+14
add missed ir-receiver and ir_rx pinctl nodes to rk3399-khadas-edge Khadas Edge board uses gpio-ir-receiver on RK_PB6 gpio Signed-off-by: Artem Lapkin <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2020-09-23arm64: dts: rockchip: add spiflash node to rk3399-khadas-edgeArtem Lapkin1-0/+10
The Khadas Edge Boards uses winbond - w25q128 spi flash with 104Mhz Signed-off-by: Artem Lapkin <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2020-09-22arm64: dts: rockchip: Add support for FriendlyARM NanoPi R2SDavid Bauer2-0/+369
This adds support for the NanoPi R2S from FriendlyARM. Rockchip RK3328 SoC 1GB DDR4 RAM Gigabit Ethernet (WAN) Gigabit Ethernet (USB3) (LAN) USB 2.0 Host Port MicroSD slot Reset button WAN - LAN - SYS LED Signed-off-by: David Bauer <[email protected]> Link: https://lore.kernel.org/r/[email protected] [adapted from sdmmc0m1_gpio to renamed sdmmc0m1_pin] Reported-by: kernel test robot <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]>
2020-09-22dt-bindings: Add doc for FriendlyARM NanoPi R2SDavid Bauer1-0/+5
Add devicetree binding documentation for the FriendlyARM NanoPi R2S. Signed-off-by: David Bauer <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2020-09-22arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instancesKishon Vijay Abraham I1-0/+80
J721E Common Processor Board has PCIe connectors for the 1st three PCIe instances. Configure the three PCIe instances in RC mode and disable the 4th PCIe instance. Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Nishanth Menon <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-22arm64: dts: ti: k3-j721e-main: Add PCIe device tree nodesKishon Vijay Abraham I2-2/+235
Add PCIe device tree nodes (both RC and EP) for the four PCIe instances here. Also add the missing translations required in the "ranges" DT property of cbass_main to access all the four PCIe instances. Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Nishanth Menon <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-09-22arm64: dts: imx8mq-librem5: correct GPIO hog propertyKrzysztof Kozlowski1-1/+1
Correct the name of property for GPIO specifier in GPIO hog. Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-22arm64: dts: imx8mm-var-som-symphony: Drop wake-up source from RTCKrzysztof Kozlowski1-1/+0
The RTC on Symphony board does not have its interrupt pin connected to the SoC, therefore it is not capable of waking up. Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-22arm64: dts: imx8mq: correct interrupt flagsKrzysztof Kozlowski4-5/+9
GPIO_ACTIVE_x flags are not correct in the context of interrupt flags. These are simple defines so they could be used in DTS but they will not have the same meaning: 1. GPIO_ACTIVE_HIGH = 0 = IRQ_TYPE_NONE 2. GPIO_ACTIVE_LOW = 1 = IRQ_TYPE_EDGE_RISING Correct the interrupt flags, assuming the author of the code wanted same logical behavior behind the name "ACTIVE_xxx", this is: ACTIVE_LOW => IRQ_TYPE_LEVEL_LOW Signed-off-by: Krzysztof Kozlowski <[email protected]> Acked-By: Tim Harvey <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-22arm64: dts: imx8mn: correct interrupt flagsKrzysztof Kozlowski3-3/+4
GPIO_ACTIVE_x flags are not correct in the context of interrupt flags. These are simple defines so they could be used in DTS but they will not have the same meaning: 1. GPIO_ACTIVE_HIGH = 0 = IRQ_TYPE_NONE 2. GPIO_ACTIVE_LOW = 1 = IRQ_TYPE_EDGE_RISING Correct the interrupt flags, assuming the author of the code wanted same logical behavior behind the name "ACTIVE_xxx", this is: ACTIVE_LOW => IRQ_TYPE_LEVEL_LOW For level low interrupts, enable also internal pull up. It is required at least on imx8mm-evk, according to schematics. Signed-off-by: Krzysztof Kozlowski <[email protected]> Acked-By: Tim Harvey <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-22arm64: dts: imx8mm: correct interrupt flagsKrzysztof Kozlowski4-6/+10
GPIO_ACTIVE_x flags are not correct in the context of interrupt flags. These are simple defines so they could be used in DTS but they will not have the same meaning: 1. GPIO_ACTIVE_HIGH = 0 = IRQ_TYPE_NONE 2. GPIO_ACTIVE_LOW = 1 = IRQ_TYPE_EDGE_RISING Correct the interrupt flags, assuming the author of the code wanted same logical behavior behind the name "ACTIVE_xxx", this is: ACTIVE_LOW => IRQ_TYPE_LEVEL_LOW ACTIVE_HIGH => IRQ_TYPE_LEVEL_HIGH In case of level low interrupts, enable also internal pull up. It is required at least on imx8mm-evk, according to schematics. The schematics for Variscite imx8mm-var-som are not available and I was unable to get proper configuration from Variscite. Signed-off-by: Krzysztof Kozlowski <[email protected]> Acked-By: Tim Harvey <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-22arm64: dts: imx8mm-var-som-symphony: fix ptn5150 interruptsKrzysztof Kozlowski1-1/+2
Conversion of int-gpios into interrupts property requires also interrupt-parent and uses different flags. Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-22arm64: dts: layerscape: correct watchdog clocks for LS1088AZhao Qiang1-8/+8
On LS1088A, watchdog clk are divided by 16, correct it in dts. Signed-off-by: Zhao Qiang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-22arm64: dts: freescale: sl28: enable fan supportMichael Walle1-0/+9
Add a pwm-fan mapped to the PWM channel 0 which is connected to the fan connector of the carrier. Signed-off-by: Michael Walle <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-22arm64: dts: freescale: sl28: enable LED supportMichael Walle1-0/+18
Now that we have support for GPIO lines of the SMARC connector, enable LED support on the KBox A-230-LS. There are two LEDs without fixed functions, one is yellow and one is green. Unfortunately, it is just one multi-color LED, thus while it is possible to enable both at the same time it is hard to tell the difference between "yellow only" and "yellow and green". Signed-off-by: Michael Walle <[email protected]> Acked-by: Pavel Machek <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-22arm64: dts: freescale: sl28: map GPIOs to input eventsMichael Walle1-0/+32
Now that we have support for GPIO lines of the SMARC connector, map the sleep, power and lid switch signals to the corresponding keys using the gpio-keys and gpio-keys-polled drivers. The power and sleep signals have dedicated interrupts, thus we use these ones. The lid switch is just mapped to a GPIO input and needs polling. Signed-off-by: Michael Walle <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-22arm64: dts: freescale: sl28: enable sl28cpldMichael Walle1-0/+102
Add the board management controller node. Signed-off-by: Michael Walle <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-22arm64: dts: imx8mq-evk: Add MIPI DSI supportFabio Estevam1-0/+44
imx8mq-evk has a MIPI DSI port that can be used to connect a Raydium RM67191 panel. Add support for it. Signed-off-by: Fabio Estevam <[email protected]> Acked-by: Guido Günther <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-22arm64: dts: layerscape: Add label to pcie nodesWasim Khan7-29/+30
Add label to pcie nodes so that they are easy to refer. Signed-off-by: Wasim Khan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-22arm64: dts: imx8mn-var-som-symphony: Add Variscite Symphony board with ↵Krzysztof Kozlowski2-0/+241
VAR-SOM-MX8MN Add a basic DTS for Variscite Symphony evaluation kit with VAR-SOM-MX8MN (i.MX 8M Nano) System on Module. This brings up the board with basic functionalities although still few issues remain (e.g. I2C3 and USB OTG port, although it might not be the problem of DTS). Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-22arm64: dts: imx8mn-var-som: Add Variscite VAR-SOM-MX8MN System on ModuleKrzysztof Kozlowski1-0/+551
Add DTSI of Variscite VAR-SOM-MX8MN (Nano) System on Module in a basic version, delivered with Variscite Symphony Evaluation kit. This version comes with: - 1 GB of RAM, - 16 GB eMMC, - Gigabit Ethernet PHY, - 802.11 ac/a/b/g/n WiFi with 4.2 Bluetooth, - CAN bus, - Audio codec (not yet configured in DTSI). Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-22dt-bindings: arm: fsl: Add binding for Variscite Symphony board with ↵Krzysztof Kozlowski1-0/+6
VAR-SOM-MX8MN Add a binding for the Variscite Symphony evaluation kit board with VAR-SOM-MX8MN System on Module. Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-22dt-bindings: arm: actions: Document RoseapplePiCristian Ciocaltea1-0/+1
Define compatible strings for RoseapplePi, a SBC manufactured in Taiwan, based on Actions Semi S500 reference design. Signed-off-by: Cristian Ciocaltea <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Manivannan Sadhasivam <[email protected]>
2020-09-22dt-bindings: Add vendor prefix for RoseapplePi.orgCristian Ciocaltea1-0/+2
Add devicetree vendor prefix for RoseapplePi.org Foundation. Website: http://roseapplepi.org/ Signed-off-by: Cristian Ciocaltea <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Manivannan Sadhasivam <[email protected]>
2020-09-22dt-bindings: arm: actions: Document Caninos Loucos LabradorMatheus Castello1-0/+10
Update the documentation to add the Caninos Loucos Labrador. Labrador project consists of the computer on module Core v2 based on the Actions Semi S500, computer on module Core v3 based on the Actions Semi S700 and the Labrador base boards. Signed-off-by: Matheus Castello <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Manivannan Sadhasivam <[email protected]>
2020-09-22dt-bindings: Add vendor prefix for Caninos LoucosMatheus Castello1-0/+2
The Caninos Loucos Program develops Single Board Computers with an open structure. The Program wants to form a community of developers to use IoT technologies and disseminate the learning of embedded systems in Brazil. It is an initiative of the Technological Integrated Systems Laboratory (LSI-TEC) with the support of Polytechnic School of the University of São Paulo (Poli-USP) and Jon "Maddog" Hall. Signed-off-by: Matheus Castello <[email protected]> Acked-by: Rob Herring <[email protected]> Reviewed-by: Andreas Färber <[email protected]> Signed-off-by: Manivannan Sadhasivam <[email protected]>
2020-09-22ARM: dts: owl-s500: Add RoseapplePiCristian Ciocaltea2-0/+48
Add a Device Tree for the RoseapplePi SBC. Signed-off-by: Cristian Ciocaltea <[email protected]> Reviewed-by: Peter Korsgaard <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Manivannan Sadhasivam <[email protected]>
2020-09-22ARM: dts: owl-s500: Fix incorrect PPI interrupt specifiersCristian Ciocaltea1-3/+3
The PPI interrupts for cortex-a9 were incorrectly specified, fix them. Fixes: fdfe7f4f9d85 ("ARM: dts: Add Actions Semi S500 and LeMaker Guitar") Signed-off-by: Cristian Ciocaltea <[email protected]> Reviewed-by: Peter Korsgaard <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Manivannan Sadhasivam <[email protected]>
2020-09-22ARM: dts: Add Caninos Loucos Labrador v2Matheus Castello3-0/+58
Add Device Trees for Caninos Loucos Labrador CoM Core v2 and base board M v1. Based on the work of Andreas Färber on Lemaker Guitar device tree. Signed-off-by: Matheus Castello <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Andreas Färber <[email protected]> Signed-off-by: Manivannan Sadhasivam <[email protected]>
2020-09-22arm64: dts: actions: Add DMA Controller for S700Amit Singh Tomar1-0/+15
This commit adds DMA controller present on Actions S700, it differs from S900 in terms of number of dma channels and requests. Reviewed-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Amit Singh Tomar <[email protected]> Signed-off-by: Manivannan Sadhasivam <[email protected]>
2020-09-22arm64: dts: actions: limit address range for pinctrl nodeAmit Singh Tomar1-1/+1
After commit 7cdf8446ed1d ("arm64: dts: actions: Add pinctrl node for Actions Semi S700") following error has been observed while booting Linux on Cubieboard7-lite(based on S700 SoC). [ 0.257415] pinctrl-s700 e01b0000.pinctrl: can't request region for resource [mem 0xe01b0000-0xe01b0fff] [ 0.266902] pinctrl-s700: probe of e01b0000.pinctrl failed with error -16 This is due to the fact that memory range for "sps" power domain controller clashes with pinctrl. One way to fix it, is to limit pinctrl address range which is safe to do as current pinctrl driver uses address range only up to 0x100. This commit limits the pinctrl address range to 0x100 so that it doesn't conflict with sps range. Fixes: 7cdf8446ed1d ("arm64: dts: actions: Add pinctrl node for Actions Semi S700") Reviewed-by: Manivannan Sadhasivam <[email protected]> Suggested-by: Andre Przywara <[email protected]> Signed-off-by: Amit Singh Tomar <[email protected]> Signed-off-by: Manivannan Sadhasivam <[email protected]>
2020-09-22ARM: dts: imx6qdl-gw5xxx: correct interrupt flagsKrzysztof Kozlowski14-14/+28
GPIO_ACTIVE_x flags are not correct in the context of interrupt flags. These are simple defines so they could be used in DTS but they will not have the same meaning: 1. GPIO_ACTIVE_HIGH = 0 = IRQ_TYPE_NONE 2. GPIO_ACTIVE_LOW = 1 = IRQ_TYPE_EDGE_RISING Correct the interrupt flags, assuming the author of the code wanted same logical behavior behind the name "ACTIVE_xxx", this is: ACTIVE_LOW => IRQ_TYPE_LEVEL_LOW Signed-off-by: Krzysztof Kozlowski <[email protected]> Acked-By: Tim Harvey <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-22dt-bindings: arm: fsl: Add PHYTEC i.MX6 devicetree bindingsStefan Riedmueller1-0/+37
Add devicetree bindings for i.MX6 based phyCORE-i.MX6, phyBOARD-Mira and phyFLEX-i.MX6. Signed-off-by: Stefan Riedmueller <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-22dt-bindings: arm: fsl: Add PHYTEC i.MX6 UL/ULL devicetree bindingsStefan Riedmueller1-0/+18
Add devicetree bindings for i.MX6 UL/ULL based phyCORE-i.MX6 UL/ULL and phyBOARD-Segin. Signed-off-by: Stefan Riedmueller <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-22ARM: dts: imx6q-logicpd: Use GPIO chipselectFabio Estevam1-1/+2
Using the native SPI chipselect on i.MX6 is known to be problematic. Doing it on a imx6q-sabresd causes the SPI NOR probe to fail: [ 5.388704] spi-nor spi0.0: unrecognized JEDEC id bytes: 00 00 00 00 00 00 Use the GPIO chipselect to avoid such problem. Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-22ARM: dts: imx: Add an entry for imx6q-logicpd.dtbFabio Estevam1-0/+1
Add an entry for imx6q-logicpd.dtb so that it can be built by default. Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-22ARM: dts: imx6q-logicpd: Add a specific board compatible stringFabio Estevam1-1/+1
It is standard practice to have a specific board compatible string, so pass "logicpd,imx6q-logicpd". Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-22dt-bindings: arm: fsl: Add an entry for the i.MX6 LogicPD boardFabio Estevam1-0/+1
Add an entry for the i.MX6 LogicPD board. Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-22ARM: dts: imx6q: align GPIO hog names with dtschemaKrzysztof Kozlowski4-21/+21
dtschema for pca95xx expects GPIO hogs to end with 'hog' prefix. While touching the hogs, fix indentation (spaces -> tabs). Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-09-22arm64: dts: imx8mn-ddr4-evk: Remove unneeded PMIC pin configurationKrzysztof Kozlowski1-8/+0
The pin configuration for PMIC interrupt is already set by imx8mn-evk.dtsi with exactly the same values. Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
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