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2022-10-27drm/edid: add a quirk for two LG monitors to get them to work on 10bpcHamza Mahfooz2-0/+18
The LG 27GP950 and LG 27GN950 have visible display corruption when trying to use 10bpc modes. So, to fix this, cap their maximum DSC target bitrate to 15bpp. Suggested-by: Roman Li <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amdgpu: Add EEPROM I2C address support for ip discoveryCandice Li1-2/+18
1. Update EEPROM_I2C_MADDR_SMU_13_0_0 to EEPROM_I2C_MADDR_54H 2. Add EEPROM I2C address support for smu v13_0_0 and v13_0_10. Signed-off-by: Candice Li <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amdgpu: Update ras eeprom support for smu v13_0_0 and v13_0_10Candice Li1-0/+10
Enable RAS EEPROM support for smu v13_0_0 and v13_0_10. Signed-off-by: Candice Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amdgpu: Optimize TA load/unload/invoke debugfs interfacesCandice Li4-104/+168
1. Add a function pointer structure ta_funcs to psp context 2. Make the interfaces generic to all TAs 3. Leverage exisitng TA context and remove unused functions 4. Fix return code bugs v2: Add comments for ta funcs macros and correct typo Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Candice Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amdgpu: Optimize RAS TA initialization and TA unload funcsCandice Li1-2/+8
1. Save TA unload psp response status 2. Add RAS TA loading status check for initializaiton 3. Drop RAS context teardown to allow RAS TA to be reloaded Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Candice Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amdkfd: Fix NULL pointer dereference in svm_migrate_to_ram()Yang Li1-3/+1
./drivers/gpu/drm/amd/amdkfd/kfd_migrate.c:985:58-62: ERROR: p is NULL but dereferenced. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=2549 Reported-by: Abaci Robot <[email protected]> Signed-off-by: Yang Li <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amd/display: prevent memory leakgehao2-0/+5
In dce6(0,1,4)_create_resource_pool and dce80_create_resource_pool the allocated memory should be released if construct pool fails. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: gehao <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amd/display: move remaining FPU code to dml folderAo Zhong3-2/+14
pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0; pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0; these two operations in dcn32/dcn32_resource.c still need to use FPU, This will cause compilation to fail on ARM64 platforms because -mgeneral-regs-only is enabled by default to disable the hardware FPU. Therefore, imitate the dcn31_zero_pipe_dcc_fraction function in dml/dcn31/dcn31_fpu.c, declare the dcn32_zero_pipe_dcc_fraction function in dcn32_fpu.c, and move above two operations into this function. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Ao Zhong <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amd/display: move remaining FPU code to dml folderAo Zhong3-42/+40
In the process of enabling DCN support for arm64, I found that the dcn10_resource_construct_fp function in dcn10/dcn10_resource.c still needs to use FPU. This will cause compilation to fail on ARM64 platforms because -mgeneral-regs-only is enabled by default to disable the hardware FPU. So move dcn10_resource_construct_fp from dcn10 folder to dml/dcn10 folder to enable hardware FPU for that function. Reviewed-by: Rodrigo Siqueira <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Ao Zhong <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amdgpu: remove deprecated MES version varsGraham Sider3-10/+0
MES scheduler and kiq versions are stored in mes.sched_version and mes.kiq_version, respectively, which are read from a register after their queues are initialized. Remove mes.ucode_fw_version and mes.data_fw_version which tried to read this versioning info from the firmware headers (which don't contain this information). Signed-off-by: Graham Sider <[email protected]> Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amdgpu: correct MES debugfs versionsGraham Sider1-4/+6
Use mes.sched_version, mes.kiq_version for debugfs as mes.ucode_fw_version does not contain correct versioning information. Signed-off-by: Graham Sider <[email protected]> Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amdgpu: Move the mutex_lock to protect the return status of ↵Alan Liu3-4/+13
securedisplay command buffer [Why] Before we call psp_securedisplay_invoke(), we call psp_prep_securedisplay_cmd_buf() to prepare and initialize the command buffer. However, we didn't use the mutex_lock to protect the status of command buffer. So when multiple threads are using the command buffer, after thread A return from psp_securedisplay_invoke() and the command buffer status is set to SUCCESS, another thread B may call psp_prep_securedisplay_cmd_buf() and initialize the status to FAILURE again, and cause Thread A to get a failure return status. [How] Move the mutex_lock out of psp_securedisplay_invoke() to its caller to cover psp_prep_securedisplay_cmd_buf() and the code checking the return status of command buffer. Signed-off-by: Alan Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amdgpu: remove ras_error_status parameter for UMC poison handlerTao Zhou4-16/+8
Make the code simpler. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amdgpu: add RAS poison handling for MCATao Zhou1-11/+20
For MCA poison, if unmap queue fails, only gpu reset should be triggered without page retirement handling, MCA notifier will do it. v2: handle MCA poison consumption in umc_poison_handler directly. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amdgpu: use page retirement API in MCA notifierTao Zhou1-33/+3
Make the code more readable. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amdgpu: add RAS page retirement functions for MCATao Zhou2-0/+55
Define page retirement functions for MCA platform. v2: remove page retirement handling from MCA poison handler, let MCA notifier do page retirement. v3: remove specific poison handler for MCA to simplify code. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amdkfd: remove unused struct cdit_headerPaulo Miguel Almeida1-23/+1
struct cdit_header was never used across any of the amd drivers nor this is exposed to UAPI so it can be removed. This patch removes struct cdit_header and refactor code accordingly Signed-off-by: Paulo Miguel Almeida <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amdkfd: remove unused kfd_pm4_headers_diq header filePaulo Miguel Almeida1-291/+0
kfd_pm4_headers_diq.h header is a leftover from the old H/W debugger module support added on commit fbeb661bfa895dc ("drm/amdkfd: Add skeleton H/W debugger module support"). That implementation was removed after a while and the last file that included that header was removed on commit 5bdd3eb253544b1 ("drm/amdkfd: Remove unused old debugger implementation"). This patch removes the unused header file kfd_pm4_headers_diq.h Signed-off-by: Paulo Miguel Almeida <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amd/display: Filter Invalid 420 Modes for HDMI TMDSFangzhi Zuo1-0/+67
[Why] Invalidate unsupported 420 modes on HDMI TMDS. HDMI TMDS does not support ODM. Any modes that are horizontally wider than 4096, cannot be supported via TMDS. So they must be filtered out and should not pass validation. [How] Create fake plane for the new stream, and validate global state by going through dml validation routine. Tested-by: Mark Broadworth <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Fangzhi Zuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amd/display: Rework comments on dc fileRodrigo Siqueira2-123/+70
The file dc.c has multiple comments that do not follow the kernel-doc or are made in a distracting way. This commit alleviates part of this issue by reorganizing some comments inside the dc file. Signed-off-by: Rodrigo Siqueira <[email protected]> Reviewed-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amd/display: 3.2.209Aric Cyr1-1/+1
DC version 3.2.209 brings along the following: * Improve color manipulation * Add corrections to DML and some flag configuration * Updates for DCN32x * Expand kernel-doc Tested-by: Mark Broadworth <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amdgpu: set fb_modifiers_not_supported in vkmsYifan Zhang1-0/+2
This patch to fix the gdm3 start failure with virual display: /usr/libexec/gdm-x-session[1711]: (II) AMDGPU(0): Setting screen physical size to 270 x 203 /usr/libexec/gdm-x-session[1711]: (EE) AMDGPU(0): Failed to make import prime FD as pixmap: 22 /usr/libexec/gdm-x-session[1711]: (EE) AMDGPU(0): failed to set mode: Invalid argument /usr/libexec/gdm-x-session[1711]: (WW) AMDGPU(0): Failed to set mode on CRTC 0 /usr/libexec/gdm-x-session[1711]: (EE) AMDGPU(0): Failed to enable any CRTC gnome-shell[1840]: Running GNOME Shell (using mutter 42.2) as a X11 window and compositing manager /usr/libexec/gdm-x-session[1711]: (EE) AMDGPU(0): failed to set mode: Invalid argument vkms doesn't have modifiers support, set fb_modifiers_not_supported to bring the gdm back. Signed-off-by: Yifan Zhang <[email protected]> Acked-by: Guchun Chen <[email protected]> Reviewed-by: Tim Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amd/display: Add kernel doc for commit sequenceRodrigo Siqueira3-11/+79
Add basic kernel-doc that describes some of the struct and functions that are part of the DC commit sequence.. Tested-by: Mark Broadworth <[email protected]> Reviewed-by: Aurabindo Pillai <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amd/display: Add kernel doc to some of the dc fieldsRodrigo Siqueira3-11/+40
Add kernel-doc to some important elements from DC struct that might help to understand DC sequence. Tested-by: Mark Broadworth <[email protected]> Reviewed-by: Aurabindo Pillai <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amd/display: Add basic ODM descriptionRodrigo Siqueira3-0/+24
Add kernel-doc to some of the ODM-related functions. Tested-by: Mark Broadworth <[email protected]> Reviewed-by: Aurabindo Pillai <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amd/display: Add DEC/CRB basic docRodrigo Siqueira2-0/+19
Add a kernel-doc to the DE-Tile function hook. Tested-by: Mark Broadworth <[email protected]> Reviewed-by: Aurabindo Pillai <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amd/display: Expand kernel doc for DCRodrigo Siqueira7-3/+82
This commit adds extra documentation for elements related to FAMs. Tested-by: Mark Broadworth <[email protected]> Reviewed-by: Aurabindo Pillai <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amd/display: Wrong colorimetry workaroundMa Hanghong4-3/+17
[Why] For FreeSync HDR, native color space flag in AMD VSIF(BT.709) should be used when intepreting content and color space flag in VSC or AVI infoFrame should be ignored. However, it turned out some userspace application still use color flag in VSC or AVI infoFrame which is incorrect. [How] Transfer function is used when building the VSC and AVI infoFrame. Set colorimetry to BT.709 when all the following match: 1. Pixel format is YCbCr; 2. In FreeSync 2 HDR, color is COLOR_SPACE_2020_YCBCR; 3. Transfer function is TRANSFER_FUNC_GAMMA_22; Tested-by: Mark Broadworth <[email protected]> Reviewed-by: Krunoslav Kovac <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Ma Hanghong <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amd/display: skip commit minimal transition statezhikzhai1-0/+22
[WHY] Now dynamic ODM will now be disabled when MPO is required safe transitions to avoid underflow, but we are triggering the way of minimal transition too often. Commit state of dc with no check will do pipeline setup which may re-initialize the component with no need such as audio. [HOW] Just do the minimal transition when all of pipes are in use, otherwise return true to skip. Tested-by: Mark Broadworth <[email protected]> Reviewed-by: Dillon Varone <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: zhikzhai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amd/display: wait for vblank during pipe programmingHaiyi Zhou1-4/+2
[WHY] Skipping vblank during global sync update request can result in underflow on certain displays. [HOW] Roll back to the previous behavior where DC waits for vblank during pipe programming. Fixes: 5d3e14421410 ("drm/amd/display: do not wait for vblank during pipe programming") Tested-by: Mark Broadworth <[email protected]> Reviewed-by: Martin Leung <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Haiyi Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amd/display: Fix SDR visual confirmAric Cyr1-3/+10
Apply SDR visual confirm to RGB10 and FP16 formats as well when needed. Tested-by: Mark Broadworth <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amd/display: cursor update command incompleteMax Tseng1-0/+4
Missing send cursor_rect width & Height into DMUB. PSR-SU would use these information. But missing these assignment in last refactor commit Tested-by: Mark Broadworth <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Max Tseng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amd/display: Enable timing sync on DCN32Alvin Lee1-0/+1
Missed enabling timing sync on DCN32 because DCN32 has a different DML param. Tested-by: Mark Broadworth <[email protected]> Reviewed-by: Martin Leung <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amd/display: Fix HDCP 1.X 1A-04 failingBhawanpreet Lakha1-1/+1
[Why] On some linux based OS, the hotplug->HDCP start takes longer than 4seconds (by ~100ms) This is due to the HDCP delay (3 sec) so we only have 1 second to hotplug->stream enablement, which is not enough for certain OS configs. [How] Change the Delay to 0 seconds. From testing it seems like 0 Seconds can pass 1.x and 2.x compliances Tested-by: Mark Broadworth <[email protected]> Reviewed-by: Aurabindo Pillai <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amd/display: Remove optimization for VRR updatesAlvin Lee1-3/+0
Optimization caused unexpected regression, so remove for now. Tested-by: Mark Broadworth <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amd/display: Set memclk levels to be at least 1 for dcn32Dillon Varone1-0/+3
[Why] Cannot report 0 memclk levels even when SMU does not provide any. [How] When memclk levels reported by SMU is 0, set levels to 1. Tested-by: Mark Broadworth <[email protected]> Reviewed-by: Martin Leung <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amd/display: Update latencies on DCN321Dillon Varone1-5/+5
Update DF related latencies based on new measurements. Tested-by: Mark Broadworth <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amd/display: 3.2.208Aric Cyr1-1/+1
DC version 3.2.208 brings along the following: * Add more kernel doc * Enable secure display on DCN21 * Limit dcn32 to 1950Mhz display clock * PSR code refactor * Rework audio stream sequence * Generic bug fixes Tested-by: Mark Broadworth <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amd/display: Document part of the DMUB cmdAnthony Koo1-1/+12
Add a simple documentation in the dmub_cmd. Tested-by: Mark Broadworth <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Anthony Koo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amd/display: Limit dcn32 to 1950Mhz display clockJun Lei1-4/+4
[why] Hardware team recommends we limit dispclock to 1950Mhz for all DCN3.2.x [how] Limit to 1950 when initializing clocks. Tested-by: Mark Broadworth <[email protected]> Reviewed-by: Alvin Lee <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Jun Lei <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amd/display: Drop struct crc_region and reuse struct rectAlan Liu8-42/+46
[Why] reuse struct rect rather than adding a new struct. [How] - Userspace keeps inputting x_start, y_start, x_end, y_end - We translate data to x, y, width, height in code flow to store - translate back to x_start, y_start, x_end, y_end before programming HW Tested-by: Mark Broadworth <[email protected]> Reviewed-by: Wayne Lin <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alan Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amd/display: Implement secure display on DCN21Alan Liu11-189/+223
[Why] Porting secure display feature from DCN10 to DCN21. Support single display for now and will extend to multiple displays. [How] - use workqueue to offload works for dmub or dmcu firmware - after receiving ROI update from userspace, set skip_frame_cnt to 1 - refactor amdgpu_dm_crtc_handle_crc_window_irq() - disable PSR before activating secure_display on a crtc - check if secure_display is activated before enabling psr - only work for single display for now. Tested-by: Mark Broadworth <[email protected]> Reviewed-by: Wayne Lin <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alan Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amd/display: Ignore Cable ID FeatureFangzhi Zuo1-0/+3
Ignore cable ID for DP2 receivers that does not support the feature. Tested-by: Mark Broadworth <[email protected]> Reviewed-by: Roman Li <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Fangzhi Zuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/amd/display: Update DSC capabilitie for DCN314Leo Chen1-1/+1
dcn314 has 4 DSC - conflicted hardware document updated and confirmed. Tested-by: Mark Broadworth <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Leo Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-27drm/i915/sdvo: Extract intel_sdvo_has_audio()Ville Syrjälä1-9/+18
Pull the SDVO audio state computation into a helper. This is almost identical to intel_hdmi_has_audio(), except the sink capabilities are stored under intel_sdvo rather than intel_hdmi. Might be nice to get rid of this duplication eventually... Cc: Chaitanya Kumar Borah <[email protected]> Cc: Kai Vehmanen <[email protected]> Cc: Takashi Iwai <[email protected]> Reviewed-by: Jani Nikula <[email protected]> Reviewed-by: Kai Vehmanen <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-10-27drm/i915/audio: Do the vblank waitsVille Syrjälä1-13/+18
The spec tells us to do a bunch of vblank waits in the audio enable/disable sequences. Make it so. The FIXMEs are nonsense since we do the audio disable very early and enable very late, so vblank interrupts are in fact enabled when we do this. TODO not sure we actually want these since we don't even rely on the hw ELD buffer, and these might be there just to give the audio side a bit of time to respond to the unsol events. OTOH they might be really needed for some other reason. Cc: Chaitanya Kumar Borah <[email protected]> Cc: Kai Vehmanen <[email protected]> Cc: Takashi Iwai <[email protected]> Acked-by: Jani Nikula <[email protected]> Reviewed-by: Kai Vehmanen <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-10-27drm/i915/audio: Split "ELD valid" vs. audio PD on hsw+Ville Syrjälä1-5/+11
On the older platforms the audio presence detect bit is in the port register, so it gets written outside audio codec hooks and is this separate from the ELD valid toggling. Split the operations into two steps on hsw+ to be more consistent with both the other platforms and the spec. Also according to the spec we might need some vblank waits between the two which definitely needs them done separately. Cc: Chaitanya Kumar Borah <[email protected]> Cc: Kai Vehmanen <[email protected]> Cc: Takashi Iwai <[email protected]> Reviewed-by: Jani Nikula <[email protected]> Reviewed-by: Kai Vehmanen <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-10-27drm/i915/audio: Use intel_de_rmw() for most audio registersVille Syrjälä1-81/+57
The audio code does a lot of RMW accesses. Utilize intel_de_rmw() to make that a bit less tedious. There are still some hand rolled RMW left, but those have a lot of code in between the read and write to calculate the new value, so would need some refactoring first. v2: Add parens around the ?: to satisfy the robot Cc: Chaitanya Kumar Borah <[email protected]> Cc: Kai Vehmanen <[email protected]> Cc: Takashi Iwai <[email protected]> Reviewed-by: Jani Nikula <[email protected]> Reviewed-by: Kai Vehmanen <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-10-27drm/i915/audio: Use u32* for ELDVille Syrjälä1-12/+9
Make the eld pointer u32* so we don't have to do super ugly casting in the code itself. Cc: Chaitanya Kumar Borah <[email protected]> Cc: Kai Vehmanen <[email protected]> Cc: Takashi Iwai <[email protected]> Reviewed-by: Jani Nikula <[email protected]> Reviewed-by: Kai Vehmanen <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-10-27drm/i915/audio: Make sure we write the whole ELD bufferVille Syrjälä1-9/+25
Currently we only write as many dwords into the hardware ELD buffers as drm_eld_size() tells us. That could mean the remainder of the hardware buffer is left with whatever stale garbage it had before, which doesn't seem entirely great. Let's zero out the remainder of the buffer in case the provided ELD doesn't fill it fully. We can also sanity check out idea of the hardware ELD buffer's size by making sure the address wrapped back to zero once we wrote the entire buffer. Cc: Chaitanya Kumar Borah <[email protected]> Cc: Kai Vehmanen <[email protected]> Cc: Takashi Iwai <[email protected]> Reviewed-by: Jani Nikula <[email protected]> Reviewed-by: Kai Vehmanen <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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