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2010-09-21intel-gtt add a cleanup function for chipset specific stuffDaniel Vetter1-8/+31
The old code didn't clean up the i830 chipset flush page. And it looks nicer. Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21intel-gtt: store the dma mask size in intel_gtt_driverDaniel Vetter1-7/+11
Storing this explicitly makes for clearer code and hopefully less further confusion. Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21intel-gtt: clean up gtt size reportingDaniel Vetter3-4/+5
Consolidate everything in intel-gtt.c and also kill the export of intel_max_stolen. Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21agp: kill agp_(unmap|map)_memoryDaniel Vetter2-11/+0
DMA remapping was only used by the intel-gtt driver. With that code now folded into the driver, kill the agp generic support for it. Cc: Dave Airlie <[email protected]> Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21intel-gtt: consolidate fake_agp driver structsDaniel Vetter1-131/+39
They're now all the same. Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21intel-gtt: move chipset flush to the gtt driver structDaniel Vetter1-7/+21
This is the last differentiator between the different fake agp drivers. Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21intel-gtt: kill mask_memory functionsDaniel Vetter1-92/+13
That indirection mess can now go. Add a dummy i81x gtt_driver to avoid a NULL pointer check. Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21intel-gtt: generic (insert|remove)_entries for sandybridgeDaniel Vetter1-136/+8
Like before, but now with the added bonus of being able to kill quite a bit of no-longer userful code (the old dmar support stuff). Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21intel-gtt: generic (insert|remove)_entries for g33/i965Daniel Vetter1-12/+9
Like for the i915. Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21intel-gtt: generic (insert|remove)_entries for i915Daniel Vetter1-11/+49
Beef up the generic version to support dmar. Otherwise like for the i830. v2: Don't try to DMA remap on resume for already remapped pages. Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21intel-gtt: generic (insert|remove)_entries for i830Daniel Vetter1-25/+28
Well, not all too generic because it does not yet support dmar. Add a new function check_flags to ensure that non-gem code does not try to screw us over. v2: Beautify i830_check_flags with an idea from Chris Wilson. Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21agp: kill agp_(map|unmap)_pageDaniel Vetter2-23/+1
Only used to remap the scratch page. Now that intel-gtt does this itself, kill the support code. Cc: Dave Airlie <[email protected]> Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21intel-gtt: drop agp scratch page support stuffDaniel Vetter1-28/+0
intel-gtt.c now handles the scratch page itself, so drop all that was just there to support it. Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21intel-gtt: introduce pte write function for gen6Daniel Vetter1-22/+26
Like for i830. intel_i9xx_configure is now unused, so kill it. Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21intel-gtt: introduce pte write function for g33/i965/gm45Daniel Vetter1-2/+15
Like for the i830. Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21intel-gtt: introduce pte write function for i8xx/i915/i945Daniel Vetter1-9/+32
And put it to use in the gtt configuration code that writes the scratch page addr in all gtt ptes. This makes intel_i830_configure generic, hence rename it to intel_fake_agp_configure. Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21intel-gtt: initialize our own scratch pageDaniel Vetter1-17/+64
The intel gtt fake agp driver is the only agp driver to use dma address remapping. So it makes sense to fold this code back into the only user (and thus reduce the reliance on the agp code). This patch does the first step by initializing (and remapping) the scratch page in a new function intel_gtt_setup_scratch_page. Unfortunately intel_gtt_cleanup had to move to avoid a forward declaration. The new scratch page is not yet used, though. v2: Refactor out scratch page teardown. Suggested by Chris Wilson on irc. This makes it clear what's going on and results in a nice symmetry between setup and teardown. Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915: Track pinned objectsChris Wilson3-14/+26
Keep a list of pinned objects and display it via debugfs. Now all objects that exist in the GTT are always tracked on one of the active, flushing, inactive or pinned lists. Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915: Drain any pending flips on the fb prior to unpinningChris Wilson3-20/+26
If we have queued a page flip on the current fb and then request a mode change, wait until the page flip completes before performing the new request. Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915: Merge ring flushing and lazy requestsChris Wilson3-32/+24
Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915: Track gpu fence usageChris Wilson2-2/+10
Track if the gpu requires the fence for the execution of a batch buffer and so only wait upon the retirement of the object's last rendering seqno if the fence is in use by the GPU. Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915/ringbuffer: whitespace cleanupChris Wilson2-65/+68
Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915: drop alignment ringbuffer parameterDaniel Vetter2-5/+1
Always PAGE_SIZE and only complicates the code. Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915: don't explicitly initialize ringbuffer members to zeroDaniel Vetter1-33/+0
The compiler happily does that for us. Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915: use new macros to access the ring ctl registerDaniel Vetter2-17/+7
Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915: use new macros to access the ring head registerDaniel Vetter2-40/+13
Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915: use new macros to access the ring start registerDaniel Vetter2-8/+6
Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915: use new macros to access the ring tail registerDaniel Vetter2-50/+22
Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915: add relative ring register macrosDaniel Vetter3-0/+12
Documentation explicitly mentions that the ring registers are designed to have the same offsets relative to a base registers. Use this to fight the code beaurocratic in intel_ringbuffer.c. No code changes in this patch, just the new definitions. Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915: kill duplicated/unneeded register definesDaniel Vetter1-18/+0
This looks like a copy-paste remnant from the i810. All the regs that are actually used are already defined somewhere else in i915_reg.h! Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915: Use ring->flush() instead of MI_FLUSHChris Wilson3-17/+20
Use the ring abstraction to hide the details of having choose the appropriate flushing method. Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915/ringbuffer: Mark the initialisation structs as constant.Chris Wilson1-3/+3
Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915: add a new BSD ring buffer for SandybridgeXiang, Haihao4-8/+159
This ring buffer is used for video decoding/encoding on Sandybridge. Signed-off-by: Xiang, Haihao <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915/ringbuffer: Implement advance using set_tailChris Wilson2-17/+1
As noted by Zhenyu, we can now simply replace the existing advance hook by calling the new set_tail function pointer directly. Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915: add set_tail hook in struct intel_ring_bufferXiang, Haihao2-5/+19
This is prepared for video codec ring buffer on Sandybridge. It is needed to read/write more than one register to move the tail pointer of the video codec ring on Sandybridge. Signed-off-by: Xiang, Haihao <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915: do not export the instances of struct intel_ring_bufferXiang, Haihao3-16/+31
Introduce intel_init_render_ring_buffer(), intel_init_bsd_ring_buffer for ring initialization. Signed-off-by: Xiang, Haihao <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915: fix HAS_BSD with a device info flagXiang, Haihao2-1/+6
Signed-off-by: Xiang, Haihao <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915: Clean up bo lists on all hung gpusChris Wilson3-19/+16
Previously we only tidied up the active bo lists for chipsets were we would attempt to reset the GPU. However, this action is necessary for the system to continue and reclaim the dead bo for all chipsets. Pointed out, in passing, by Owain Ainsworth. Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915: Clear GPU read domains on resetChris Wilson3-0/+19
Clear the GPU read domain for the inactive objects on a reset so that they are correctly invalidated on reuse. Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915: Clear flushing lists on GPU resetChris Wilson3-0/+23
Owain Ainsworth noticed that the reset code failed to clear the flushing list leaving the driver in an inconsistent state following a hung GPU. Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915: Only emit a flush request on the active ring.Chris Wilson4-22/+51
When flushing the GPU domains,we emit a flush on *both* rings, even though they share a unified cache. Only emit the flush on the currently active ring. Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915: Inline i915_gem_ring_retire_request()Chris Wilson1-53/+38
Change the semantics to retire any buffer older than the current seqno rather than repeatedly calling calling the function to retire the buffer at the head of the list matching the request seqno. Whilst this should have no semantic impact on the implementation, Daniel was wondering if there was a bug where we might miss a retirement and so end up with a continually growing active list. Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915/debug: Dump BSD ring buffers to debugfsChris Wilson1-6/+12
Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915: After a reset perform a forced modesetChris Wilson1-7/+10
On more recent chipsets, restoring the display is not as simple as writing a few registers, so force a full modeset of the current configuration in order to retrain the display link. Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915: Add support for GPU soft reset on Ironlake.Kenneth Graunke3-7/+27
Ironlake's graphics reset register has to be accessed via the MCHBAR, rather than via PCI config space, which requires some refactoring. Signed-off-by: Kenneth Graunke <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915: Rename graphics reset registers.Kenneth Graunke3-8/+10
The graphics domains are listed as GRDOM in the documentation, and the GDRST PCI config register (0xc0) is only valid on I965 and GM45. Newer chips (like Sandy Bridge) have a different GDRST. Signed-off-by: Kenneth Graunke <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915: Actually set the reset bit in i965_reset.Kenneth Graunke1-16/+15
Previously, it was only being set if passed GDRST_FULL - but the only caller passed GDRST_RENDER. So the hardware never actually reset. The comments also did not match the code. Instead, just set the reset bit regardless of what flags were passed. The GPU now resets correctly on my GM45. Signed-off-by: Kenneth Graunke <[email protected]> Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915: INTEL_INFO->gen supercedes i8xx, i9xx, i965gChris Wilson17-201/+197
Avoid confusion between i965g meaning broadwater and the gen4+ chipset families. Signed-off-by: Chris Wilson <[email protected]>
2010-09-21drm/i915: Cache LVDS EDIDChris Wilson1-11/+8
We assume that the panel is permenantly connected and that the EDID data is consistent from boot, so simply cache the whole EDID for the panel. Signed-off-by: Chris Wilson <[email protected]>
2010-09-21Merge branch 'drm-intel-fixes' into HEADChris Wilson614-3693/+6587
Conflicts: drivers/char/agp/intel-agp.c drivers/gpu/drm/i915/intel_crt.c
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