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2016-08-19amdgpu: move ttm stuff to amdgpu_ttm.hFlora Cui3-51/+80
Signed-off-by: Flora Cui <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-19drm/amd/powerplay: enable power containment features for tonga.Rex Zhu5-9/+548
v2: fix build error introduced when fix code style problems. Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-17drm/amd/amdgpu: Add more debugfs config dataTom St Denis1-1/+5
Adds family and external_rev_id to config data Signed-off-by: Tom St Denis <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-17drm/amdgpu: Hardcode virtual DCE vblank / scanout position return valuesEmily Deng1-12/+4
For virtual display feature, by hardcoding 0 for the vblank counter and -EINVAL for the scanout position return value, we signal to the core DRM code that there are no hardware counters we can use for these. Signed-off-by: Emily Deng <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-16drm/amd/amdgpu: Add more config data for debugfsTom St Denis1-1/+6
Adds rev_id as well as cg/pg flags to help debug runtime. Signed-off-by: Tom St Denis <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-16drm/amdgpu: fix coding style in amdgpu_object.cChristian König1-37/+49
Just a few 80 chars problems. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-16drm/amdgpu: add function pointer to the pte_update_paramsChristian König1-22/+54
Remember what function to call while planning the commands instead of figuring it our later on. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-16drm/amdgpu: stop splitting PTE commands into smaller onesChristian König5-149/+73
It doesn't make much sense to create bigger commands first which we then need to split into smaller one again. Just make sure the commands we create aren't to big in the first place. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-16drm/amdgpu: remove AMDGPU_VM_NO_FLUSH defineChristian König1-3/+0
Not used any more. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-16drm/amdgpu: cleanup the write_pte implementationsChristian König5-98/+54
We don't need the gart mapping handling here any more. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-16drm/amdgpu: remove pages_addr handling from the VM codeChristian König1-9/+1
Not needed any more. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-16drm/amdgpu: write PTEs directly into the IB.Christian König1-5/+21
Write the PTEs at the end of the IB instead of directly into the SDMA commands. This can save quite some CPU cycles building the entries. This doesn't change the DW estimation because PTEs where embedded into the IB before as well. It just moves them to the end of the IB. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-16drm/amdgpu: add shadow flag V2Chunming Zhou1-0/+8
Indicate if need to sync between bo and shadow, where sync to where. V2: Rename to backup_shadow Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-16drm/amdgpu: allocate shadow for pd/pt bo V2Chunming Zhou1-3/+11
The pd/pt shadow bo will be used to backup page table, when gpu reset happens, we can restore the page table by them. V2: Free shadow bo. Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-16drm/amdgpu: validate shadow as well when validating boChunming Zhou1-30/+46
Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-16drm/amdgpu: add shadow bo support V2Chunming Zhou3-3/+48
shadow bo is the shadow of a bo, which is always in GTT, which can be used to backup the original bo. V2: reference shadow parent, shadow bo will be freed by who allocted him. Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-16drm/amd/amdgpu: UVD v6 register cleanupTom St Denis1-16/+11
Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-16drm/amd/amdgpu: VCE v2 register cleanupTom St Denis1-25/+14
Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-16drm/amd/amdgpu: add mutex in check_soft for VCE v3Tom St Denis1-0/+2
Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-16drm/amd/amdgpu: Cleanup register access in VCE v3Tom St Denis1-102/+43
Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-10Fixing copy-paste errors and removing unneeded newlinesAlexandre Demers1-5/+3
Reviewed-by: Christian König <[email protected]> Signed-off-by: Alexandre Demers <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-10drm: Add DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE/RELATIVE flags v2Michel Dänzer4-10/+86
These flags allow userspace to explicitly specify the target vertical blank period when a flip should take effect. v2: * Add new struct drm_mode_crtc_page_flip_target instead of modifying struct drm_mode_crtc_page_flip, to make sure all existing userspace code keeps compiling (Daniel Vetter) Acked-by: Christian König <[email protected]> Reviewed-by: Daniel Vetter <[email protected]> Signed-off-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-10drm/radeon: Set MASTER_UPDATE_MODE to 0 againMichel Dänzer3-8/+6
With the previous change, it's safe to let page flips take effect anytime during a vertical blank period. This can avoid delaying a flip by a frame in some cases where we get to radeon_flip_work_func -> adev->mode_info.funcs->page_flip during a vertical blank period. Acked-by: Christian König <[email protected]> Signed-off-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-10drm/radeon: Provide page_flip_target hookMichel Dänzer2-65/+25
Now we can program a flip during a vertical blank period, if it's the one targeted by the flip (or a later one). This allows simplifying radeon_flip_work_func considerably. Acked-by: Christian König <[email protected]> Signed-off-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-10drm/amdgpu: Set MASTER_UPDATE_MODE to 0 againMichel Dänzer3-8/+8
With the previous change, it's safe to let page flips take effect anytime during a vertical blank period. This can avoid delaying a flip by a frame in some cases where we get to amdgpu_flip_work_func -> adev->mode_info.funcs->page_flip during a vertical blank period. Acked-by: Christian König <[email protected]> Signed-off-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-10drm/amdgpu: Provide page_flip_target hookMichel Dänzer7-76/+39
Now we can program a flip during a vertical blank period, if it's the one targeted by the flip (or a later one). This allows simplifying amdgpu_flip_work_func considerably. agd: update dce_virtual.c as well. Acked-by: Christian König <[email protected]> Signed-off-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-10drm: Add page_flip_target CRTC hook v2Michel Dänzer2-4/+40
Mostly the same as the existing page_flip hook, but takes an additional parameter specifying the target vertical blank period when the flip should take effect. v2: * Add curly braces around else statement corresponding to an if block with curly braces (Alex Deucher) * Call drm_crtc_vblank_put in the error case (Daniel Vetter) * Clarify entry point documentation comment (Daniel Vetter) Acked-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Daniel Vetter <[email protected]> Signed-off-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-10gpu: drm: radeon: radeon_i2c: don't print error when adding adapter failsWolfram Sang1-6/+2
The core will do this for us now. Signed-off-by: Wolfram Sang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-10gpu: drm: amd: amdgpu: amdgpu_i2c: don't print error when adding adapter failsWolfram Sang1-3/+1
The core will do this for us now. Signed-off-by: Wolfram Sang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-10drm/amdgpu: use more than 64KB fragment size if possibleChristian König1-4/+8
We align to 64KB, but when userspace aligns even more we can easily use more. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-10drm/amdgpu: flip frag_ptes and update_ptsChristian König1-87/+79
We can add the fragment params before we split the update for the page tables. That should save a few CPU cycles for larger updates. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-10drm/amdgpu: add adev to the pte_update_paramsChristian König1-36/+29
No need to carry that forward as a separate parameter. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-10drm/amdgpu: rename amdgpu_vm_update_paramsChristian König1-47/+44
Well those are actually page table entry parameters. This also makes the variable names used a bit shorter. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-10drm/amdgpu: cleanup VM fragment definesChristian König2-5/+5
We can actually do way more than just the 64KB we currently used as default. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-10drm/amdgpu: remove unused VM definesChristian König1-2/+0
Not used for a long time. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-10drm/amd/amdgpu: Simplify bitfield operations in gfx v8Tom St Denis2-230/+48
This patch introduces a new macro WREG32_FIELD which is used to write to a register with a new value in a field. It's designed to replace the pattern: tmp = RREG32(mmFoo); tmp &= ~REG__FIELD_MASK; tmp |= new_value << REG__FIELD__SHIFT; WREG32(mmFoo, tmp) with: WREG32_FIELD(Foo, FIELD, new_value); Unlike WREG32_P() it understands offsets/masks and doesn't require the caller to shift the value (or mask properly). It's applied where suitable in the gfx_v8_0.c driver to start with. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-10drm/amd/amdgpu: Simplify various gfx v8 functionsTom St Denis1-41/+20
Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-10drm/amd/amdgpu: Correct whitespace in GFX v8Tom St Denis1-25/+16
Fix various whitespace issues in gfx v8 driver. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-10drm/amdgpu: Change the virtual_display type from int to char*.Emily Deng5-7/+35
For virtual display feature, as there may be multiple GPUs, for user could choose whiche GPU need to enable this feature, change the type of virtual_display from int to char*. The variable will be set like this virtual_display="xxxx:xx:xx.x;xxxx:xx:xx.x;". Signed-off-by: Emily Deng <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-08drm/amdgpu: add virtual dce support for icelandAlex Deucher1-2/+56
Signed-off-by: Alex Deucher <[email protected]>
2016-08-08drm/amdgpu/virtual_dce: add case for topaz for disable_dceAlex Deucher1-1/+4
This asic has no DCE block. Also clarify the error message for unmatched chips. Signed-off-by: Alex Deucher <[email protected]>
2016-08-08drm/amdgpu: move vsync_timer_enabled setup to dce virtual early_initAlex Deucher3-2/+1
Put it in one place. Signed-off-by: Alex Deucher <[email protected]>
2016-08-08drm/amdgpu: Set ip_blocks according variable amdgpu_virtual_display.Emily Deng3-50/+113
For virtual display feature, if user set the option "amdgpu.virtual_display=1" when load amdgpu.ko. Then need to set the ip_blocks with virtual display ip blocks. And when enable virtual display, the amdgpu_dal need to be set to zero. Signed-off-by: Emily Deng <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-08drm/amdgpu: Define one variable for virtual display.Emily Deng2-0/+5
For virtual display feature, define on variable in amdgpu.ko. When want to enable virtual display feature, need set the option "amdgpu.virtual_display=1". And then disable vga render and crtc if have DCE engine. Signed-off-by: Emily Deng <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-08drm/amdgpu: Define virtual display ip blocks.Emily Deng2-0/+623
For virtual display feature, define virtual display ip blocks, and set dce_virtual_ip_funcs to DCE block. Signed-off-by: Emily Deng <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-08drm/amdgpu: Add DRM_MODE_CONNECTOR_VIRTUAL connector in amdgpu_connector_add.Emily Deng1-0/+91
For virtual display feature, add one connector type in amdgpu_connector_add. Signed-off-by: Emily Deng <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-08drm/amdgpu: Call pageflip irq funtion when receiced vsync interrupt.Emily Deng1-3/+7
For virtual display feature, as there is no dce engine, so no pageflip irq generated. So directly call pageflip irq funtion when received vysn interrupt. Signed-off-by: Emily Deng <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-08drm/amdgpu: Use software timer to generate vsync interrupt.Emily Deng3-2/+37
For virtual display feature, use the software timer to simulate the vsync interrupt. Signed-off-by: Emily Deng <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-08drm/amdgpu: Disable VGA render and crtc when init GMC.Emily Deng7-11/+173
For virtual display feature, when the GPU has DCE engine, need to disable the VGA render and CRTC, or it will hang when initialize GMC. Signed-off-by: Emily Deng <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-08-08drm/amdgpu: To define whether the GPU has DCE engine.Emily Deng2-0/+29
For virtual display feature, when the GPU has DCE engine, need to disable the VGA render and CRTC, or it will hang when initialize GMC. So first detect whether the GPU has DCE engine. Signed-off-by: Emily Deng <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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