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There was an additional alias in the specifier it hogged line 27
instead of line 1.
Signed-off-by: Guido Günther <[email protected]>
Signed-off-by: Martin Kepplinger <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Add 2x2 SFP+ cage support for clearfog-itx boards.
Signed-off-by: Russell King <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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With the first redesign the debug UART had changed from
UART2 to UART1.
As the first hardware revision is considered as alpha and
will not be supported in future. The old setup will not
be preserved.
Signed-off-by: Teresa Remmet <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Reorder flexspi clock-names entry to make it compliant with bindings.
Signed-off-by: Kuldeep Singh <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Reorder flexspi clock-names entry to make it compliant with bindings.
Signed-off-by: Kuldeep Singh <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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In NXP LS1028A there is a MAC-to-MAC internal link between enetc_port2
and mscc_felix_port4. This link operates at 2.5Gbps and is described as
such for the mscc_felix_port4 node.
The reason for the discrepancy is a limitation in the PHY library
support for fixed-link nodes. Due to the fact that the PHY library
registers a software PHY which emulates the clause 22 register map, the
drivers/net/phy/fixed_phy.c driver only supports speeds up to 1Gbps.
The mscc_felix_port4 node is probed by DSA, which does not use the PHY
library directly, but phylink, and phylink has a different representation
for fixed-link nodes, one that does not have the limitation of not being
able to represent speeds > 1Gbps.
Since the enetc driver was converted to phylink too as of commit
71b77a7a27a3 ("enetc: Migrate to PHYLINK and PCS_LYNX"), the limitation
has been practically lifted there too, and we can describe the real link
speed in the device tree now.
Signed-off-by: Vladimir Oltean <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Add the description for ecspi2 support.
Signed-off-by: Adrien Grassein <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Reviewed-by: Marco Felsch <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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The i.MX8QuadMax is a Dual (2x) Cortex-A72 and Quad (4x) Cortex-A53
proccessor with powerful graphic and multimedia features.
This patch adds i.MX8QuadMax MEK board support.
Note that MX8QM needs a special workaround for TLB flush due to a SoC
errata, otherwise there may be random crash if enable both clusters of
A72 and A53. As the errata workaround is still not in mainline, so we
disable A72 cluster first for MX8QM MEK.
Cc: Rob Herring <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: [email protected]
Cc: Sascha Hauer <[email protected]>
Cc: Fabio Estevam <[email protected]>
Signed-off-by: Dong Aisheng <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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The i.MX8QuadMax is a Dual (2x) Cortex-A72 and Quad (4x) Cortex-A53
proccessor with powerful graphic and multimedia features. It uses
the same architecture as MX8QXP, so many SS can be reused.
This patch adds i.MX8QuadMax SoC dtsi file.
Cc: Rob Herring <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: [email protected]
Cc: Sascha Hauer <[email protected]>
Cc: Fabio Estevam <[email protected]>
Signed-off-by: Dong Aisheng <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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The DMA SS of MX8QM is mostly the same as the DMA part in MX8QXP ADMA SS
while it has one more instance for each of LPUART, ADC and LPI2C. And unlike
MX8QXP that flexcan clocks are shared between multiple CAN instances,
MX8QM has separate flexcan clock slice.
So we reuse the most part of common imx8-ss-dma.dtsi and add new things
based on it.
Cc: Rob Herring <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: [email protected]
Cc: Sascha Hauer <[email protected]>
Cc: Fabio Estevam <[email protected]>
Signed-off-by: Dong Aisheng <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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amda ss is consisted of dma and audio ss in qxp which are
also used in qm.
Let's split them into two ss for better code reuse.
Signed-off-by: Dong Aisheng <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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The CONN SS of MX8QM is mostly the same as MX8QXP except it has one more
USB HSIC module support. So we can fully reuse the exist CONN SS dtsi.
Add <soc>-ss-conn.dtsi with compatible string updated according to
imx8-ss-conn.dtsi.
Cc: Rob Herring <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: [email protected]
Cc: Sascha Hauer <[email protected]>
Cc: Fabio Estevam <[email protected]>
Signed-off-by: Dong Aisheng <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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The LSIO SS of MX8QM is exactly the same as MX8QXP. So we can fully
reuse the exist LSIO SS dtsi. Add <soc>-ss-lsio.dtsi with compatible
string updated according to imx8-ss-lsio.dtsi.
Cc: Rob Herring <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: [email protected]
Cc: Sascha Hauer <[email protected]>
Cc: Fabio Estevam <[email protected]>
Signed-off-by: Dong Aisheng <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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switch to new lpcg clock binding
Signed-off-by: Dong Aisheng <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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switch to two cell scu clock binding
Signed-off-by: Dong Aisheng <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Add adma lpcg clocks
Cc: Rob Herring <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: [email protected]
Cc: Sascha Hauer <[email protected]>
Cc: Fabio Estevam <[email protected]>
Signed-off-by: Dong Aisheng <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Add conn lpcg clocks
Cc: Rob Herring <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: [email protected]
Cc: Sascha Hauer <[email protected]>
Cc: Fabio Estevam <[email protected]>
Signed-off-by: Dong Aisheng <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Add lsio lpcg clocks
Cc: Rob Herring <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: [email protected]
Cc: Sascha Hauer <[email protected]>
Cc: Fabio Estevam <[email protected]>
Signed-off-by: Dong Aisheng <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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MX8 SoC is comprised of a few HW subsystems while some of them can be
reused in the different SoCs. So let's re-orginize them into subsystems
in device tree as well for the possible reuse of the common part.
Note, as there's still no devices of hsio subsys, so removed it
first instead of creating a subsys headfile with no devices.
They will be added back when new devices added.
Cc: Rob Herring <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: [email protected]
Cc: Sascha Hauer <[email protected]>
Cc: Fabio Estevam <[email protected]>
Signed-off-by: Dong Aisheng <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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SCU clock depends on SCU Power domain. Moving scu pd node before
scu clock can save a hundred of defer probes of all system devices
which depends on power domain and clocks.
Cc: Rob Herring <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: [email protected]
Cc: Sascha Hauer <[email protected]>
Cc: Fabio Estevam <[email protected]>
Signed-off-by: Dong Aisheng <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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According to binding doc, add the fallback compatible string for
scu pd.
Cc: Rob Herring <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: [email protected]
Cc: Sascha Hauer <[email protected]>
Cc: Fabio Estevam <[email protected]>
Signed-off-by: Dong Aisheng <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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There is wdog[2,3] in i.MX8MP, so add them.
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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The Kontron pitx-imx8m board is based on an i.MX8MQ soc.
Signed-off-by: Heiko Thiery <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Michael Walle <[email protected]>
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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The reMarkable2 (https://remarkable.com) is an e-ink tablet based on
the imx7d SoC.
This commit is based on the DTS provide by reMarkable but ported to the
latest kernel (instead of 4.14). I have removed references to
non-upstream devices and have changed the UART so that the console can
be accessed without having to open up the device via the OTG pogo pins.
Currently the kernel boots, but there is no support for the display.
WiFi is untested (no display or UART RX makes it hard to test), but
should work with the current upstream driver. As it's untested it's not
included in this commit.
Signed-off-by: Alistair Francis <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Signed-off-by: Alistair Francis <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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reMarkable AS produces eInk tablets
Signed-off-by: Alistair Francis <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Add node for Samsung S5K5BAF CMOS image sensor and enable the associated
MIPI CSI-2 receiver node.
Signed-off-by: Timon Baetz <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[krzk: put csis_1 node in alphabetical order]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Make it clear which UIB is used with each board in
comments and model text.
Signed-off-by: Linus Walleij <[email protected]>
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There is no point in sharing any definitions between
the R2 and R3 versions of the TVK1281618 UIB. The
proximity sensor collides with the touchscreen etc,
it is less confusing to get rid of the overarching
TVK1281618 UIB file and just use one for each.
Signed-off-by: Linus Walleij <[email protected]>
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The TC35893 is connected to different GPIOs in different
UIBs so just bite the bullet and push this info down
into respective UIB so we can avoid confusion when
reading the DTS files.
Signed-off-by: Linus Walleij <[email protected]>
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delay select values for MMCSD subsystems
The following speed modes are now supported in J7200 SoC,
- HS200 and HS400 modes at 1.8 V card voltage, in MMCSD0 subsystem [1].
- UHS-I speed modes in MMCSD1 subsystem [1].
Add support for UHS-I modes by adding voltage regulator device tree nodes
and corresponding pinmux details, to power cycle and voltage switch cards.
Set respective tags in sdhci0 and remove no-1-8-v tag from sdhci1
device tree nodes.
Also update the delay values for various speed modes supported, based on
the revised january 2021 J7200 datasheet[2].
[1] - section 12.3.6.1.1 MMCSD Features, in
https://www.ti.com/lit/ug/spruiu1a/spruiu1a.pdf,
(SPRUIU1A – JULY 2020 – REVISED JANUARY 2021)
[2] - https://www.ti.com/lit/ds/symlink/dra821u.pdf,
(SPRSP57B – APRIL 2020 – REVISED JANUARY 2021)
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
Reviewed-by: Kishon Vijay Abraham I <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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There are 6 gpio instances inside SoC with 2 groups as show below:
Group one: wkup_gpio0, wkup_gpio1
Group two: main_gpio0, main_gpio2, main_gpio4, main_gpio6
Only one instance from each group can be used at a time. So use main_gpio0
and wkup_gpio0 in current linux context and disable the rest of the nodes.
Signed-off-by: Faiz Abbas <[email protected]>
Signed-off-by: Sekhar Nori <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
Reviewed-by: Grygorii Strashko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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There are 4 instances of gpio modules in main domain:
gpio0, gpio2, gpio4 and gpio6
Groups are created to provide protection between different processor
virtual worlds. Each of these modules I/O pins are muxed within the
group. Exactly one module can be selected to control the corresponding
pin by selecting it in the pad mux configuration registers.
This group in main domain pins out 69 lines (5 banks). Add DT modes for
each module instance in the main domain.
Similar to the gpio groups in main domain, there is one gpio group in
wakeup domain with 2 module instances in it.
The gpio group pins out 72 pins (6 banks) of the first 85 gpio lines. Add
DT nodes for each module instance in the wakeup domain.
Signed-off-by: Faiz Abbas <[email protected]>
Signed-off-by: Sekhar Nori <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
Reviewed-by: Grygorii Strashko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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Acer A500 uses Atmel Maxtouch 1386 touchscreen controller. This controller
has WAKE line which could be connected to I2C clock lane, dedicated GPIO
or fixed to HIGH level. Controller wakes up from a deep sleep when WAKE
line is asserted low. Acer A500 has WAKE line connected to I2C clock and
Linux device driver doesn't work property without knowing what wakeup
method is used by h/w.
Add atmel,wakeup-method property to the touchscreen node.
Signed-off-by: Dmitry Osipenko <[email protected]>
[[email protected]: use literal to avoid dependency on header file]
Signed-off-by: Thierry Reding <[email protected]>
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The TVK1281618 R3 sensors are different from the R2 board,
some incorrectness is fixed and some new sensors added, we
also rename the nodes appropriately with accelerometer@
etc.
Signed-off-by: Linus Walleij <[email protected]>
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These sensors are particular to the TVK UIB R2 board and
will conflict with the R3 board, so push them down to
the actual UIB include DTSI.
Rename the nodes appropriately to accelerometer@ etc
in the process.
Signed-off-by: Linus Walleij <[email protected]>
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The Synaptics RMI4 touchscreen is a property of the
TVK1281618 R2 UIB, so move it into that file instead
of the main TVK1281618 main include so we can define
another touchscreen for the R3 UIB.
Signed-off-by: Linus Walleij <[email protected]>
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The touchscreen is mounted with flipped x/y on the R2
version of TVK1281618. Push this setting to that DTS file
only.
The function nodes were named wrong so the OF properties
didn not "take". Fix the node names from "rmi-fnn" to
"rmi4-nn" so this also work.
Signed-off-by: Linus Walleij <[email protected]>
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GPIO215 has a rail named WLAN_RST_N but it is actually connected
to the pin WLAN_REG_ON on the BCM4330 chip, so this should be
the WLAN regulator GPIO rather than GPIO222. The misunderstanding
comes from the erroneous naming of the rail on the schematic.
GPIO222 is indeed connected to the rail BT_VREG_EN and the pin
BT_REG_ON, and can be handled by the driver as usual.
This corrects misunderstandings and makes Janice's WLAN and BT
setup look like that of Golden and Skomer.
Add explicit BCM4330 compatible to the WLAN chip.
Cc: Stephan Gerhold <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
Reviewed-by: Stephan Gerhold <[email protected]>
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Provide access to NVRAM which contains device environment variables.
Signed-off-by: Rafał Miłecki <[email protected]>
Signed-off-by: Florian Fainelli <[email protected]>
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This fixes warnings/errors like:
arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dt.yaml: /: memory@0:reg:0: [0, 134217728, 2281701376, 402653184] is too long
From schema: /lib/python3.6/site-packages/dtschema/schemas/reg.yaml
Signed-off-by: Rafał Miłecki <[email protected]>
Signed-off-by: Florian Fainelli <[email protected]>
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Add the sub-mailbox nodes that are used to communicate between MPU and
various remote processors present in the AM64x SoCs for the AM642 EVM
and AM642 SK boards. These include the R5F remote processors in the two
dual-R5F clusters (MAIN_R5FSS0 & MAIN_R5FSS1) in the MAIN domain; and a
M4 processor in the MCU safety island.
These sub-mailbox nodes utilize the System Mailbox clusters 2, 4 and 6.
The remaining clusters 3, 5 and 7 are currently not used, and so are
disabled. Clusters 0 and 1 were never added to the dts file as they do
not support interrupts towards the A53 core.
The sub-mailbox nodes added match the hard-coded mailbox configuration
used within the TI RTOS IPC software packages. The R5F processor
sub-systems are assumed to be running in Split mode, so a sub-mailbox
node is used by each of the R5F cores. Only the sub-mailbox node for
the first R5F core in each cluster is used in case of a Single-CPU mode
for that R5F cluster.
NOTE:
The cluster nodes only have the Mailbox IP interrupt outputs that are
routed to the GIC_SPI. The sub-mailbox nodes' irq-id are indexing into
the listed interrupts, with the usr-id using the actual interrupt output
line number from the Mailbox IP.
Signed-off-by: Suman Anna <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
Reviewed-by: Gowtham Tammana <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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The AM64 MAIN domain contains a Mailbox IP instance with multiple
clusters, and is a variant of the IP on current AM65x and J721E
SoCs. The AM64x SoC has only 8 clusters with no interrupts routed
to the A53 core on the first 2 clusters. The interrupt outputs
from the IP do not go through any Interrupt Routers and are
hard-wired to each processor, with only couple of interrupts
from each cluster reaching the A53 core.
Add all the Mailbox clusters that generate interrupts towards the
A53 core as their own nodes under the cbass_main node instead of
creating an almost empty parent node for the Mailbox IP and the
clusters as its child nodes. All these nodes are enabled by default
in the base dtsi file, but any cluster that does not define any
child sub-mailbox nodes should be disabled in the corresponding
board dts files.
Signed-off-by: Suman Anna <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
Reviewed-by: Gowtham Tammana <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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The AM64x SoC contains a HwSpinlock IP instance that is a minor variant
of the IP on existing TI K3 SoCs such as AM65x, J721E or J7200 SoCs.
Add the DT node for this on AM64x SoCs. The node is present within the
MAIN domain, and is added as a child node under the cbass_main node.
Signed-off-by: Suman Anna <[email protected]>
Signed-off-by: Nishanth Menon <[email protected]>
Reviewed-by: Gowtham Tammana <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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An endpoint is not a device and it is recommended to use clocks property
in device node. RT5658 Codec binding already specifies the usage of
clocks property. Thus move the clocks from endpoint to device node.
Fixes: 5b4f6323096a ("arm64: tegra: Audio graph sound card for Jetson AGX Xavier")
Suggested-by: Rob Herring <[email protected]>
Signed-off-by: Sameer Pujar <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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rv1108.dtsi
A test with the command below gives this error:
/arch/arm/boot/dts/rv1108-evb.dt.yaml: watchdog@10360000:
clock-names:0: 'tclk' was expected
Comment from the dw_wdt.c file:
Try to request the watchdog dedicated timer clock source. It must
be supplied if asynchronous mode is enabled. Otherwise fallback
to the common timer/bus clocks configuration, in which the very
first found clock supply both timer and APB signals.
Like in the other Rockchip watchdog nodes the property "clock-names"
is not needed, so remove it.
make ARCH=arm dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml
Signed-off-by: Johan Jonker <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
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The watchdog compatible strings are suppose to be SoC orientated.
In the more recently added Rockchip rk322x.dtsi file only
the fallback string "snps,dw-wdt" is used, so add the new
compatible string:
"rockchip,rk3228-wdt", "snps,dw-wdt"
make ARCH=arm dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml
Signed-off-by: Johan Jonker <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
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The watchdog compatible strings are suppose to be SoC orientated.
In the more recently added Rockchip rv1108.dtsi file only
the fallback string "snps,dw-wdt" is used, so add the new
compatible string:
"rockchip,rv1108-wdt", "snps,dw-wdt"
make ARCH=arm dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml
Signed-off-by: Johan Jonker <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
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The watchdog compatible strings are suppose to be SoC orientated.
In the more recently added Rockchip rk3399.dtsi file only
the fallback string "snps,dw-wdt" is used, so add the new
compatible string:
"rockchip,rk3399-wdt", "snps,dw-wdt"
make ARCH=arm64 dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml
Signed-off-by: Johan Jonker <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
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The watchdog compatible strings are suppose to be SoC orientated.
In the more recently added Rockchip rk3328.dtsi file only
the fallback string "snps,dw-wdt" is used, so add the new
compatible string:
"rockchip,rk3328-wdt", "snps,dw-wdt"
make ARCH=arm64 dtbs_check
DT_SCHEMA_FILES=Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml
Signed-off-by: Johan Jonker <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Heiko Stuebner <[email protected]>
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