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* pci/host-xgene:
arm64: dts: Add APM X-Gene PCIe device tree nodes
PCI: xgene: Add APM X-Gene PCIe driver
Conflicts:
drivers/pci/host/Kconfig
drivers/pci/host/Makefile
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* pci/virtualization:
PCI: Add ACS quirk for AMD A88X southbridge devices
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Add the device tree nodes for APM X-Gene PCIe host controller and PCIe
clock interface. Since X-Gene SOC supports maximum 5 ports, 5 dts nodes
are added.
Signed-off-by: Tanmay Inamdar <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
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AMD has confirmed that peer-to-peer between two southbridge functions does
not occur.
Add a quirk to indicate that these functions are isolated even though they
don't have an ACS capability.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=81841
Signed-off-by: Marti Raudsepp <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Joel Schopp <[email protected]>
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* pci/host-designware:
PCI: designware: Remove open-coded bitmap operations
PCI: designware: Setup and clear exactly one MSI at a time
Conflicts:
drivers/pci/host/pcie-designware.c
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* pci/resource:
PCI: Add missing MEM_64 mask in pci_assign_unassigned_bridge_resources()
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Add the AppliedMicro X-Gene SOC PCIe host controller driver. The X-Gene
PCIe controller supports up to 8 lanes and GEN3 speed. The X-Gene SOC
supports up to 5 PCIe ports.
[bhelgaas: folded in MAINTAINERS and bindings updates]
Tested-by: Ming Lei <[email protected]>
Tested-by: Dann Frazier <[email protected]>
Signed-off-by: Tanmay Inamdar <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Liviu Dudau <[email protected]> (driver)
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Replace them by using the standard kernel bitmap ops. No functional
change, but makes the code a lot cleaner.
Signed-off-by: Lucas Stach <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Pratyush Anand <[email protected]>
Acked-by: Jingoo Han <[email protected]>
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* pci/msi:
PCI/MSI: Remove unnecessary temporary variable
PCI/MSI: Use __write_msi_msg() instead of write_msi_msg()
MSI/powerpc: Use __read_msi_msg() instead of read_msi_msg()
PCI/MSI: Use __get_cached_msi_msg() instead of get_cached_msi_msg()
PCI/MSI: Add "msi_bus" sysfs MSI/MSI-X control for endpoints
PCI/MSI: Remove "pos" from the struct msi_desc msi_attrib
PCI/MSI: Remove unused kobject from struct msi_desc
PCI/MSI: Rename pci_msi_check_device() to pci_msi_supported()
PCI/MSI: Move D0 check into pci_msi_check_device()
PCI/MSI: Remove arch_msi_check_device()
irqchip: armada-370-xp: Remove arch_msi_check_device()
PCI/MSI/PPC: Remove arch_msi_check_device()
Conflicts:
drivers/pci/host/pcie-designware.c
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* pci/host-generic:
arm64: Add architectural support for PCI
PCI: Add pci_remap_iospace() to map bus I/O resources
of/pci: Add support for parsing PCI host bridge resources from DT
of/pci: Add pci_get_new_domain_nr() and of_get_pci_domain_nr()
PCI: Add generic domain handling
of/pci: Fix the conversion of IO ranges into IO resources
of/pci: Move of_pci_range_to_resource() to of/address.c
ARM: Define PCI_IOBASE as the base of virtual PCI IO space
of/pci: Add pci_register_io_range() and pci_pio_to_address()
asm-generic/io.h: Fix ioport_map() for !CONFIG_GENERIC_IOMAP
Conflicts:
drivers/pci/host/pci-tegra.c
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* pci/aer:
PCI/AER: Rename PCI_ERR_UNC_TRAIN to PCI_ERR_UNC_UND
PCI/AER: Add additional PCIe AER error strings
trace, RAS: Add additional PCIe AER error strings
trace, RAS: Replace bare numbers with #defines for PCIe AER error strings
* pci/virtualization:
PCI: Add ACS quirk for Intel 10G NICs
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The only use of "status" is to hold a value which is immediately returned,
so just return and remove the variable directly.
Signed-off-by: Bjorn Helgaas <[email protected]>
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default_restore_msi_irq() already has the struct msi_desc pointer required
by __write_msi_msg(), so call it directly instead of having write_msi_msg()
look it up from the IRQ.
No functional change.
[bhelgaas: split into separate patch]
Signed-off-by: Yijing Wang <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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rtas_setup_msi_irqs() already has the struct msi_desc pointer required by
__read_msi_msg(), so call it directly instead of having read_msi_msg() look
it up from the IRQ.
No functional change.
[bhelgaas: changelog]
Signed-off-by: Yijing Wang <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Michael Ellerman <[email protected]>
CC: Benjamin Herrenschmidt <[email protected]>
CC: [email protected]
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Both callers of get_cached_msi_msg() start with a struct irq_data pointer,
look up the corresponding IRQ number, and pass it to get_cached_msi_msg(),
which then uses irq_get_irq_data() to look up the struct irq_data again to
call __get_cached_msi_msg().
Since we already have the struct irq_data, call __get_cached_msi_msg()
directly and skip the lookup work done by get_cached_msi_msg().
No functional change.
[bhelgaas: changelog]
Signed-off-by: Yijing Wang <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
CC: Tony Luck <[email protected]>
CC: [email protected]
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The "msi_bus" sysfs file for bridges sets a bus flag to allow or disallow
future driver requests for MSI or MSI-X. Previously, the sysfs file
existed for endpoints but did nothing.
Add "msi_bus" support for endpoints, so an administrator can prevent the
use of MSI and MSI-X for individual devices.
Note that as for bridges, these changes only affect future driver requests
for MSI or MSI-X, so drivers may need to be reloaded.
Add documentation for the "msi_bus" sysfs file.
[bhelgaas: changelog, comments, add "subordinate", add endpoint printk,
rework bus_flags setting, make bus_flags printk unconditional]
Signed-off-by: Yijing Wang <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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"msi_attrib.pos" is only used for MSI (not MSI-X), and we already cache the
MSI capability offset in "dev->msi_cap".
Remove "pos" from the struct msi_attrib and use "dev->msi_cap" directly.
[bhelgaas: changelog, fix whitespace]
Signed-off-by: Yijing Wang <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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After commit 1c51b50c2995 ("PCI/MSI: Export MSI mode using attributes, not
kobjects"), the kobject in struct msi_desc is unused.
Remove the unused struct kobject from struct msi_desc.
[bhelgaas: changelog]
Fixes: 1c51b50c2995 ("PCI/MSI: Export MSI mode using attributes, not kobjects")
Signed-off-by: Yijing Wang <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Greg Kroah-Hartman <[email protected]>
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Rename pci_msi_check_device() to pci_msi_supported() for clarity. Note
that pci_msi_supported() returns true if MSI/MSI-X is supported, so code
like:
if (pci_msi_supported(...))
reads naturally.
[bhelgaas: changelog, split to separate patch, reverse sense]
Signed-off-by: Alexander Gordeev <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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Both callers of pci_msi_check_device() check that the device is in D0
state, so move the check from the callers into pci_msi_check_device()
itself.
In pci_enable_msi_range(), note that pci_msi_check_device() never returns a
positive value any more, so the loop that called it until it returns zero
or negative is no longer necessary.
[bhelgaas: changelog, split to separate patch]
Signed-off-by: Alexander Gordeev <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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No architectures implement arch_msi_check_device() or the struct msi_chip
.check_device() method, so remove them.
Remove the "type" parameter to pci_msi_check_device() because it was only
used to call arch_msi_check_device() and is no longer needed.
[bhelgaas: changelog, split to separate patch]
Signed-off-by: Alexander Gordeev <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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Move MSI checks from arch_msi_check_device() to arch_setup_msi_irqs().
This makes the code more compact and allows removing
arch_msi_check_device() from generic MSI code.
Tested-by: Thomas Petazzoni <[email protected]>
Signed-off-by: Alexander Gordeev <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Jason Cooper <[email protected]>
CC: Thomas Gleixner <[email protected]>
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Move MSI checks from arch_msi_check_device() to arch_setup_msi_irqs().
This makes the code more compact and allows removing
arch_msi_check_device() from generic MSI code.
Signed-off-by: Alexander Gordeev <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Michael Ellerman <[email protected]>
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Use the generic PCI domain and OF functions to provide support for PCI
on arm64.
[bhelgaas: Change comments to use generic PCI, not just PCIe. Nothing at
this level is PCIe-specific.]
Signed-off-by: Liviu Dudau <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Catalin Marinas <[email protected]>
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Add pci_remap_iospace() to map bus I/O resources into the CPU virtual
address space. Architectures with special needs may provide their own
version, but most should be able to use this one.
This function is useful for PCI host bridge drivers that need to map the
PCI I/O resources into virtual memory space.
[bhelgaas: phys_addr description, drop temporary "err" variable]
Signed-off-by: Liviu Dudau <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Catalin Marinas <[email protected]>
CC: Arnd Bergmann <[email protected]>
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Provide a function to parse the PCI DT ranges that can be used to create a
pci_host_bridge structure together with its associated bus.
Signed-off-by: Liviu Dudau <[email protected]>
[make io_base parameter optional]
Signed-off-by: Robert Richter <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
CC: Arnd Bergmann <[email protected]>
CC: Grant Likely <[email protected]>
CC: Rob Herring <[email protected]>
CC: Catalin Marinas <[email protected]>
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Add pci_get_new_domain_nr() to allocate a new domain number and
of_get_pci_domain_nr() to retrieve the PCI domain number of a given device
from DT. Host bridge drivers or architecture-specific code can choose to
implement their PCI domain number policy using these two functions.
Using of_get_pci_domain_nr() guarantees a stable PCI domain number on every
boot provided that all host bridge controllers are assigned a number in the
device tree using "linux,pci-domain" property. Mixing use of
pci_get_new_domain_nr() and of_get_pci_domain_nr() is not recommended as it
can lead to potentially conflicting domain numbers being assigned to root
buses behind different host bridges.
Signed-off-by: Liviu Dudau <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
CC: Arnd Bergmann <[email protected]>
CC: Grant Likely <[email protected]>
CC: Rob Herring <[email protected]>
CC: Catalin Marinas <[email protected]>
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The handling of PCI domains (or PCI segments in ACPI speak) is usually a
straightforward affair but its implementation is currently left to the
architectural code, with pci_domain_nr(b) querying the value of the domain
associated with bus b.
This patch introduces CONFIG_PCI_DOMAINS_GENERIC as an option that can be
selected if an architecture wants a simple implementation where the value
of the domain associated with a bus is stored in struct pci_bus.
The architectures that select CONFIG_PCI_DOMAINS_GENERIC will then have to
implement pci_bus_assign_domain_nr() as a way of setting the domain number
associated with a root bus. All child buses except the root bus will
inherit the domain_nr value from their parent.
Signed-off-by: Catalin Marinas <[email protected]>
[Renamed pci_set_domain_nr() to pci_bus_assign_domain_nr()]
Signed-off-by: Liviu Dudau <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
CC: Arnd Bergmann <[email protected]>
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The ranges property for a host bridge controller in DT describes the
mapping between the PCI bus address and the CPU physical address. The
resources framework however expects that the IO resources start at a pseudo
"port" address 0 (zero) and have a maximum size of IO_SPACE_LIMIT. The
conversion from PCI ranges to resources failed to take that into account,
returning a CPU physical address instead of a port number.
Also fix all the drivers that depend on the old behaviour by fetching the
CPU physical address based on the port number where it is being needed.
Signed-off-by: Liviu Dudau <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Linus Walleij <[email protected]>
CC: Grant Likely <[email protected]>
CC: Rob Herring <[email protected]>
CC: Arnd Bergmann <[email protected]>
CC: Thierry Reding <[email protected]>
CC: Simon Horman <[email protected]>
CC: Catalin Marinas <[email protected]>
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The setup_irq function is supposed to set up exactly one MSI IRQ. Multiple
IRQ setup is handled differently, to respect the choices made by the upper
layers.
Also only clear one MSI IRQ at a time; the PCI core will call into this
function multiple times if it has to tear down more than one MSI IRQ.
Signed-off-by: Lucas Stach <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Pratyush Anand <[email protected]>
Acked-by: Jingoo Han <[email protected]>
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In 5b28541552ef ("PCI: Restrict 64-bit prefetchable bridge windows to
64-bit resources"), we added IORESOURCE_MEM_64 to the mask in
pci_assign_unassigned_root_bus_resources(), but not to the mask in
pci_assign_unassigned_bridge_resources().
Add IORESOURCE_MEM_64 to the pci_assign_unassigned_bridge_resources() type
mask.
Fixes: 5b28541552ef ("PCI: Restrict 64-bit prefetchable bridge windows to 64-bit resources")
Signed-off-by: Yinghai Lu <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
CC: [email protected] # v3.16+
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We need to enhance of_pci_range_to_resources() enough that it won't make
sense for it to be inline anymore. Move it to drivers/of/address.c, under
#ifdef CONFIG_PCI.
of_address.h previously implemented of_pci_range_to_resources()
unconditionally, regardless of any config options. The implementation in
address.c is defined only when CONFIG_OF_ADDRESS=y and CONFIG_PCI=y,
so add a dummy version to avoid build errors when CONFIG_OF or
CONFIG_OF_ADDRESS is not defined.
[bhelgaas: drop extra detail from changelog, move def under CONFIG_PCI,
add dummy of_pci_range_to_resource() for build errors (from Arnd)]
Signed-off-by: Liviu Dudau <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
CC: Grant Likely <[email protected]>
CC: Rob Herring <[email protected]>
CC: Arnd Bergmann <[email protected]>
CC: Catalin Marinas <[email protected]>
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This is needed for calls into OF code that parses PCI ranges. It signals
support for memory mapped PCI I/O accesses that are described by device
trees.
Signed-off-by: Liviu Dudau <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Catalin Marinas <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
CC: Russell King <[email protected]>
CC: Rob Herring <[email protected]>
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Some architectures do not have a simple view of the PCI I/O space and
instead use a range of CPU addresses that map to bus addresses. For some
architectures these ranges will be expressed by OF bindings in a device
tree file.
This patch introduces a pci_register_io_range() helper function with a
generic implementation that can be used by such architectures to keep track
of the I/O ranges described by the PCI bindings. If the PCI_IOBASE macro
is not defined, that signals lack of support for PCI and we return an
error.
In order to retrieve the CPU address associated with an I/O port, a new
helper function pci_pio_to_address() is introduced. This will search in
the list of ranges registered with pci_register_io_range() and return the
CPU address that corresponds to the given port.
[arnd: add dummy !CONFIG_OF pci_pio_to_address() to fix build errors]
Signed-off-by: Liviu Dudau <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Catalin Marinas <[email protected]>
Acked-by: Rob Herring <[email protected]>
CC: Grant Likely <[email protected]>
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The !CONFIG_GENERIC_IOMAP version of ioport_map() is wrong. It returns a
mapped, i.e., virtual, address that can start from zero and completely
ignores the PCI_IOBASE and IO_SPACE_LIMIT that most architectures that use
!CONFIG_GENERIC_MAP define.
Tested-by: Tanmay Inamdar <[email protected]>
Signed-off-by: Liviu Dudau <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Catalin Marinas <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
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Intel has verified there is no peer-to-peer between functions for the below
selection of 82598, 82599, and X520 10G NICs. These NICs lack an ACS
capability, so we're not able to determine this isolation without the help
of quirks.
Generalize the Solarflare quirk and add these Intel 10G NICs.
Signed-off-by: Alex Williamson <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: John Ronciak <[email protected]>
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* pci/host-designware:
PCI: designware: Add get_msi_data() to pcie_host_ops
PCI: designware: Rename get_msi_data() to get_msi_addr()
PCI: designware: Fix IO resource end address calculation
PCI: designware: Fix configuration base address when using 'reg'
PCI: designware: Use NULL instead of false
[bhelgaas: Fixup keystone for "PCI: designware: Rename get_msi_data() to
get_msi_addr()"]
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into next
* pci/enumeration:
PCI: Generate uppercase hex for modalias interface class
* pci/virtualization:
PCI: Add ACS quirk for Solarflare SFC9120 & SFC9140
PCI: Remove unused pci_get_dma_source()
PCI: Remove unused pci_find_upstream_pcie_bridge()
* pci/cleanup:
PCI: Remove assignment from complicated "if" conditions
PCI: Remove assignment from "if" conditions
PCI: Remove unnecessary curly braces
PCI: Add space before open parenthesis
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* pci/host-mvebu:
PCI: mvebu: Fix uninitialized variable in mvebu_get_tgt_attr()
* pci/host-spear:
PCI: spear: Pass config resource through reg property
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In PCIe r1.0, sec 5.10.2, bit 0 of the Uncorrectable Error Status, Mask,
and Severity Registers was for "Training Error." In PCIe r1.1, sec 7.10.2,
bit 0 was redefined to be "Undefined."
Rename PCI_ERR_UNC_TRAIN to PCI_ERR_UNC_UND to reflect this change.
No functional change.
[bhelgaas: changelog]
Signed-off-by: Chen, Gong <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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Add strings for all AER error bits defined in PCIe r3.0.
[bhelgaas: changelog, drop designated initializer change]
Signed-off-by: Chen, Gong <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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Add all AER error bits defined in PCIe r3.0.
[bhelgaas: changelog]
Signed-off-by: Chen, Gong <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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Replace bare numbers like "BIT(0)" with the existing #defines, e.g.,
PCI_ERR_COR_RCVR, to improve maintainability. This way grep will find more
uses of the #defines.
No functional change.
[bhelgaas: changelog]
Signed-off-by: Chen, Gong <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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* pci/hotplug:
PCI: pciehp: Stop disabling notifications during init
PCI: pciehp: Add more Slot Control debug output
PCI: pciehp: Fix wait time in timeout message
* pci/initdata:
x86/PCI: Mark PCI BIOS initialization code as such
x86/PCI: Constify pci_mmcfg_probes[] array
x86/PCI: Mark constants of pci_mmcfg_nvidia_mcp55() as __initconst
x86/PCI: Move __init annotation to the correct place
x86/PCI: Mark DMI tables as initialization data
* pci/misc:
PCI: Move PCI_VENDOR_ID_VMWARE to pci_ids.h
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Move PCI_VENDOR_ID_VMWARE from device-specific files to pci_ids.h.
It is useful to always have access to it, especially when accessing
subsystem_vendor_id on emulated devices.
[bhelgaas: keep pci_ids.h sorted and use lower-case hex]
Signed-off-by: Francesco Ruggeri <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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The modifications effectively change the value of len_tmp
in the case where the first condition is not met.
Signed-off-by: Quentin Lambert <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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The following Coccinelle semantic patch was used to find and correct cases
of assignments in "if" conditions:
@@
expression var, expr;
statement S;
@@
+ var = expr;
if(
- (var = expr)
+ var
) S
Signed-off-by: Quentin Lambert <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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Remove curly braces in simple "if" cases.
No functional change.
Signed-off-by: Quentin Lambert <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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Add space before open parenthesis as is conventional.
No functional change.
[bhelgaas: fix a few more in ibmphp, shpchp]
Signed-off-by: Quentin Lambert <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
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Add a struct pcie_host_ops .get_msi_data() method for platforms to return
their special MSI message data.
Signed-off-by: Minghuan Lian <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Mohit KUMAR <[email protected]>
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