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2023-01-24drm/amdgpu: limit AV1 to the first instance on VCN4 encodeDavid (Ming Qiang) Wu1-16/+46
AV1 is only supported on the first instance. Added vcn_v4_0_enc_find_ib_param() to help search for an IB param. Signed-off-by: David (Ming Qiang) Wu <[email protected]> Reviewed-by: Ruijing Dong <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-24drm/amd/display: Correcting prefetch mode for fast validateSaaem Rizvi1-7/+1
[WHY and HOW] When fast validating, we should be agnostic to any sort of optimizations such as supporting Pstate or stutter in Vblank. We should change our prefetch mode for fast validate to support none of these optimizations. For example, Valve Index running at 144Hz can only be validated without any support these optimizations. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Saaem Rizvi <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-24drm/amd/display: Set hvm_enabled flag for S/G modeRoman Li1-1/+1
[Why] After enabling S/G on dcn314 a screen corruption may be observed. HostVM flag should be set in S/G mode to be included in DML calculations. [How] In S/G mode gpu_vm_support flag is set. Use its value to init is_hvm_enabled. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-24drm/amdgpu/display/mst: adjust the logic in 2nd phase of updating payloadWayne Lin1-1/+5
[why & how] adjust the coding in dm_helpers_dp_mst_send_payload_allocation() for reading easily. Signed-off-by: Wayne Lin <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Acked-by: Harry Wentland <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-24drm/amdgpu/display/mst: adjust the naming of mst_port and port of aconnectorWayne Lin7-58/+59
[why & how] The term (i.e. port & mst_port) that we used to use in amdgpu is a bit confusing. Rename them to mst_output_port & mst_root respectively. Signed-off-by: Wayne Lin <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Acked-by: Harry Wentland <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-24drm/display/dp_mst: Correct the kref of port.Wayne Lin1-1/+3
[why & how] We still need to refer to port while removing payload at commit_tail. we should keep the kref till then to release. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2171 Signed-off-by: Wayne Lin <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Fixes: 4d07b0bc4034 ("drm/display/dp_mst: Move all payload info into the atomic state") Cc: [email protected] # 6.1 Acked-by: Harry Wentland <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Tested-by: Didier Raboud <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-24drm/drm_print: correct format problemWayne Lin1-1/+1
[why & how] __drm_dbg() parameter set format is wrong and not aligned with the format under CONFIG_DRM_USE_DYNAMIC_DEBUG is on. Fix it. Signed-off-by: Wayne Lin <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Acked-by: Harry Wentland <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-24drm/amdgpu/display/mst: update mst_mgr relevant variable when long HPDWayne Lin1-2/+12
[Why & How] Now the vc_start_slot is controlled at drm side. When we service a long HPD, we still need to run dm_helpers_dp_mst_write_payload_allocation_table() to update drm mst_mgr's relevant variable. Otherwise, on the next plug-in, payload will get assigned with a wrong start slot. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2171 Signed-off-by: Wayne Lin <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Fixes: 4d07b0bc4034 ("drm/display/dp_mst: Move all payload info into the atomic state") Cc: [email protected] # 6.1 Acked-by: Harry Wentland <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Tested-by: Didier Raboud <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-24drm/amdgpu/display/mst: limit payload to be updated one by oneWayne Lin1-12/+39
[Why] amdgpu expects to update payload table for one stream one time by calling dm_helpers_dp_mst_write_payload_allocation_table(). Currently, it get modified to try to update HW payload table at once by referring mst_state. [How] This is just a quick workaround. Should find way to remove the temporary struct dc_dp_mst_stream_allocation_table later if set struct link_mst_stream_allocatio directly is possible. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2171 Signed-off-by: Wayne Lin <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Fixes: 4d07b0bc4034 ("drm/display/dp_mst: Move all payload info into the atomic state") Cc: [email protected] # 6.1 Acked-by: Harry Wentland <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Tested-by: Didier Raboud <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-24drm/amdgpu/display/mst: Fix mst_state->pbn_div and slot count assignmentsLyude Paul2-5/+24
Looks like I made a pretty big mistake here without noticing: it seems when I moved the assignments of mst_state->pbn_div I completely missed the fact that the reason for us calling drm_dp_mst_update_slots() earlier was to account for the fact that we need to call this function using info from the root MST connector, instead of just trying to do this from each MST encoder's atomic check function. Otherwise, we end up filling out all of DC's link information with zeroes. So, let's restore that and hopefully fix this DSC regression. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2171 Signed-off-by: Lyude Paul <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Fixes: 4d07b0bc4034 ("drm/display/dp_mst: Move all payload info into the atomic state") Cc: [email protected] # 6.1 Reviewed-by: Harry Wentland <[email protected]> Tested-by: Didier Raboud <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-24drm/amdgpu: skip psp suspend for IMU enabled ASICs mode2 resetTim Huang1-0/+12
The psp suspend & resume should be skipped to avoid destroy the TMR and reload FWs again for IMU enabled APU ASICs. Signed-off-by: Tim Huang <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-24drm/amd/display: set allow_freesync parameter in DMAurabindo Pillai1-0/+1
[Why&how] There are cases where VRR is possible but not enabled. If allow_freesync parameter is not set, SubVP logic defaults to checking only the ignore MSA parameter that is always set if display is DRR capable, which breaks the system while trying to enable SubVP on multi monitor configs where freesync does not work due to Xorg limitation. SubVP uses allow_freesync parameter to check if SubVP + DRR case can be executed. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-24drm/amd/display: Revert "ignore msa parameter only if freesync is enabled"Aurabindo Pillai1-9/+2
This reverts commit 6ffa679916474b26c9b6c81003b42f2e1f0feda1. This commit introduced a regression in Unigine Heaven benchmark where the display would turn off due to incorrect handling of the parameter to ignore MSA packets. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-24drm/amd/display: Allow idle optimization after turning off all pipesAlvin Lee1-0/+10
[Why] In certain D3 cases (BOCO / BOMACO) the hardware is reset but software state still has idle_optimizations = true. This prevents us from entering idle optimizations again if no display is connected. [How] In hw init, reset the idle optimization state, and allow idle optimizations after all pipes have been turned off. Reviewed-by: Jun Lei <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-24drm/amd/display: Guard Freesync HDMI parsing with dc_lockStylon Wang1-2/+6
[Why] All calls into DC must be guarded by dc_lock because DC code is not safe against multi-thread or re-entry. [How] Hold dc_lock when calling DC interfaces to parse Freesync HDMI. Reviewed-by: Roman Li <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-24drm/amd/display: Speed up DML fast_validate pathIlya Bakoulin3-19/+31
[Why] Iterating over every voltage state when we need to validate thousands of configurations all at once (i.e. display hotplug) can take a significant amount of time. [How] Check just the highest voltage state when fast_validate is true to verify whether the configuration can work at all, then do a proper validation including all voltage states later when fast_validate is false. Reviewed-by: Nevenko Stupar <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Ilya Bakoulin <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-24drm/amd/display: Disable MALL SS and messages for PSR supported configsDillon Varone1-0/+7
[Description] The two features are not supported at the same time in driver at this time, so disable it. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-24drm/amd/display: force connector state when bpc changes during complianceQingqing Zhuo5-121/+209
[Why] During DP DSC compliance tests, bpc requested would change between sub-tests, which requires stream to be recommited. [How] Force connector to disconnect and reconnect whenever there is a bpc change in automated test. Reviewed-by: Jerry Zuo <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Signed-off-by: hersen wu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-24drm/amd/display: use a more appropriate return value in dp_retrieve_lttpr_cap()Hamza Mahfooz1-1/+1
Not all ASICs support LTTPR, however if they don't it doesn't mean that we have encountered unexpected behaviour. So, use DC_NOT_SUPPORTED instead of DC_ERROR_UNEXPECTED. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-24drm/amdgpu: declare firmware for new MES 11.0.4Li Ma1-0/+2
To support new mes ip block Signed-off-by: Li Ma <[email protected]> Reviewed-by: Yifan Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-24drm/amdgpu: enable imu firmware for GC 11.0.4Li Ma1-0/+1
The GC 11.0.4 needs load IMU to power up GFX before loads GFX firmware. Signed-off-by: Li Ma <[email protected]> Reviewed-by: Yifan Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-24drm/amd/pm: add missing AllowIHInterrupt message mapping for SMU13.0.0Evan Quan1-0/+1
Add SMU13.0.0 AllowIHInterrupt message mapping. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-24drm/amdgpu: remove unconditional trap enable on add gfx11 queuesJonathan Kim1-1/+0
Rebase of driver has incorrect unconditional trap enablement for GFX11 when adding mes queues. Reported-by: Graham Sider <[email protected]> Signed-off-by: Jonathan Kim <[email protected]> Reviewed-by: Graham Sider <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-19Documentation/gpu: update dGPU asic info tableAlex Deucher1-0/+2
Update to the latest launched dGPUs. Link: https://www.amd.com/en/graphics/radeon-rx-graphics Link: https://www.amd.com/en/graphics/amd-radeon-rx-laptops Reviewed-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-19drm/amd/display: remove duplicate included header filesye xingchen1-1/+0
resource.h is included more than once. Signed-off-by: ye xingchen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-19drm/amdgpu: return the PCIe gen and lanes from the INFO ioctlMarek Olšák3-4/+19
For computing PCIe bandwidth in userspace and troubleshooting PCIe bandwidth issues. Note that this intentionally fills holes and padding in drm_amdgpu_info_device. Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20790 Signed-off-by: Marek Olšák <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-19drm/amdgpu: print bo inode number instead of ptrPierre-Eric Pelloux-Prayer1-2/+2
This allows to correlate the infos printed by /sys/kernel/debug/dri/n/amdgpu_gem_info to the ones found in /proc/.../fdinfo and /sys/kernel/debug/dma_buf/bufinfo. Signed-off-by: Pierre-Eric Pelloux-Prayer <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-19drm/amdgpu: retire unused get_umc_v6_7_channel_indexTao Zhou1-7/+0
Fix the following compile warning: drivers/gpu/drm/amd/amdgpu/umc_v6_7.c:53:24: warning: unused function 'get_umc_v6_7_channel_index' [-Wunused-function] static inline uint32_t get_umc_v6_7_channel_index(struct amdgpu_device *adev, ^ 1 warning generated. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-19drm/amdgpu: Optimize sdma ras block initialization code for sdma v4_0YiPeng Chai1-16/+5
Optimize sdma ras block initialization code for sdma v4_0. Signed-off-by: YiPeng Chai <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-19drm/amd/display: fix hdmi_encoded_link_bw definitionArnd Bergmann1-6/+0
Some of the data structures are hidden when CONFIG_DRM_AMD_DC_DCN is disabled, which leads to a link failure: drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_dp_capability.c:234:21: error: 'union hdmi_encoded_link_bw' declared inside parameter list will not be visible outside of this definition or declaration [-Werror] 234 | const union hdmi_encoded_link_bw hdmi_encoded_link_bw) | ^~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_dp_capability.c:234:42: error: parameter 2 ('hdmi_encoded_link_bw') has incomplete type 234 | const union hdmi_encoded_link_bw hdmi_encoded_link_bw) | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_dp_capability.c:232:17: error: function declaration isn't a prototype [-Werror=strict-prototypes] 232 | static uint32_t intersect_frl_link_bw_support( | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_dp_capability.c: In function 'get_active_converter_info': drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_dp_capability.c:1126:76: error: storage size of 'hdmi_encoded_link_bw' isn't known 1126 | union hdmi_encoded_link_bw hdmi_encoded_link_bw; | ^~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_dp_capability.c:1130:101: error: 'struct <anonymous>' has no member named 'MAX_ENCODED_LINK_BW_SUPPORT' 1130 | hdmi_color_caps.bits.MAX_ENCODED_LINK_BW_SUPPORT); There is probably no need to hide the data structure, and removing the #ifdef makes it build cleanly. Fixes: d5a43956b73b ("drm/amd/display: move dp capability related logic to link_dp_capability") Signed-off-by: Arnd Bergmann <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-19drm/amd/display: fix dp_retrieve_lttpr_cap() return valueArnd Bergmann1-3/+3
gcc-13 notices a mismatch between the return type of dp_retrieve_lttpr_cap() and the returned value: drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_dp_capability.c: In function 'dp_retrieve_lttpr_cap': drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_dp_capability.c:1465:24: error: implicit conversion from 'enum <anonymous>' to 'enum dc_status' [-Werror=enum-conversion] 1465 | return false; | ^~~~~ Change the value to an actual dc_status code and remove the bogus initialization that was apparently meant to get returned here. Fixes: b473bd5fc333 ("drm/amd/display: refine wake up aux in retrieve link caps") Signed-off-by: Arnd Bergmann <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-19drm/amdgpu: Add sdma ras function on sdma v6_0_3YiPeng Chai3-0/+60
Add sdma ras function on sdma v6_0_3. Signed-off-by: YiPeng Chai <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-19drm/amd/display: disable S/G display on DCN 3.1.4Alex Deucher1-1/+0
Causes flickering or white screens in some configurations. Disable it for now until we can fix the issue. Cc: [email protected] Cc: [email protected] Acked-by: Christian König <[email protected]> Reviewed-by: Roman Li <[email protected]> Reviewed-by: Yifan Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-19drm/amd/display: disable S/G display on DCN 3.1.5Alex Deucher1-1/+0
Causes flickering or white screens in some configurations. Disable it for now until we can fix the issue. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2354 Cc: [email protected] Cc: [email protected] Acked-by: Christian König <[email protected]> Reviewed-by: Yifan Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-19drm/amd: decrease message about missing PSP runtime database to debugMario Limonciello1-1/+1
Laptops with APUs from a variety of manufacturers and generations show a warning about a missing PSP runtime database. As it's not required for PSP to dump this database into framebuffer, decrease messages about it missing to debug. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-19drm/amd/display: Decrease messaging about DP alt mode state to debugMario Limonciello1-1/+1
Currently plugging in a USB-C device that issues an HPD will emit a warning level message `DP Alt mode state on HPD: %d`. This is needlessly noisy for most people, decrease it to debug so that it can be turned on by dynamic debug as needed. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-19drm/amdgpu/vcn4: fail to schedule IB for AV1 if VCN0 is harvestedAlex Deucher1-0/+4
Only VCN0 supports AV1. Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-19drm/amdgpu/soc21: don't expose AV1 if VCN0 is harvestedAlex Deucher1-13/+48
Only VCN0 supports AV1. Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-19drm/amdgpu/vcn3: fail to schedule IB for AV1 if VCN0 is harvestedAlex Deucher1-0/+4
Only VCN0 supports AV1. Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-19drm/amdgpu/nv: don't expose AV1 if VCN0 is harvestedAlex Deucher1-20/+81
Only VCN0 supports AV1. Reviewed-by: Leo Liu <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-19Documentation/gpu: Add Raphael to apu-asic-info-tableMario Limonciello1-0/+1
Raphael launched in 2022 but was missed to add to this table. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-19Documentation/gpu: Add Mendocino to apu-asic-info-tableMario Limonciello1-0/+1
Mendocino launched in 2023 and uses the new naming scheme for APU processors. Link: https://community.amd.com/t5/corporate/announcing-new-model-numbers-for-2023-mobile-processors/ba-p/543985 Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-19Documentation/gpu: Update lines for GREEN_SARDINE and YELLOW_CARPMario Limonciello1-2/+2
These products have launched, so add matching codenames. Also AMD has announced that both of these products have new refresh variants that launch in 2023 using the new naming scheme, so add that information. Link: https://community.amd.com/t5/corporate/announcing-new-model-numbers-for-2023-mobile-processors/ba-p/543985 Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-19Documentation/gpu: Add MP0 version to apu-asic-info-tableMario Limonciello2-9/+9
MP0 version is useful to know to figure out which firmware is intended for a platform. Add a column for all supported APUs. v2: squash in column fix (Mario) Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-18drm/amdgpu: allow multipipe policy on ASICs with one MECLang Yu1-0/+3
Always enable multipipe policy on ASICs with GC VERSION > 9.0.0 instead of MEC number > 1. This will allow multipipe policy on ASICs with one MEC, e.g., gfx11 APUs. Signed-off-by: Lang Yu <[email protected]> Reviewed-by: Aaron Liu <[email protected]> Reviewed-by: Yifan Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-18drm/amdgpu: correct MEC number for gfx11 APUsLang Yu1-2/+9
There is only one MEC on these APUs. Signed-off-by: Lang Yu <[email protected]> Reviewed-by: Aaron Liu <[email protected]> Reviewed-by: Yifan Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-18drm/amd/display: fix issues with driver unloadHamza Mahfooz2-5/+0
Currently, we run into a number of WARN()s when attempting to unload the amdgpu driver (e.g. using "modprobe -r amdgpu"). These all stem from calling drm_encoder_cleanup() too early. So, to fix this we can stop calling drm_encoder_cleanup() from amdgpu_dm_fini() and instead have it be called from amdgpu_dm_encoder_destroy(). Also, we don't need to free in amdgpu_dm_encoder_destroy() since mst_encoders[] isn't explicitly allocated by the slab allocator. Fixes: f74367e492ba ("drm/amdgpu/display: create fake mst encoders ahead of time (v4)") Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-18drm/amdgpu/vcn: Remove redundant indirect SRAM HW model checkGuilherme G. Piccoli1-78/+3
The HW model validation that guards the indirect SRAM checking in the VCN code path is redundant - there's no model that's not included in the switch, making it useless in practice [0]. So, let's remove this switch statement for good. [0] lore.kernel.org/amd-gfx/MN0PR12MB61013D20B8A2263B22AE1BCFE2C19@MN0PR12MB6101.namprd12.prod.outlook.com Suggested-by: Alex Deucher <[email protected]> Reviewed-by: Mario Limonciello <[email protected]> Cc: James Zhu <[email protected]> Cc: Lazar Lijo <[email protected]> Cc: Leo Liu <[email protected]> Cc: Sonny Jiang <[email protected]> Signed-off-by: Guilherme G. Piccoli <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-18drm/amdgpu/vcn: Adjust firmware names indentationGuilherme G. Piccoli1-19/+19
This is an incredibly trivial fix, just for the sake of "aesthetical" organization of the defines. Some were space based, most were tab based and there was a lack of "alignment", now it's all the same and aligned. Cc: James Zhu <[email protected]> Cc: Lazar Lijo <[email protected]> Cc: Leo Liu <[email protected]> Cc: Mario Limonciello <[email protected]> Cc: Sonny Jiang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Guilherme G. Piccoli <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amdgpu: Use the sched from entity for amdgpu_cs traceLeo Liu1-2/+2
The problem is that base sched hasn't been assigned yet at this moment, causing something like "ring=0" all the time from trace. mpv:cs0-3473 [002] ..... 129.047431: amdgpu_cs: ring=0, dw=48, fences=0 mpv:cs0-3473 [002] ..... 129.089125: amdgpu_cs: ring=0, dw=48, fences=0 mpv:cs0-3473 [002] ..... 129.130987: amdgpu_cs: ring=0, dw=48, fences=0 mpv:cs0-3473 [002] ..... 129.172478: amdgpu_cs: ring=0, dw=48, fences=0 Fixes: 4624459c84d7 ("drm/amdgpu: add gang submit frontend v6") Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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