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2016-11-23ARM: dts: koelsch: use demuxer for I2C1Simon Horman1-0/+35
Make it possible to fallback to GPIO for I2C1 on the EXIO-C connector. This is based on reference work for the I2C0 core of the lager/r8a7790 by Wolfram Sang. Signed-off-by: Simon Horman <[email protected]> [wsa: rebased and fixed aliases] Signed-off-by: Wolfram Sang <[email protected]>
2016-11-23ARM: dts: lager: use demuxer for IIC1/I2C1Simon Horman1-2/+37
Make it possible to select which I2C1 IP core you want to run on the EXIO-A connector. This is based on reference work for the I2C0 core of the lager board by Wolfram Sang. Signed-off-by: Simon Horman <[email protected]> [wsa: rebased and fixed aliases] Signed-off-by: Wolfram Sang <[email protected]>
2016-11-23ARM: dts: lager: rename and reindex i2cexioSimon Horman1-5/+7
The rename from i2cexio to i2cexio0 is in preparation for adding i2cexio1 which will use the demuxer for IIC1/I2C1. The reindexing from i2c8 to i2c10 is to allow space for grouping of additional GPIO buses to be added by follow-up patches to support demuxing of other i2c buses. Also note that fallback to GPIO is not provided by the hardware for IIC0/I2C0. Signed-off-by: Simon Horman <[email protected]> [wsa: rebased, fixed alias and removed typo in commit message] Signed-off-by: Wolfram Sang <[email protected]>
2016-11-23ARM: dts: r8a7794: Use SYSC "always-on" PM Domain for soundGeert Uytterhoeven1-2/+2
Hook up the Audio-DMAC and sound device nodes to the SYSC "always-on" PM Domain, for a more consistent device-power-area description in DT. Cfr. commit 0761ff2ad0c581f3 ("ARM: dts: r8a7794: Add SYSC PM Domains"). Fixes: 320d6c5a08a4abd3 ("ARM: dts: r8a7794: add sound support") Fixes: 298e4ee3d213a076 ("ARM: dts: r8a7794: add Audio-DMAC support") Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Simon Horman <[email protected]>
2016-11-23ARM: dts: r8a7794: Correct hsusb parent clockGeert Uytterhoeven1-1/+1
The parent clock of the HSUSB clock is the HP clock, not the MP clock. Fixes: c7bab9f929e51761 ("ARM: shmobile: r8a7794: Add USB clocks to device tree") Signed-off-by: Geert Uytterhoeven <[email protected]> Acked-by: Yoshihiro Shimoda <[email protected]> Signed-off-by: Simon Horman <[email protected]>
2016-11-23ARM: dts: alt: Fix PFC names for DUJacopo Mondi1-2/+2
Update the PFC pin groups and function names of DU interface for r8a7794 ALT board. The currently specified pin groups and function names prevented PFC and DU interfaces from being correctly configured: sh-pfc e6060000.pin-controller: function 'du' not supported sh-pfc e6060000.pin-controller: invalid function du in map table sh-pfc e6060000.pin-controller: function 'du' not supported sh-pfc e6060000.pin-controller: invalid function du in map table sh-pfc e6060000.pin-controller: function 'du' not supported sh-pfc e6060000.pin-controller: invalid function du in map table sh-pfc e6060000.pin-controller: function 'du' not supported sh-pfc e6060000.pin-controller: invalid function du in map table rcar-du: probe of feb00000.display failed with error -22 Signed-off-by: Jacopo Mondi <[email protected]> Acked-by: Sergei Shtylyov <[email protected]> Signed-off-by: Simon Horman <[email protected]>
2016-11-23Merge tag 'rzg-clock-defs-tag1'; commit '538321bd9718'; commit ↵Simon Horman4-0/+137
'97ca8402997c' into dt-for-v4.10 Renesas RZ/G1M and RZ/G1E CPG Core Clock Definitions Shared by clock drivers, and DTS files.
2016-11-23ARM: dts: exynos: Remove the cd-gpios property for eMMC of Odroid XU3/4Jaehoon Chung1-1/+0
Odroid XU3/4 didn't need to use the cd-gpios for detecting card. Because host controller has the CDETECT register through SDx_CDN line. Host controller can know whether card is inserted or not with this register. When I have checked the Odroid XU3/4, they are using CDETECT register (not using exteranl cd-gpio). Signed-off-by: Jaehoon Chung <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]>
2016-11-23ARM: dts: exynos: Specify snps, dwmac in compatible string for gmacNiklas Cassel1-1/+1
devicetree binding for stmmac states: - compatible: Should be "snps,dwmac-<ip_version>", "snps,dwmac" For backwards compatibility: "st,spear600-gmac" is also supported. No functional change intended. Signed-off-by: Niklas Cassel <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]>
2016-11-23ARM: shmobile: r8a7745: add power domain index macrosSergei Shtylyov1-0/+25
Add macros usable by the device tree sources to reference R8A7745 SYSC power domains by index. Based on the original (and large) patch by Dmitry Shifrin <[email protected]>. Signed-off-by: Sergei Shtylyov <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Simon Horman <[email protected]>
2016-11-22ARM: dts: sun6i: hummingbird-a31: Enable display output through VGA bridgeChen-Yu Tsai1-0/+67
The Hummingbird A31 board has a VGA DAC which converts RGB output from the LCD interface to VGA analog signals. Add nodes for the VGA DAC, its power supply, and enable this part of the display pipeline. Signed-off-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2016-11-22ARM: dts: sun5i: Add touchscreen node to reference-design-tablet.dtsiHans de Goede2-24/+39
Just like on sun8i all sun5i tablets use the same interrupt and power gpios for their touchscreens. I've checked all known a13 fex files and only the UTOO P66 uses a different gpio for the interrupt. Add a touchscreen node to sun5i-reference-design-tablet.dtsi, which fills in the necessary gpios to avoid duplication in the tablet dts files, just like we do in sun8i-reference-design-tablet.dtsi. This will make future patches adding touchscreen nodes to a13 tablets simpler. Signed-off-by: Hans de Goede <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2016-11-22ARM: sunxi: Add the missing clocks to the pinctrl nodesMaxime Ripard7-11/+22
The pin controllers also use the two oscillators for debouncing. Add them to the DTs. Signed-off-by: Maxime Ripard <[email protected]> Acked-by: Linus Walleij <[email protected]> Acked-by: Chen-Yu Tsai <[email protected]>
2016-11-22ARM: dts: sun7i: bananapi-m1-plus: Enable USB OTGChen-Yu Tsai1-0/+20
The Bananapi M1+ supports USB OTG, with the PMIC doing VBUS sensing. Enable the USB OTG related functions. Signed-off-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2016-11-22ARM: dts: sun7i: bananapi-m1-plus: Add PMIC regulatorsChen-Yu Tsai1-4/+31
The Bananapi M1+, like other Allwinner A20 based boards, uses the AXP209 PMIC to supply its power. Add the AXP209 regulators. Signed-off-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2016-11-22ARM: dts: sun7i: bananapi-m1-plus: Enable USB PHY for USB host supportChen-Yu Tsai1-0/+5
The 2 USB host ports are directly tied to the 2 USB hosts in the SoC. The 2 host pairs were already enabled, but the USB PHY wasn't. VBUS on the 2 ports are always on. Enable the USB PHY. Fixes: 04c85ecad32a ("ARM: dts: sun7i: Add dts file for Bananapi M1 Plus board") Signed-off-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2016-11-22ARM: sun8i: sina33: Enable USB gadgetMaxime Ripard1-0/+5
The micro-USB on the SinA33 has a somewhat interesting design in the sense that it has a micro USB connector, but the VBUS is (supposed to be) controlled through an (unpopulated) jumper. Obviously, that doesn't work really well, and only the peripheral mode really works. Still enable it. Signed-off-by: Maxime Ripard <[email protected]>
2016-11-22ARM: dts: sun8i: reference-design-tablet: ldo_io1 is vcc-touchscreenHans de Goede2-7/+7
On some Q8 and other tablets ldo_io1 is used as vcc-touchscreen, config at as such in sun8i-reference-design-tablet.dtsi. Note that it will only be enabled when it us actually referenced by a foo-supply property in the touchscreen node, so for tablets which do not use ldo_io1 as vcc-touchscreen, it will be disabled. Signed-off-by: Hans de Goede <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2016-11-22ARM: dts: sun8i: replace enable-sdio-wakeup with wakeup-source for BananaPi M1+Sudeep Holla1-1/+1
Though the mmc core driver will continue to support the legacy "enable-sdio-wakeup" property to enable SDIO as the wakeup source, "wakeup-source" is the new standard binding. This patch replaces the legacy "enable-sdio-wakeup" with the unified "wakeup-source" property in order to avoid any further copy-paste duplication. Cc: Chen-Yu Tsai <[email protected]> Cc: Maxime Ripard <[email protected]> Signed-off-by: Sudeep Holla <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2016-11-22ARM: gr8: evb: Add i2s codecMaxime Ripard1-1/+16
The GR8-EVB comes with a wm8978 codec connected to the i2s bus. Add a card in order to have it working Signed-off-by: Maxime Ripard <[email protected]>
2016-11-22ARM: dts: sun6i: sina31s: Enable internal audio codecChen-Yu Tsai1-0/+8
The SinA31s routes the SoC's LINEOUT pins to a line out jack, and MIC1 to a microphone jack, with MBIAS providing phantom power. Signed-off-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2016-11-22ARM: dts: sun6i: hummingbird: Enable internal audio codecChen-Yu Tsai1-0/+13
The Hummingbird A31 has headset and line in audio jacks and an onboard mic routed to the pins for the SoC's internal codec. The line out pins are routed to an onboard speaker amp, whose output is available on a pin header. Signed-off-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2016-11-22ARM: dts: sun6i: Add audio codec device nodeChen-Yu Tsai1-0/+13
The A31 SoC includes the Allwinner audio codec, capable of 24-bit playback up to 192 kHz and 24-bit capture up to 48 kHz. Signed-off-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2016-11-22ARM: gr8: evb: Enable SPDIFMaxime Ripard1-0/+18
The GR8-EVB has a SPDIF out connector. Enable it. Signed-off-by: Maxime Ripard <[email protected]> Acked-by: Chen-Yu Tsai <[email protected]>
2016-11-22ARM: dts: sun8i: Add SPI controller node in H3Milo Kim1-0/+32
H3 SPI subsystem is almost same as A31 SPI except buffer size, so those DT properties are reusable. Cc: Maxime Ripard <[email protected]> Cc: Chen-Yu Tsai <[email protected]> Signed-off-by: Milo Kim <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2016-11-22ARM: dts: sun8i: Add SPI pinctrl node in H3Milo Kim1-0/+14
H3 supports two SPI controllers. Four pins (MOSI, MISO, SCLK, SS) are configured through the pinctrl subsystem. Cc: Maxime Ripard <[email protected]> Cc: Chen-Yu Tsai <[email protected]> Signed-off-by: Milo Kim <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2016-11-22ARM: dts: sun8i: Add dts file for NanoPi M1 SBCMilo Kim1-0/+64
NanoPi M1 is the Allwinner H3 based board. This patch enables UART for debug console, LEDs, GPIO key switch, 3 USB host ports, a micro SD slot and related power and pin controls by using NanoPi common dtsi file. Cc: James Pettigrew <[email protected]> Signed-off-by: Milo Kim <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2016-11-22ARM: dts: sun8i: Use the common file in NanoPi NEO SBCMilo Kim1-78/+1
NanoPi common dtsi supports all components of NEO SBC, so just include it. Cc: James Pettigrew <[email protected]> Signed-off-by: Milo Kim <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2016-11-22ARM: dts: sun8i: Add common dtsi file for NanoPi SBCsMilo Kim1-0/+144
This patch provides a common file for NanoPi M1 and Neo SBC. Those have common features below. * UART0 * 2 LEDs * USB host (EHCI3, OHCI3) and PHY * MicroSD * GPIO key switch Cc: James Pettigrew <[email protected]> Signed-off-by: Milo Kim <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2016-11-22ARM: dts: sun9i: cubieboard4: Enable AP6330 WiFiChen-Yu Tsai1-0/+32
The board has a Ampak AP6330 WiFi/BT/FM module. Inside it is a Broadcom BCM4330 WiFi/BT/FM combo IC. The WiFi portion is connected to mmc1, with the enabling pin connected to PL2. The AC100 RTC provides a low power clock signal. Signed-off-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2016-11-22ARM: dts: sun9i: a80-optimus: Enable AP6330 WiFiChen-Yu Tsai1-0/+30
The board has a Ampak AP6330 WiFi/BT/FM module. Inside it is a Broadcom BCM4330 WiFi/BT/FM combo IC. The WiFi portion is connected to mmc1, with the enabling pin connected to PL2. The AC100 RTC provides a low power clock signal. Signed-off-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2016-11-22ARM: dts: sun9i: Add mmc1 pinmux settingChen-Yu Tsai1-0/+8
On the A80, mmc1 is available on pingroup G. Designs mostly use this to connect to an SDIO WiFi chip. Signed-off-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2016-11-22ARM: sun5i: chip: Add optional busesMaxime Ripard1-0/+14
The I2C1 and SPI2 buses are exposed on the CHIP headers, and are not explicitly dedicated to anything. Add them to the DTS with the muxing already set, but keep them disabled. Signed-off-by: Maxime Ripard <[email protected]> Acked-by: Chen-Yu Tsai <[email protected]>
2016-11-22ARM: sun5i: Add RGB 565 LCD pinsMaxime Ripard1-0/+10
Some boards use the LCD in RGB565. Enable the pin muxing option. Signed-off-by: Maxime Ripard <[email protected]> Acked-by: Chen-Yu Tsai <[email protected]>
2016-11-22ARM: sun5i: Add SPI2 pinsMaxime Ripard1-0/+14
All the sun5i have the SPI2 pins exposed on the PE bank. Add them to the DT. Signed-off-by: Maxime Ripard <[email protected]> Acked-by: Chen-Yu Tsai <[email protected]>
2016-11-22ARM: sun5i: Rename A10s pinsMaxime Ripard2-4/+4
The SPI2 pins on the sun5i PB bank are only available on the A10s. Rename the A10s only bank so that it doesn't confuse people on the other SoCs whose indexing would start at b. Signed-off-by: Maxime Ripard <[email protected]> Acked-by: Chen-Yu Tsai <[email protected]>
2016-11-22ARM: sun5i: chip: add a node for the w1 gpio controllerAntoine Tenart1-0/+14
The CHIP uses a 1-Wire bus to discover the DIPs. Enable the bus in the DT. Signed-off-by: Antoine Tenart <[email protected]> Acked-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2016-11-22ARM: sun5i: chip: Enable Wi-Fi SDIO chipMaxime Ripard1-0/+41
The WiFi chip is powered through a GPIO and two regulators in parallel. Since that case is not supported yet, just set them as always on before we rework the regulator framework to deal with those. Signed-off-by: Maxime Ripard <[email protected]> Acked-by: Chen-Yu Tsai <[email protected]>
2016-11-22ARM: gr8: Add CHIP Pro supportMaxime Ripard2-0/+267
The CHIP Pro is a small embeddable board. It features a GR8, an AXP209 PMIC, a 512MB SLC NAND and a WiFi/BT chip. Signed-off-by: Maxime Ripard <[email protected]> Acked-by: Chen-Yu Tsai <[email protected]>
2016-11-22ARM: gr8: Add UART3 pinsMaxime Ripard1-0/+14
The UART3 pins were missing from the DTSI. Add them. Signed-off-by: Maxime Ripard <[email protected]> Acked-by: Chen-Yu Tsai <[email protected]>
2016-11-22ARM: gr8: Add UART2 pinsMaxime Ripard1-0/+14
The UART2 pins were missing from the DTSI. Add them. Signed-off-by: Maxime Ripard <[email protected]> Acked-by: Chen-Yu Tsai <[email protected]>
2016-11-22ARM: gr8: Add missing pwm channel 1 pinMaxime Ripard1-0/+7
The PWM controller has two different channels, but only the first pin was exposed in the DTSI. Add the other one. Signed-off-by: Maxime Ripard <[email protected]> Acked-by: Chen-Yu Tsai <[email protected]>
2016-11-22ARM: gr8: Fix typo in the i2s mclk pin groupMaxime Ripard1-1/+1
There was a dumb copy and paste mistake here, fix it. Signed-off-by: Maxime Ripard <[email protected]> Acked-by: Chen-Yu Tsai <[email protected]>
2016-11-22ARM: gr8: Add the UART3Maxime Ripard1-0/+10
The GR8 has access to the UART3 controller, which was missing in the DTSI. Add it. Signed-off-by: Maxime Ripard <[email protected]> Acked-by: Chen-Yu Tsai <[email protected]>
2016-11-22ARM: dts: sun6i: Add A31 LCD0 RGB888 pinsChen-Yu Tsai1-0/+13
The LCD0 controller on the A31 can do RGB output up to 8 bits per channel. Add the pins for RGB888 output. Signed-off-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2016-11-22ARM: dts: sun6i: Add device nodes for first display pipelineChen-Yu Tsai2-0/+160
The A31 has 2 parallel display pipelines, which can be intermixed. However the driver currently only supports one of them. Signed-off-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2016-11-22ARM: dts: sunxi: Add cpu-supply for Olimex A20 EVBEmmanuel Vadot1-0/+4
sun7i-a20-olimex-som-evb.dts doesn't contain cpu-supply needed for voltage-scaling with cpufreq-dt so define it. The default voltages are defined in sun7i-a20.dtsi. Signed-off-by: Emmanuel Vadot <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2016-11-22ARM: sun5i: a13-olinuxino: Enable VGA bridgeMaxime Ripard1-0/+54
Now that we have support for the VGA bridges using our DRM driver, enable the display engine for the Olimex A13-Olinuxino. Signed-off-by: Maxime Ripard <[email protected]> Acked-by: Chen-Yu Tsai <[email protected]>
2016-11-22ARM: dts: sun6i: Sort pinmux setting nodesChen-Yu Tsai1-41/+41
The pinmux setting nodes for the A31 were added out of alphabetical order. Sort them. Signed-off-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2016-11-22ARM: gr8: Rename the DTSI and relevant DTSMaxime Ripard3-2/+2
Reviews have found that sun5i was a better prefix after all for the GR8. Rename the relevant device trees before it's too late. Signed-off-by: Maxime Ripard <[email protected]>
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