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2021-02-16drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable()Ville Syrjälä1-0/+6
The other DDI .enable_clock() functions are trying to protect us against pll==NULL. A bit tempted to throw out all the WARNs as just unnecessary noise, but I guess they might have some use when poking around the shared_dpll code (not sure it wouldn't oops elsewhere though). So let's unify it all and sprinkle in the missing WARNs for icl/dg1. Reviewed-by: Lucas De Marchi <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-16drm/i915: Sprinkle a few missing locks around shared DDI clock registersVille Syrjälä1-0/+8
The current code attempts to protect the RMWs into global clock routing registers with a mutex, but forgets to do so in a few places. Let's remedy that. Note that at the moment we serialize all modesets onto single wq, so this shouldn't actually matter. But maybe one day we wish to attempt parallel modesets again... Reviewed-by: Lucas De Marchi <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-16drm/i915: Use intel_de_rmw() for DDI clock routingVille Syrjälä1-49/+28
The DDI clock routing programming is riddled with shared registers, forcing us to do a lot of RMW. Switch over to intel_de_rmw() to make that a bit less obnoxious. Reviewed-by: Lucas De Marchi <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-16drm/i915: Extract icl+ .{enable,disable}_clock() vfuncsVille Syrjälä1-58/+99
For ICL+ we have several styles of clock routing for DDIs: 1) TC DDI + TC PHY -> needs DDI_CLK_SEL==MG/TBT part form intel_ddi_clk_{select,disable}() and ICL_DPCLKA_CFGCR0_TC_CLK_OFF part form icl_{map,unmap}_plls_to_ports() 2) ICL/TGL combo DDI + combo PHY -> just need the stuff from icl_{map,unmap}_plls_to_ports() 3) JSL/EHL TC DDI + combo PHY -> needs DDI_CLK_SEL==MG part from intel_ddi_clk_{select,disable}() and the full combo style clock selection from icl_{map,unmap}_plls_to_ports() 4) ADLS/RKL -> these use both TC and combo DDIs with combo PHYs, however they always use the full combo style clock selection as per icl_{map,unmap}_plls_to_ports() and do not use DDI_CLK_SEL at all, thus get treated the same as 2) We extract all that from the current mess in the following way: 1) icl_ddi_tc_{enable,disable}_clock() 2) icl_ddi_combo_{enable,disable}_clock() 3) jsl_ddi_tc_{enable,disable}_clock() 4) for now we reuse icl_ddi_combo_{enable,disable}_clock() here v2: s/dev_priv/i915/ (Lucas) Reviewed-by: Lucas De Marchi <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-16drm/i915: Convert DG1 over to .{enable,disable}_clock()Ville Syrjälä1-22/+21
Replace dg1_{map,unmap}_plls_to_ports() with the appropriate encoder vfuncs. And let's relocate the disable function next to the enable function while at it. Reviewed-by: Lucas De Marchi <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-16drm/i195: Extract cnl_ddi_{enable,disable}_clock()Ville Syrjälä1-20/+42
Extract the DDI clock routing for CNL into the new vfuncs. v2: s/dev_priv/i915/ (Lucas) Reviewed-by: Lucas De Marchi <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-16drm/i915: Extract skl_ddi_{enable,disable}_clock()Ville Syrjälä1-15/+38
Extract the DDI clock routing clode for skl/derivatives into the new encoder vfuncs. v2: s/dev_priv/i915/ (Lucas) Reviewed-by: Lucas De Marchi <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-16drm/i915: Extract hsw_ddi_{enable,disable}_clock()Ville Syrjälä3-6/+31
Yank out the HSW/BDW code from intel_ddi_clk_{select,disable}() and put it into the new encoder .{enable,disable}_clock() vfuncs. v2: s/dev_priv/i915/ (Lucas) v3: Deal with FDI Reviewed-by: Lucas De Marchi <[email protected]> #v2 Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-16drm/i915: Introduce .{enable,disable}_clock() encoder vfuncsVille Syrjälä4-9/+32
The current code dealing with the clock routing for DDI encoders is a maintenance nightmare. Let's start cleaning it up by allowing the encoder to provide vfuncs for enablign/disabling the clock. We leave them initially unimplemented, falling back to the old if-else approach. v2: Convert the FDI enable sequence Reviewed-by: Lucas De Marchi <[email protected]> #v2 Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-16drm/i915: Use intel_ddi_clk_select() for FDIVille Syrjälä3-8/+8
We want to put all DDI clock routing code into one place. Unify the FDI enable sequence to use the standard function instead of hand rolling its own. The disable sequence already uses the normal thing. Cc: Lucas De Marchi <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Lucas De Marchi <[email protected]>
2021-02-13drm/i915: move intel_init_audio_hooks inside displayLucas De Marchi2-2/+1
intel_init_audio_hooks() sets up hooks in the display struct and only makes sense when we have display. Move it inside intel_init_display_hooks() so it isn't called when we don't have display. Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-13drm/i915/display: move register functions to display/Lucas De Marchi3-43/+58
Now that all display-related functions are grouped in i915_driver_register(), move them to display/ so we reduce the amount of display calls from the rest of the driver. Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-13drm/i915: group display-related register callsLucas De Marchi1-30/+34
intel_gt_driver_register() may be called earlier than intel_opregion_register() and acpi_video_register(), so move it up. intel_display_debugfs_register() may be called later, together with the other display-related initializations. There is a slight change in behavior that sysfs files will show up before the display-related debugfs files, but that shouldn't be a problem - userspace shouldn't be relying in debugfs. This allows us to group all the display-related calls under a single check for "HAS_DISPLAY()" that can be later moved to a better place. Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-13drm/i915: stop registering if drm_dev_register() failsLucas De Marchi1-9/+11
If drm_dev_register() fails there is no reason to continue registering the driver and initializing. Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-12drm/i915: Try to detect sudden loss of MMIO accessMatt Roper1-0/+16
In rare circumstances bugs in PCI programming, broken BIOS, or failing hardware can cause the CPU to lose access to the MMIO BAR on dgfx platforms. This is a pretty catastrophic failure since all register reads come back with values of 0xFFFFFFFF. Let's check for this special case while doing our usual checks for unclaimed registers; the FPGA_DBG register we use for those checks on modern platforms has some unused bits that will always read back as 0 when things are behaving properly; we can use them as canaries to detect when MMIO itself has suddenly broken and try to print a more informative error message in the logs. v2: Let the detection function still return 'true' if we've lost our MMIO access. We'll still get an extra false positive message about an unclaimed register access, but we'll still honor the 'mmio_debug' limit and not spam the log. (Lucas) Cc: Lucas De Marchi <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Lucas De Marchi <[email protected]>
2021-02-12drm/i915: FPGA_DBG is display-specificMatt Roper3-4/+4
Although the bspec's description doesn't make it very clear, the hardware architects have confirmed that the FPGA_DBG register that we use to check for unclaimed MMIO accesses is display-specific and will only properly flag unclaimed MMIO transactions for registers in the display range. If a platform doesn't have display, FPGA_DBG itself will not be available and should not be checked. Let's move the feature flag into intel_device_info.display to more accurately reflect this. Given that we now know FPGA_DBG is display-specific, it could be argued that we should only check it on out intel_de_*() functions. However let's not make that change right now; keeping the checks in all of the existing locations still helps us catch cases where regular intel_uncore_*() functions use bad MMIO offset math / base addresses and accidentally wind up landing within an unused area within the display MMIO range. It will also help catch cases where userspace-initiated MMIO (e.g., IGT's intel_reg tool) attempt to read bad offsets within the display range. v2: Add missing hunk with the update to the HAS_FPGA_DBG_UNCLAIMED macro. (CI) Cc: Lucas De Marchi <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-12drm/i915/gen9_bc: Add W/A for missing STRAP config on TGP PCH + CML combosLyude Paul1-1/+8
Apparently the new gen9_bc platforms that Intel has introduced don't provide us with a STRAP config register to read from for initializing DDI B, C, and D detection. So, workaround this by hard-coding our strap config in intel_setup_outputs(). Changes since v4: * Split this into it's own commit Cc: Matt Roper <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Ville Syrjala <[email protected]> [originally from Tejas's work] Signed-off-by: Tejas Upadhyay <[email protected]> Signed-off-by: Lyude Paul <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-12drm/i915/gen9_bc: Introduce HPD pin mappings for TGP PCH + CML combosLyude Paul1-0/+10
Next, let's start introducing the HPD pin mappings for Intel's new gen9_bc platform in order to make hotplugging display connectors work. Since gen9_bc is just a TGP PCH along with a CML CPU, except with the same HPD mappings as ICL, we simply add a skl_hpd_pin function that is shared between gen9 and gen9_bc which handles both the traditional gen9 HPD pin mappings and the Icelake HPD pin mappings that gen9_bc uses. Changes since v4: * Split this into its own commit * Introduce skl_hpd_pin() like vsyrjala suggested and use that instead of sticking our HPD pin mappings in TGP code Cc: Matt Roper <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Ville Syrjala <[email protected]> [originally from Tejas's work] Signed-off-by: Tejas Upadhyay <[email protected]> Signed-off-by: Lyude Paul <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-12i915/perf: Drop the check for report reason in OAUmesh Nerlige Ramappa1-5/+0
After fixing the OA_TAIL_PTR corruption, there are no more reports with reason field of zero. Drop the check for report reason. Signed-off-by: Umesh Nerlige Ramappa <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Signed-off-by: Lionel Landwerlin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-12drm/i915/debugfs: HDCP capability enc NULL checkAnshuman Gupta1-3/+14
DP-MST connector encoder initializes at modeset Adding a connector->encoder NULL check in order to avoid any NULL pointer dereference. intel_hdcp_enable() already handle this but debugfs can also invoke the intel_{hdcp,hdcp2_capable}. Handling it gracefully. v2: - Use necessary lock and NULL check in i915_hdcp_sink_capability_show. [Imre] Reviewed-by: Imre Deak <[email protected]> Signed-off-by: Anshuman Gupta <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-11drm/i915/display: fix comment on skl strapsLucas De Marchi1-2/+3
We are not checking for specific SKUs and feedback from HW team is that it may not work since it was supposed to be fixed by the same time straps stopped to be used. So, just update comment. v2: Instead of removing the check, just update the comment since feedback from HW team was that it actually may not work Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-11drm/i915/gen9_bc: Introduce TGP PCH DDC pin mappingsLyude Paul2-0/+29
With the introduction of gen9_bc, where Intel combines Cometlake CPUs with a Tigerpoint PCH, we'll need to introduce new DDC pin mappings for this platform in order to make all of the display connectors work. So, let's do that. Changes since v4: * Split this into it's own patch - vsyrjala Changes since v5: * Rename gen9bc_port_to_ddc_pin() to gen9bc_tgp_port_to_ddc_pin() Cc: Matt Roper <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Ville Syrjala <[email protected]> [originally from Tejas's work] Signed-off-by: Tejas Upadhyay <[email protected]> Signed-off-by: Lyude Paul <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-11drm/i915/gen9_bc: Recognize TGP PCH + CML combosLyude Paul1-1/+2
Since Intel has introduced the gen9_bc platform, a combination of Tigerpoint PCHs and CML CPUs, let's recognize such platforms as valid and avoid WARNing on them. Changes since v4: * Split this into it's own patch - vsyrjala Cc: Matt Roper <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Ville Syrjala <[email protected]> [originally from Tejas's work] Signed-off-by: Tejas Upadhyay <[email protected]> Signed-off-by: Lyude Paul <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-11drm/i915/display: Handle lane polarity for DDI portUma Shankar3-0/+22
Lane Reversal is required for some of the DDI ports. This information is populated in VBT and driver should read the same and set the polarity while enabling the port. This patch handles the same. It helps fix a display blankout issue on DP ports on certain platforms. Signed-off-by: Uma Shankar <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-10drm/i915/display: Add DDR5 and LPDDR5 BW buddy page entriesJosé Roberto de Souza1-0/+8
Set the right BW buddy page mask for new memory types. BSpec: 49218 Cc: Clint Taylor <[email protected]> Cc: Matt Roper <[email protected]> Cc: Lucas De Marchi <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Reviewed-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-10drm/i915: Warn when releasing a frontbuffer while in useVille Syrjälä1-0/+2
Let's scream if we are about to release a frontbuffer which is still in use. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Chris Wilson <[email protected]>
2021-02-10drm/i915: Fix overlay frontbuffer trackingVille Syrjälä1-9/+8
We don't have a persistent fb holding a reference to the frontbuffer object, so every time we do the get+put we throw the frontbuffer object immediately away. And so the next time around we get a pristine frontbuffer object with bits==0 even for the old vma. This confuses the frontbuffer tracking code which understandably expects the old frontbuffer to have the overlay's bit set. Fix this by hanging on to the frontbuffer reference until the next flip. And just to make this a bit more clear let's track the frontbuffer explicitly instead of just grabbing it via the old vma. Cc: [email protected] Cc: Chris Wilson <[email protected]> Cc: Joonas Lahtinen <[email protected]> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1136 Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Fixes: 8e7cb1799b4f ("drm/i915: Extract intel_frontbuffer active tracking") Reviewed-by: Chris Wilson <[email protected]>
2021-02-10drm/i915: Disallow plane x+w>stride on ilk+ with X-tilingVille Syrjälä1-0/+27
ilk+ planes get notably unhappy when the plane x+w exceeds the stride. This wasn't a problem previously because we always aligned SURF to the closest tile boundary so the x offset never got particularly large. But now with async flips we have to align to 256KiB instead and thus this becomes a real issue. On ilk/snb/ivb it looks like the accesses just wrap early to the next tile row when scanout goes past the SURF+n*stride boundary, hsw/bdw suffer more heavily and start to underrun constantly. i965/g4x appear to be immune. vlv/chv I've not yet checked. Let's borrow another trick from the skl+ code and search backwards for a better SURF offset in the hopes of getting the x offset below the limit. IIRC when I ran into a similar issue on skl years ago it was causing the hardware to fall over pretty hard as well. And let's be consistent and include i965/g4x in the check as well, just in case I just got super lucky somehow when I wasn't able to reproduce the issue. Not that it really matters since we still use 4k SURF alignment for i965/g4x anyway. Fixes: 6ede6b0616b2 ("drm/i915: Implement async flips for vlv/chv") Fixes: 4bb18054adc4 ("drm/i915: Implement async flip for ilk/snb") Fixes: 2a636e240c77 ("drm/i915: Implement async flip for ivb/hsw") Fixes: cda195f13abd ("drm/i915: Implement async flips for bdw") Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Chris Wilson <[email protected]>
2021-02-09drm/i915/tgl+: Make sure TypeC FIA is powered up when initializing itImre Deak1-30/+37
The TypeC FIA can be powered down if the TC-COLD power state is allowed, so block the TC-COLD state when initializing the FIA. Note that this isn't needed on ICL where the FIA is never modular and which has no generic way to block TC-COLD (except for platforms with a legacy TypeC port and on those too only via these legacy ports, not via a DP-alt/TBT port). Cc: <[email protected]> # v5.10+ Cc: José Roberto de Souza <[email protected]> Reported-by: Paul Menzel <[email protected]> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/3027 Signed-off-by: Imre Deak <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jos� Roberto de Souza <[email protected]>
2021-02-09i915/perf: Add additional OA formats for gen12Umesh Nerlige Ramappa1-6/+3
Gen12 supports additional OA formats as compared to what was added earlier. Include the additional OA formats. Signed-off-by: Umesh Nerlige Ramappa <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Signed-off-by: Lionel Landwerlin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-09i915/perf: Move OA formats to single arrayUmesh Nerlige Ramappa1-17/+2
Variations in OA formats in the different gens has led to creation of several sparse arrays to store the formats. Move oa formats into a single array and format_mask to check for platform specific oa formats. Signed-off-by: Umesh Nerlige Ramappa <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Signed-off-by: Lionel Landwerlin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-09i915/perf: Store a mask of valid OA formats for a platformUmesh Nerlige Ramappa2-1/+70
Validity of an OA format is checked by using a sparse array of formats per gen. Instead maintain a mask of supported formats for a platform in the perf object. v2: Use set_bit and test_bit style for the format_mask (Chris) Signed-off-by: Umesh Nerlige Ramappa <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Signed-off-by: Lionel Landwerlin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-08drm/i915/rkl: Remove require_force_probe protectionTejas Upadhyay1-1/+0
Removing force probe protection from RKL platform. Did not observe warnings, errors, flickering or any visual defects while doing ordinary tasks like browsing and editing documents in a two monitor setup. Signed-off-by: Tejas Upadhyay <[email protected]> Acked-by: Chris Wilson <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/20201130124855.319226-1-tejaskumarx.surendrakumar.upadhyay@intel.com
2021-02-08drm/i915: Fix HAS_LSPCON macro for platforms between GEN9 and GEN10Ankit Nautiyal1-1/+1
Legacy LSPCON chip from MCA and Parade is only used for platforms between GEN9 and GEN10. Fixing the HAS_LSPCON macro to reflect the same. Signed-off-by: Ankit Nautiyal <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-08drm/i915: refactor skylake scaler code into new file.Dave Airlie14-564/+598
This moves the code from various places and consolidates it into one new file. v2: - rename skl_program_plane -> skl_program_plane_scaler (Ville) - also move skl_pfit_enable, and consequently make some skl_scaler_* functions static to skl_scaler.c (Ville) Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/2fa703ffc7b96a41c392fd5ebbd2e6e4ffb6fb05.1612536383.git.jani.nikula@intel.com
2021-02-08drm/i915: migrate i9xx plane get configDave Airlie3-119/+123
Migrate this code out like the skylake code. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/c003bd458a6bcc703e9e2fb05731fb7124012e8c.1612536383.git.jani.nikula@intel.com
2021-02-08drm/i915: migrate pll enable/disable code to intel_dpll.[ch]Dave Airlie6-515/+529
This moves the older i9xx/vlv/chv enable/disable to dpll file. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/7fa8c76b0f07f3ede9efd7c1f989f33fbc8c53a3.1612536383.git.jani.nikula@intel.com
2021-02-08drm/i915: move is_ccs_modifier to an inlineDave Airlie3-10/+9
There is no need for this to be out of line. Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/bb73a151b7b780f927edeb7e121449446592805d.1612536383.git.jani.nikula@intel.com
2021-02-08drm/i915: split fb scalable checks into g4x and skl versionsDave Airlie2-6/+5
This just cleans these up a bit. Signed-off-by: Dave Airlie <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/c91d924e93965515d2017dbf3c89c245ff6d52ea.1612536383.git.jani.nikula@intel.com
2021-02-08drm/i915: move pipe update code into crtc. (v2)Dave Airlie2-238/+241
Daniel suggested this should move here. v2: move vrr code. Signed-off-by: Dave Airlie <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/738c7aaeb63c7d2357ddd932f18787ec8a3cefeb.1612536383.git.jani.nikula@intel.com
2021-02-08drm/i915: migrate skl planes code new file (v5)Dave Airlie14-2287/+2374
Rework the plane init calls to do the gen test one level higher. Rework some of the plane helpers so they can live in new file, there is still some scope to clean up the plane/fb interactions later. v2: drop atomic code back, rename file to Ville suggestions, add header file. v3: move scaler bits back v4: drop wrong new includes (Ville) v5: integrate the ccs gen12 changes v6: fix unrelated code movement (Ville) Signed-off-by: Dave Airlie <[email protected]> [Jani: fixed up sparse warnings.] Signed-off-by: Jani Nikula <[email protected]> Reported-by: kernel test robot <[email protected]> Reported-by: Dan Carpenter <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/4e88a5c6b9ab3b93cc2b6c7d78c26ae86f6abbd0.1612536383.git.jani.nikula@intel.com
2021-02-05drm/i915: Use intel_hdmi_port_clock() moreVille Syrjälä1-13/+14
Replace the hand rolled intel_hdmi_port_clock() stuff with the real thing. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Mika Kahola <[email protected]>
2021-02-05drm/i915: Index min_{cdclk,voltage_level}[] with pipeVille Syrjälä1-4/+4
min_cdclk[] and min_voltage_level[] are supposed to be indexed with the pipe. Fix up a few cases where we index via the crtc index (via the atomic iterators) instead. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Mika Kahola <[email protected]>
2021-02-05drm/i915: migrate hsw fdi code to new file.Dave Airlie5-146/+156
Daniel asked for this, but it's a bit messy and I'm not sure how best to clean it up yet. Signed-off-by: Dave Airlie <[email protected]> [Jani: also moved fdi buf trans to intel_fdi.c.] Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/44491f2465549ea5c2e48cde5437fa232f77ab96.1612467466.git.jani.nikula@intel.com
2021-02-05drm/i915: refactor ddi translations into a separate file (v2)Dave Airlie4-1405/+1507
Ville suggested this, these tables are probably better being standalone. This fixes up the cnl/bxt interfaces to be like the others, the intel one I left alone since it has a few extra entrypoints. v2: add back missing rocketlake bits. Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Dave Airlie <[email protected]> [Jani: made some functions static] Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/def9eed2581d71863ccdf35f323b525facc2482c.1612467466.git.jani.nikula@intel.com
2021-02-05drm/i915: Make psr_safest_params and enable_psr2_sel_fetch parameters read onlyJosé Roberto de Souza1-2/+2
By mistake those 2 parameters were defined as read and write in the .h file while in the .c file it is read only. The intention here was to be read only to avoid the need of additional handling. Cc: Gwan-gyeong Mun <[email protected]> Cc: Petri Latvala <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Reviewed-by: Gwan-gyeong Mun <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-05drm/i915/display: Remove PSR2 on JSL and EHLEdmund Dea1-0/+6
While JSL and EHL eDP transcoder supports PSR2, the phy of this platforms only supports eDP 1.3, so removing PSR2 support as this feature was added in eDP 1.4. Signed-off-by: Edmund Dea <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-05drm/i915/display: Support Multiple Transcoders' PSR status on debugfsGwan-gyeong Mun1-0/+16
In order to support the PSR state of each transcoder, it adds i915_psr_status to sub-directory of each transcoder. v2: Change using of Symbolic permissions 'S_IRUGO' to using of octal permissions '0444' v5: Addressed JJani Nikula's review comments - Remove checking of Gen12 for i915_psr_status. - Add check of HAS_PSR() - Remove meaningless check routine. Signed-off-by: Gwan-gyeong Mun <[email protected]> Cc: José Roberto de Souza <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Anshuman Gupta <[email protected]> Reviewed-by: Anshuman Gupta <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-05drm/i915/display: Support PSR Multiple InstancesGwan-gyeong Mun10-376/+487
It is a preliminary work for supporting multiple EDP PSR and DP PanelReplay. And it refactors singleton PSR to Multi Transcoder supportable PSR. And this moves and renames the i915_psr structure of drm_i915_private's to intel_dp's intel_psr structure. It also causes changes in PSR interrupt handling routine for supporting multiple transcoders. But it does not change the scenario and timing of enabling and disabling PSR. And it not support multiple pipes with a single transcoder PSR case yet. v2: Fix indentation and add comments v3: Remove Blank line v4: Rebased v5: Rebased and Addressed Anshuman's review comment. - Move calling of intel_psr_init() to intel_dp_init_connector() v6: Address Anshuman's review comments - Remove wrong comments and add comments for a limit of supporting of a single pipe PSR v7: Update intel_psr_compute_config() for supporting multiple transcoder PSR on BDW+ v8: Address Anshuman's review comments - Replace DRM_DEBUG_KMS with drm_dbg_kms() / DRM_WARN with drm_warn() v9: Fix commit message v10: Rebased v11: Address Jose's review comment. - Reorder calling order of intel_psr2_program_trans_man_trk_ctl(). - In order to reduce changes keep the old name for drm_i915_private. - Change restrictions of multiple instances of PSR. v12: Address Jose's review comment. - Change the calling of intel_psr2_program_trans_man_trk_ctl() into commit_pipe_config(). - Change a checking order of CAN_PSR() and connector_status to original on i915_psr_sink_status_show(). - Drop unneeded intel_dp_update_pipe() function. - In order to wait a specific encoder which belong to crtc_state on intel_psr_wait_for_idle(), add checking of encoder. - Add an whitespace to comments. v13: Rebased and Address Jose's review comment. - Add and use for_each_intel_psr_enabled_encoder() macro. - In order to use correct frontbuffer_bit for each pipe, fix intel_psr_invalidate() and intel_psr_flush(). - Remove redundant or unneeded codes. - Update comments. v14: Address Jose's review comment - Add and use for_each_intel_encoder_can_psr() macro and for_each_intel_encoder_mask_can_psr() macro. - Add source_support member variable into intel_psr structure. - Update CAN_PSR() macro that checks source_support. - Move encoder's PSR availity check to psr_init() from psr_compute_config(). - Remove redundant or unneeded codes. v15: Remove wrong mutex lock/unlock of PSR from intel_psr2_program_trans_man_trk_ctl() Signed-off-by: Gwan-gyeong Mun <[email protected]> Cc: José Roberto de Souza <[email protected]> Cc: Juha-Pekka Heikkila <[email protected]> Cc: Anshuman Gupta <[email protected]> Reviewed-by: Anshuman Gupta <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-05drm/i915/display: support ddr5 mem typesClint Taylor3-2/+20
Add DDR5 and LPDDR5 return values from punit fw. BSPEC: 54023 Cc: Matt Roper <[email protected]> Cc: José Roberto de Souza <[email protected]> Signed-off-by: Clint Taylor <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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