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2022-09-01Documentation/gpu: Add an explanation about the DCN pipelineRodrigo Siqueira3-0/+2079
In the DCN code, we constantly talk about hardware pipeline, pipeline, or even just pipes, which is a concept that is not obvious to everyone. For this reason, this commit expands the DCN overview explanation by adding a new section that describes what a pipeline is from the DCN perspective. Changes since V1: - Rewrite the first paragraph that describes AMD hardware pipeline. Cc: Harry Wentland <[email protected]> Cc: Nicholas Kazlauskas <[email protected]> Cc: Bhawanpreet Lakha <[email protected]> Cc: Hersen Wu <[email protected]> Cc: Alex Hung <[email protected]> Cc: Pierre-Eric Pelloux-Prayer <[email protected]> Cc: Leo Li <[email protected]> Cc: Simon Ser <[email protected]> Cc: Pekka Paalanen <[email protected]> Cc: Sean Paul <[email protected]> Cc: Mark Yacoub <[email protected]> Cc: Pierre-Loup <[email protected]> Cc: Michel Dänzer <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-01Documentation/gpu: Add info table for ASICsRodrigo Siqueira3-0/+49
Amdgpu driver is used in an extensive range of devices, and each ASIC has some specific configuration. As a result of this variety, sometimes it is hard to identify the correct block that might cause the issue. This commit expands the amdgpu kernel-doc to alleviate this issue by introducing one ASIC table that describes dGPU and another one that shares the APU info. Cc: Harry Wentland <[email protected]> Cc: Nicholas Kazlauskas <[email protected]> Cc: Bhawanpreet Lakha <[email protected]> Cc: Hersen Wu <[email protected]> Cc: Alex Hung <[email protected]> Cc: Pierre-Eric Pelloux-Prayer <[email protected]> Cc: Leo Li <[email protected]> Cc: Simon Ser <[email protected]> Cc: Pekka Paalanen <[email protected]> Cc: Sean Paul <[email protected]> Cc: Mark Yacoub <[email protected]> Cc: Pierre-Loup <[email protected]> Cc: Michel Dänzer <[email protected]> Cc: Kent Russell <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-01drm/amd/amdgpu: skip ucode loading if ucode_size == 0Chengming Gui1-1/+1
Restrict the ucode loading check to avoid frontdoor loading error. Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-01drm/i915/slpc: Let's fix the PCODE min freq table setup for SLPCRodrigo Vivi3-10/+61
We need to inform PCODE of a desired ring frequencies so PCODE update the memory frequencies to us. rps->min_freq and rps->max_freq are the frequencies used in that request. However they were unset when SLPC was enabled and PCODE never updated the memory freq. v2 (as Suggested by Ashutosh): if SLPC is in use, let's pick the right frequencies from the get_ia_constants instead of the fake init of rps' min and max. v3: don't forget the max <= min return v4: Move all the freq conversion to intel_rps.c. And the max <= min check to where it belongs. v5: (Ashutosh) Fix old comment s/50 HZ/50 MHz and add a doc explaining the "raw format" Fixes: 7ba79a671568 ("drm/i915/guc/slpc: Gate Host RPS when SLPC is enabled") Cc: <[email protected]> # v5.15+ Cc: Ashutosh Dixit <[email protected]> Tested-by: Sushma Venkatesh Reddy <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Reviewed-by: Ashutosh Dixit <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-09-01drm/cmdline-parser: Use assert when neededMichał Winiarski1-40/+40
Expecting to observe a specific value, when the function responsible for setting the value has failed will lead to extra noise in test output. Use assert when the situation calls for it. Also - very small tidying up around the changed areas (whitespace). v2: Leave out the locals (drm_connector is huge) (lkp) Signed-off-by: Michał Winiarski <[email protected]> Reviewed-by: Maíra Canal <[email protected]> Signed-off-by: Maíra Canal <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-09-01drm/cmdline-parser: Merge negative testsMichał Winiarski1-190/+103
Negative tests can be expressed as a single parameterized test case, which highlights that we're following the same test logic (passing invalid cmdline and expecting drm_mode_parse_command_line_for_connector to fail), which improves readability. v2: s/negative/invalid to be consistent with other testcases in DRM Signed-off-by: Michał Winiarski <[email protected]> Reviewed-by: Maíra Canal <[email protected]> Signed-off-by: Maíra Canal <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-09-01gpu/drm/bridge/cadence: avoid flush_scheduled_work() usageTetsuo Handa1-1/+2
Like commit c4f135d643823a86 ("workqueue: Wrap flush_workqueue() using a macro") says, flush_scheduled_work() is dangerous and will be forbidden. We are on the way for removing all flush_scheduled_work() callers from the kernel, and this patch is for removing flush_scheduled_work() call from cadence driver. Since cdns-mhdp8546 driver uses 4 works mhdp->modeset_retry_work mhdp->hpd_work mhdp->hdcp.check_work mhdp->hdcp.prop_work I assume that flush_scheduled_work() in cdns_mhdp_remove() needs to wait for only these 4 works. Since mhdp->modeset_retry_work already uses cancel_work_sync(), I assume that flush_scheduled_work() needs to wait for only 3 works. But I came to wonder whether mhdp->hdcp.check_work should be flushed or cancelled. While flush_scheduled_work() waits for completion of works which were already queued to system_wq, mhdp->hdcp.check_work is a delayed work. That is, this work won't be queued to system_wq unless timeout expires. Current code will wait for mhdp->hdcp.check_work only if timeout already expired. If timeout is not expired yet, flush_scheduled_work() will fail to cancel mhdp->hdcp.check_work, and cdns_mhdp_hdcp_check_work() which is triggered by mhdp->hdcp.check_work will schedule hdcp->check_work, which is too late for flush_scheduled_work() to wait for completion of cdns_mhdp_hdcp_prop_work(). But since I couldn't get comments on how do we want to handle this race window [1], this patch chose "do nothing" for mhdp->hdcp.check_work and mhdp->hdcp.prop_work. That is, I assume that flush_scheduled_work() in cdns_mhdp_remove() needs to wait for only mhdp->hpd_work work. Link: https://lkml.kernel.org/r/[email protected] [1] Signed-off-by: Tetsuo Handa <[email protected]> Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-09-01drm/panfrost: Update io-pgtable APIRobin Murphy1-17/+27
Convert to io-pgtable's bulk {map,unmap}_pages() APIs, to help the old single-page interfaces eventually go away. Unmapping heap BOs still wants to be done a page at a time, but everything else can get the full benefit of the more efficient interface. Signed-off-by: Robin Murphy <[email protected]> Acked-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Steven Price <[email protected]> Signed-off-by: Steven Price <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/daef7f8c134d989c55636a5790d8c0fcaca1bae3.1661205687.git.robin.murphy@arm.com
2022-08-31drm/i915/slpc: Fix inconsistent locked returnRodrigo Vivi1-20/+20
Fix for intel_guc_slpc_set_min_freq() warn: inconsistent returns '&slpc->lock'. v2: Avoid with_intel_runtime_pm with the internal goto/return. (Ashutosh) Also standardize the 'ret' if this came from the efficient setup. And avoid the 'unlikely'. Fixes: 95ccf312a1e4 ("drm/i915/guc/slpc: Allow SLPC to use efficient frequency") Reported-by: kernel test robot <[email protected]> Reported-by: Dan Carpenter <[email protected]> Cc: Ashutosh Dixit <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Reviewed-by: Ashutosh Dixit <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-08-30drm/amdgpu: Remove the unneeded result variable 'r'ye xingchen1-4/+1
Return the value sdma_v4_0_start() directly instead of storing it in another redundant variable. Reported-by: Zeal Robot <[email protected]> Signed-off-by: ye xingchen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-30drm/amdgpu: add new ip block for MES 11.0.3Hawking Zhang1-0/+1
Add ip block support for mes v11_0_3. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Frank Min <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-30drm/amdgpu: add new ip block for GFX 11.0Hawking Zhang1-0/+1
Add ip block support for gfx v11_0_3. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Frank Min <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-30drm/amdgpu: Set GC family for GC 11.0.3Hawking Zhang1-0/+1
Set AMDGPU_FAMILY_GC_11_0_0. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Frank Min <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-30drm/amdgpu: enable imu_rlc_ram programming for v11_0_3Hawking Zhang4-1/+181
All gc v11_0_3 registers in gcvml2 range have different register offset from the ones in gc v11_0_0. v11_0_3 imu_rlc_ram programming has to be separated from v11_0_0 implementation v2: fix checkpatch errors (Alex) Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Frank Min <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-30drm/amdkfd: Added GFX 11.0.3 SupportDavid Belanger2-0/+9
Added missing cases for GFX 11.0.3 code in a few switch statements. Signed-off-by: David Belanger <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-30drm/amdgpu: init gfx config for gfx v11_0_3Hawking Zhang1-0/+2
initialize some gfx config for gfx v11_0_3 Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Frank Min <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-30drm/amdgpu: declare firmware for new MES 11.0.3Hawking Zhang1-0/+2
To support new mes ip block Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Frank Min <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-30drm/amdgpu: declare firmware for new GC 11.0.3Hawking Zhang1-0/+4
To support new gfx ip block Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Frank Min <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-30drm/amdgpu: add new ip block for GMC 11.0Hawking Zhang1-0/+1
Add ip block support for gmc v11_0_3. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Frank Min <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-30drm/amdgpu: initialize gmc sw config for v11_0_3Hawking Zhang1-0/+1
initialize gmc sw config for v11_0_3 Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Frank Min <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-30drm/amdgpu: add gfxhub_v3_0_3 supportYang Wang4-2/+550
add gfxhub_v3_0_3 support Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-30drm/amdgpu: add gc v11_0_3 ip headersFrank Min2-0/+56726
Add gc v11_0_3 register offset and shift masks header files v2: update registers (Alex) Signed-off-by: Frank Min <[email protected]> Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-30drm/amdgpu: only init tap_delay ucode when it's included in ucode binaryHawking Zhang1-25/+35
Not all the gfx10 variants need to integrate global tap_delay and per se tap_delay firmwares Only init tap_delay ucode when it does include in rlc ucode binary so driver doesn't send a null buffer to psp for firmware loading Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Jack Gui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-30drm/i915/ats-m: Add thread execution tuning settingMatt Roper4-0/+13
On client DG2 platforms, optimal performance is achieved with the hardware's default "age based" thread execution setting. However on ATS-M, switching this to "round robin after dependencies" provides better performance. We'll add a new "tuning" feature flag to the ATS-M device info to enable/disable this setting. Bspec: 68331 Cc: Lucas De Marchi <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Matt Atwood <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-08-30Revert "drm/i915/dg2: Add preemption changes for Wa_14015141709"Matt Roper2-4/+1
This reverts commit ca6920811aa5428270dd78af0a7a36b10119065a. The intent of Wa_14015141709 was to inform us that userspace can no longer control object-level preemption as it has on past platforms (i.e., by twiddling register bit CS_CHICKEN1[0]). The description of the workaround in the spec wasn't terribly well-written, and when we requested clarification from the hardware teams we were told that on the kernel side we should also probably stop setting FF_SLICE_CS_CHICKEN1[14], which is the register bit that directs the hardware to honor the settings in per-context register CS_CHICKEN1. It turns out that this guidance about FF_SLICE_CS_CHICKEN1[14] was a mistake; even though CS_CHICKEN1[0] is non-operational and useless to userspace, there are other bits in the register that do still work and might need to be adjusted by userspace in the future (e.g., to implement other workarounds that show up). If we don't set FF_SLICE_CS_CHICKEN1[14] in i915, then those future workarounds would not take effect. This miscommunication came to light because another workaround (Wa_16013994831) has now shown up that requires userspace to adjust the value of CS_CHICKEN[10] in certain circumstances. To ensure userspace's updates to this chicken bit are handled properly by the hardware, we need to make sure that FF_SLICE_CS_CHICKEN1[14] is once again set by the kernel. Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Matt Atwood <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-08-30MAINTAINERS: Add myself as a reviewer for panel-edp.cDouglas Anderson1-0/+5
panel-edp changes go through the drm-misc tree (as per the "DRM PANEL DRIVERS" entry in MAINTAINERS), but ever since splitting panel-edp out of panel-simple I've been trying to keep a close eye on it. Make that official by listing me as a reviewer. Signed-off-by: Douglas Anderson <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/20220822105340.1.I66a9a5577f9b0af66492ef13c47bc78ed85e5d6b@changeid
2022-08-30drm/i915/selftests: allow misaligned_pin test work with unmappable memoryAndrzej Hajda1-1/+1
In case of Small BAR configurations stolen local memory can be unmappable. Since the test does not touch the memory, passing I915_BO_ALLOC_GPU_ONLY flag to i915_gem_object_create_region, will prevent -ENOSPC error from _i915_gem_object_stolen_init. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6565 Signed-off-by: Andrzej Hajda <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Signed-off-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-08-30drm/bridge: it6505: Fix the order of DP_SET_POWER commandsPin-yen Lin1-4/+4
Send DP_SET_POWER_D3 command to the downstream before stopping DP, so the suspend process will not be interrupted by the HPD interrupt. Also modify the order in .atomic_enable callback to make the callbacks symmetric. Fixes: 46ca7da7f1e8 ("drm/bridge: it6505: Send DPCD SET_POWER to downstream") Signed-off-by: Pin-yen Lin <[email protected]> Reviewed-by: Robert Foss <[email protected]> Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-08-30drm/bridge: megachips: Fix a null pointer dereference bugZheyu Ma1-1/+3
When removing the module we will get the following warning: [ 31.911505] i2c-core: driver [stdp2690-ge-b850v3-fw] unregistered [ 31.912484] general protection fault, probably for non-canonical address 0xdffffc0000000001: 0000 [#1] PREEMPT SMP KASAN PTI [ 31.913338] KASAN: null-ptr-deref in range [0x0000000000000008-0x000000000000000f] [ 31.915280] RIP: 0010:drm_bridge_remove+0x97/0x130 [ 31.921825] Call Trace: [ 31.922533] stdp4028_ge_b850v3_fw_remove+0x34/0x60 [megachips_stdpxxxx_ge_b850v3_fw] [ 31.923139] i2c_device_remove+0x181/0x1f0 The two bridges (stdp2690, stdp4028) do not probe at the same time, so the driver does not call ge_b850v3_resgiter() when probing, causing the driver to try to remove the object that has not been initialized. Fix this by checking whether both the bridges are probed. Fixes: 11632d4aa2b3 ("drm/bridge: megachips: Ensure both bridges are probed before registration") Signed-off-by: Zheyu Ma <[email protected]> Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-08-30drm/dp: add drm_dp_phy_name() for getting DP PHY nameJani Nikula2-0/+34
Add a helper for getting the DP PHY name. In the interest of caller simplicity and to avoid allocations and passing in of buffers, duplicate the const strings to return. It's a minor penalty to pay for simplicity in all the call sites. v2: Rebase, add kernel-doc, ensure non-NULL always Cc: Ville Syrjälä <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/b08dc12a7e621a48ec35546d6cd1ed4b1434810d.1660553850.git.jani.nikula@intel.com
2022-08-29drm/amd/display: clean up some inconsistent indentingsYang Li1-3/+3
The indentation of statements in the same curly bracket should be consistent. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1892 Reported-by: Abaci Robot <[email protected]> Signed-off-by: Yang Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-29drm/amd/display: clean up some inconsistent indentingsYang Li1-10/+10
The indentation of statements in the same curly bracket should be consistent. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1890 Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1891 Reported-by: Abaci Robot <[email protected]> Signed-off-by: Yang Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-29drm/amd/display: clean up some inconsistent indentingsYang Li1-5/+8
The indentation of statements in the same curly bracket should be consistent. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1886 Reported-by: Abaci Robot <[email protected]> Signed-off-by: Yang Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-29drm/amd/display: clean up one inconsistent indentingYang Li3-9/+12
1. The indentation of statements in the same curly bracket should be consistent. 2. Variable declarations in the same function should be aligned. Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1887 Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1888 Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1889 Reported-by: Abaci Robot <[email protected]> Signed-off-by: Yang Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-29drm/amdgpu: add new ip block for LSDMA 6.0Hawking Zhang1-0/+1
Add ip block support for lsdma v6_0_3. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Frank Min <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-29drm/amdgpu: add new ip block for sdma 6.0Hawking Zhang1-0/+1
Add ip block support for sdma v6_0_3. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Frank Min <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-29drm/amdgpu: declare firmware for new SDMA 6.0.3Hawking Zhang1-0/+1
To support new sdma ip block Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Frank Min <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-29drm/amdgpu: enable smu block for smu 13.0.10John Clements1-0/+1
Force to enable smu block for SMU v13.0.10 Signed-off-by: John Clements <[email protected]> Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-29drm/amdgpu: added supported smu 13.0.10 sw pptableJohn Clements1-0/+2
added sw pptable id 6666 for smu 13.0.10 v2: fix checkpatch error (Alex) Signed-off-by: John Clements <[email protected]> Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-29drm/amd/pm: add smu_v13_0_10 driver if versionYang Wang2-0/+4
add smu_v13_0_10 driver if version Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-29drm/amd/pm: add smu_v13_0_10 supportYang Wang2-0/+2
add smu_v13_0_10 support. Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-29drm/amdgpu: add new ip block for PSP 13.0Frank Min1-0/+1
Add ip block support for psp v13_0_10. Signed-off-by: Frank Min <[email protected]> Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-29drm/amdgpu: added firmware module for psp 13.0.10John Clements1-0/+1
added missing firmware module Signed-off-by: John Clements <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-29drm/amdgpu: support psp v13_0_10 ip blockFrank Min2-0/+2
Add psp v13_0_10 ip block, initialize firmware and psp functions Signed-off-by: Frank Min <[email protected]> Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-29drm/amdgpu: add new ip block for SOC21Hawking Zhang1-0/+1
Add ip block support for soc21_common. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Frank Min <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-29drm/amdgpu: Enable pg/cg flags on GC11_0_3 for VCNSonny Jiang1-2/+5
This enable VCN PG, CG, DPG and JPEG PG, CG Signed-off-by: Sonny Jiang <[email protected]> Reviewed-by: Leo Liu <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-29drm/amdgpu: initialize common sw config for v11_0_3Hawking Zhang1-0/+5
init cp/pg_flags and extenal_rev_id Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Frank Min <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-29drm/amdgpu: drop gc 11_0_0 golden settingsHawking Zhang1-41/+0
driver doesn't need to program any gc 11_0_0 golden Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-29drm/amdkfd: remove redundant variables err and retJinpeng Cui1-7/+2
Return value from kfd_wait_on_events() and io_remap_pfn_range() directly instead of taking this in another redundant variable. Reported-by: Zeal Robot <[email protected]> Signed-off-by: Jinpeng Cui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-29drm/amd/display: remove redundant vertical_line_start variableJinpeng Cui1-4/+1
Return value from expression directly instead of taking this in another redundant variable. Reported-by: Zeal Robot <[email protected]> Signed-off-by: Jinpeng Cui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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