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2022-11-09dt-bindings: vendor-prefixes: Document JadardJagan Teki1-0/+2
Jadard Technology Inc. manufactures and distributes chips from Shenzhen. Add vendor prefix for it. Signed-off-by: Jagan Teki <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Linus Walleij <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-11-09dt-bindings: vendor-prefixes: Document ChongzhouJagan Teki1-0/+2
Chongzhou is a professional is a manufacturer of LCD panels from Shenzhen. Add vendor prefix for it. Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Jagan Teki <[email protected]> Signed-off-by: Linus Walleij <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2022-11-09Merge branch '00.06-gr-ampere' of ↵Dave Airlie407-13193/+15697
https://gitlab.freedesktop.org/skeggsb/nouveau into drm-next This is the pull request for a whole bunch of fixes and prep-work that was done to support Ampere acceleration prior to GSP-RM being available. It uses the ACR firmware released by NVIDIA in linux-firmware, as we do on earlier GPUs. The work to support running on top of GSP-RM also heavily depends on various pieces of this series. In addition to the new HW support, general stability of the driver should be improved, especially around recovering HW from bugs that can be generated by userspace driver components. Signed-off-by: Dave Airlie <[email protected]> From: Ben Skeggs <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/CABDvA==s+nZD0n7CuRWLPE=Pj+02CN13r+ZQJxoHQ_EmR+o=XQ@mail.gmail.com
2022-11-09drm/nouveau/gr/ga102: initial supportBen Skeggs15-9/+565
v2: - whitespace Signed-off-by: Ben Skeggs <[email protected]> Signed-off-by: Gourav Samaiya <[email protected]>
2022-11-09drm/nouveau/ltc/ga102: initial supportBen Skeggs4-1/+65
v2. fixup for ga103 early merge Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/acr/ga102: initial supportBen Skeggs28-14/+1091
v2. fixup for ga103 early merge Signed-off-by: Ben Skeggs <[email protected]> Signed-off-by: Gourav Samaiya <[email protected]>
2022-11-09drm/nouveau/fb/ga102: load and boot VPR scrubber FWBen Skeggs19-5/+551
v2. fixup for ga103 early merge Signed-off-by: Ben Skeggs <[email protected]> Signed-off-by: Gourav Samaiya <[email protected]>
2022-11-09drm/nouveau/gr/tu102: remove gv100_grctx_unkn88cBen Skeggs1-1/+0
Match RM. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/gr/tu102: add gv100_gr_init_4188a4Ben Skeggs3-1/+4
Match RM. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/gr/tu102-: fix support for sw_bundle64_initBen Skeggs5-6/+17
We weren't sending the high bits, though they're zero currently anyway. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/gr/tu102-: use sw_veid_bundle_init from firmwareBen Skeggs8-6/+44
NVIDIA provided this on Turing, but we kept using the hardcoded version from Volta (where they didn't). Switch to the firmware version prior to Ampere. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/gr/gv100-: drop a write from init_shader_exceptions()Ben Skeggs1-1/+0
Match RM. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/gr/gv100-: move init_419bd8() after sw_ctx loadBen Skeggs2-3/+3
Match RM. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/gr/gv100-: add NV_PGRAPH_PRI_PD_AB_DIST_CONFIG_1 to patch listBen Skeggs1-0/+2
Match RM. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/gr/gv100-: fix number of tile map registersBen Skeggs2-2/+3
Match RM. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/gr/gv100-: port smid mapping code from nvgpuBen Skeggs7-12/+219
Essentially ripped verbatim from NVGPU, comments and all, and adapted to nvkm's structs and style. - maybe fixes an nvgpu bug though, a small tweak was needed to match RM v2: - remove unnecessary WARN_ON Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/gr/gp100-: modify init_fecs_exceptionsBen Skeggs2-2/+2
Match RM. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/gr/gk20a,gm20b,gp10b: split out netlist parsing from fw loadingBen Skeggs2-67/+49
We'll want to reuse the former for loading from proper netlist images. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/gr/gp100-: fix number of zcull tile regsBen Skeggs2-3/+5
Match RM. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/gr/gf117-: make ppc_nr[gpc] accurateBen Skeggs8-9/+11
We're going to be pulling in a chunk of code from NVGPU to fixup our SMID mappings on Volta and above, which depends on ppc_nr[gpc] reflecting the actual number of PPCs present, not the maximum number. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/gr/gf100-: switch to newer style interrupt handlerBen Skeggs4-10/+26
Ampere. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/gr/gf100-: move some init to init_exception2()Ben Skeggs20-2/+32
Ampere. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/gr/gf100-: move some init to init_rop_exceptions()Ben Skeggs20-7/+37
Ampere. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/gr/gf100-: move reset during golden ctx init to fecs_reset()Ben Skeggs23-5/+36
Ampere. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/gr/gf100-: wfi after register-bashing golden initBen Skeggs1-0/+2
Match RM. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/gr/gf100-: gpfifo_ctl zero before initBen Skeggs1-0/+2
Match RM. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/gr/gf100-: wait for FE_PWR_MODE_AUTOBen Skeggs1-0/+4
This doesn't fix any known issue, but RM started doing it at some point, so presumably it's needed for something. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/gr/gf100-: call FECS HALT_PIPE method before RC resetBen Skeggs3-0/+46
Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/gr/gf100-: call FECS WFI_GOLDEN_SAVE methodBen Skeggs3-11/+39
This won't work on Ampere, and, it's questionable whether we should have been using our FW's method of storing the golden context image with NV's firmware to begin with. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/gr/gf100-: stop using NV_PGRAPH_FECS_CTXSW_MAILBOX_CLEARBen Skeggs1-7/+7
This doesn't work on Ampere for some reason, switch to directly modifying NV_PGRAPH_FECS_CTXSW_MAILBOX instead. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/gr/gf100-: make global attrib_cb actually globalBen Skeggs23-269/+241
This was thought to be per-channel initially - it's not. The backing pages for the VMM mappings are shared for all channels. - switches to more straight-forward patch interfaces - prepares for sub-context support - this is saving a *sizeable* amount of vram v2: - whitespace Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/gr/gf100-: move misc context patching out of attrib_cb funcsBen Skeggs6-20/+51
Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/gr/gf100-: make global bundle_cb actually globalBen Skeggs8-37/+46
This was thought to be per-channel initially - it's not. The backing pages for the VMM mappings are shared for all channels. - switches to more straight-forward patch interfaces - prepares for sub-context support Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/gr/gf100-: make global pagepool actually globalBen Skeggs9-50/+71
This was thought to be per-channel initially - it's not. The backing pages for the VMM mappings are shared for all channels. - switches to more straight-forward patch interfaces - prepares for sub-context support Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/gr/gf100-: generate golden context during first object allocBen Skeggs3-49/+26
Needed for GV100 (and only GV100 for some reason) for WFI_GOLDEN_SAVE. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/gr/gf100-: move some code around to make next commits nicerBen Skeggs1-52/+52
Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/fifo: expose function to read engine ctxsw statusBen Skeggs3-1/+18
Needed to support Ampere differences in gr/gf100-: Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/ltc: split color vs depth/stencil zbc countsBen Skeggs13-27/+42
These differ on Ampere. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/engine: add HAL for engine-specific rc reset procedureBen Skeggs3-2/+14
Will be used to improve gr reset on GF100 and newer. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/sec2: dump tracepc info on haltBen Skeggs3-0/+21
- useful to distinguish between different issues. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/acr: use common falcon HS FW code for ACR FWsBen Skeggs30-856/+648
Adds context binding and support for FWs with a bootloader to the code that was added to load VPR scrubber HS binaries, and ports ACR over to using all of it. - gv100 split from gp108 to handle FW exit status differences Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/fb/gp102-: unlock VPR right after devinitBen Skeggs3-9/+16
Under memory load, instmem allocations could end up in the regions of VRAM that are inaccessible right after boot, and be corrupted after a suspend/resume cycle as a result of being restored before booting the mem unlock firmware. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/fb: handle sysmem flush page from common codeBen Skeggs15-83/+80
- also executes pre-DEVINIT, so early boot is able to DMA sysmem Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/flcn: new code to load+boot simple HS FWs (VPR scrubber)Ben Skeggs10-66/+594
Adds the start of common interfaces to load and boot the HS binaries provided by NVIDIA that enable the usage of GR. ACR already handles most of this, but it's very much tied into ACR's init process, and there's other code that could benefit from reusing a lot of this stuff too (ie. VBIOS DEVINIT/PreOS, VPR scrubber). The VPR scrubber code is fairly independent, and a good first target. - adds better debug output to fw loading process, to ease bring-up/debug v2: - whitespace, 0->false Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/flcn: rework falcon resetBen Skeggs16-143/+185
Mostly preparation to fit in Ampere changes, but should result in reset sequences a lot closer to RM's, and perhaps help out with the issues we sometimes see reported in this area. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/sec2: switch to newer style interrupt handlerBen Skeggs4-13/+26
Ampere. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/sec2: unload RTOS before tearing down WPRBen Skeggs11-51/+91
Reset regs won't be available on Ampere while SEC2 RTOS is running, and we're apparently supposed to be doing this on earlier GPUs too. v2: - fixed some excessive indentation Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/pmu/gm20b,gp10b: boot RTOS from PMU initBen Skeggs9-60/+92
Cleanup before falcon changes. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/pmu: move init() falcon reset to non-nvfw codeBen Skeggs8-70/+27
Cleanup before falcon changes. - fixes (attempt at?) reset of pmu while rtos is running, on gm20b v2: - remove extra whitespace Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2022-11-09drm/nouveau/pmu: move preinit() falcon reset to devinitBen Skeggs2-13/+7
Cleanup before falcon changes. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
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