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2015-09-10drm/i915: Remove one very outdated commentTvrtko Ursulin1-4/+0
Comment disagrees with the code which has changed a lot since it was documented. Note that the logic to remove -EIO handling was dropped in commit 1488fc08c1706288616c602416654fd38c773deb Author: Chris Wilson <[email protected]> Date: Tue Apr 24 15:47:31 2012 +0100 drm/i915: Remove the deferred-free list Signed-off-by: Tvrtko Ursulin <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-10drm/i915: Use crtc->state for duplication.Maarten Lankhorst1-9/+1
In async mode crtc->config can be updated after the locks are released, resulting in the wrong state being duplicated. Note that this also removes a spurious assignment of crtc_state->crtc introduced in commit f0c60574eb1216b0904c0d696c64d5096d6e4913 Author: Ander Conselvan de Oliveira <[email protected]> Date: Tue Apr 21 17:12:58 2015 +0300 drm/i915: Call drm helpers when duplicating crtc and plane states Signed-off-by: Maarten Lankhorst <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-10drm/i915: Do not handle a null plane state.Maarten Lankhorst1-5/+1
With the conversion to atomic this cannot happen any more. Signed-off-by: Maarten Lankhorst <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-10drm/i915: Remove legacy plane updates for cursor and sprite planes.Maarten Lankhorst2-6/+0
Unfortunately fbc still depends on legacy primary state, so it can't be killed off completely yet. Signed-off-by: Maarten Lankhorst <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-10drm/i915: Use atomic state when changing cursor visibility.Maarten Lankhorst1-6/+7
Signed-off-by: Maarten Lankhorst <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-10drm/i915: Use the atomic state in intel_update_primary_planes.Maarten Lankhorst1-14/+13
This function was still using the legacy state, convert it to atomic. While we're at it, fix the FIXME too and disable the primary plane. v2 (Daniel): - Add FIXME explaining that update_primary_planes should soon get removed anyway. - Don't call ->disable_plane since we can't disable the primary plane with a CS flip (noticed by Ville). Signed-off-by: Maarten Lankhorst <[email protected]> (v1) Signed-off-by: Daniel Vetter <[email protected]>
2015-09-10drm/i915: Use the plane state in intel_crtc_info.Maarten Lankhorst1-3/+5
Legacy state might not be updated any more. Signed-off-by: Maarten Lankhorst <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-10drm/i915: Use atomic plane state in the primary plane update.Maarten Lankhorst1-1/+3
Signed-off-by: Maarten Lankhorst <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-10drm/i915: add attached connector to hdmi containerShashank Sharma2-0/+2
This patch adds the intel_connector initialized to intel_hdmi display, during the init phase, just like the other encoders do. This attachment is very useful when we need to extract the connector pointer during the hotplug handler function Signed-off-by: Shashank Sharma <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-07drm/i915: don't hard code vlv backlight frequency if unsetJani Nikula1-13/+0
Fall back to VBT based backlight modulation frequency if it's not set. Do not hard code. This could be a problem if there is no VBT. Cc: Clint Taylor <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Tested-by: Clint Taylor <[email protected]> Reviewed-by: Clint Taylor <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-07drm/i915: initialize backlight max from VBTJani Nikula3-7/+185
Normally we determine the backlight PWM modulation frequency (which we also use as backlight max value) from the backlight registers at module load time, expecting the registers have been initialized by the BIOS. If this is not the case, we fail. The VBT contains the backlight modulation frequency in Hz. Add platform specific functions to convert the frequency in Hz to backlight PWM modulation frequency, and use them to initialize the backlight when the registers are not initialized by the BIOS. v2: Fix SPT and VLV. Thanks to Clint for the VLV code. Cc: Clint Taylor <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Clint Taylor <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-07drm/i915: use pch backlight override on hsw tooJani Nikula1-11/+23
Currently the difference between backlight control on HSW vs. BDW/SKL is that on HSW we modify the duty cycle on the CPU register, and have the hardware pass the changes on to the PCH registers. We still drive the PCH PWM on both. While HSW and BDW use the same LPT PCH, BDW does not pass these messages on to the PCH. Therefore on BDW we need to enable the PCH override bit, and program the PCH directly. (On SPT PCH, this mode is the default.) We could as well do this on HSW too, and in fact I've been told this is what a certain other operating system does. So use PCH backlight override on HSW too. This simplifies some follow-up code, but it does have the danger of breaking backlight on HSW machines. It should work, but mysterious are the ways of backlight. While at it, name the related backlight hooks according to the PCH rather than the CPU for clarity. Cc: Clint Taylor <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Clint Taylor <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-07drm/i915/bxt: Clean up bxt_init_clock_gatingNick Hoath1-5/+11
Add stepping check for A0 workarounds, and remove the associated FIXME tags. Split out unrelated WAs for later condition checking. v2: Fixed format (PeterL) v3: Corrected stepping check for WaDisableSDEUnitClockGating - Ignoring comment, following hardware spec instead. (ChrisH) Added description for TILECTL setting (JonB) Cc: Peter Lawthers <[email protected]> Cc: Chris Harris <[email protected]> Cc: Jon Bloomfield <[email protected]> Signed-off-by: Nick Hoath <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-04drm/i915: Fix cmdparser STORE/LOAD command descriptorsChris Wilson1-2/+2
Fixes regression from commit f1afe24f0e736b9d7f2275e2b1504af3fe612f2a Author: Arun Siluvery <[email protected]> Date: Tue Aug 4 16:22:20 2015 +0100 drm/i915: Change SRM, LRM instructions to use correct length which forgot to account for the length bias when declaring the fixed length. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91844 Reported-by: Andreas Reis <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Cc: Dave Gordon <[email protected]> Cc: Arun Siluvery <[email protected]> Cc: Mika Kuoppala <[email protected]> Cc: Daniel Vetter <[email protected]> Reviewed-by: Arun Siluvery <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-04drm/i915: Dump pfit state as hexVille Syrjälä1-4/+4
The pfit state is stored as register values, so dump them as hex instead of decimal to make some sense of the error messages. Signed-off-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-04drm/i915: access the PP_ON_DELAYS/PP_OFF_DELAYS regs only pre GEN5Imre Deak4-21/+12
These registers exist only before GEN5, so currently we may access undefined registers on VLV/CHV and BXT. Apply the workaround only pre GEN5. Since the workaround is relevant only when LVDS is present, for clarity apply it only if this is the case. This triggered an unclaimed register access warning on BXT. v2: (Ville) - move the workaround to the LVDS init code - print a debug note about the workaround Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-04drm/i915: access the PP_CONTROL reg only pre GEN5Imre Deak1-1/+1
This register exists only pre GEN5, but atm we also access it on VLV/BXT/CHV. Prevent accessing it on these latter platforms. Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-04drm/i915: Refactor common ringbuffer allocation codeChris Wilson3-76/+70
A small, very small, step to sharing the duplicate code between execlists and legacy submission engines, starting with the ringbuffer allocation code. Signed-off-by: Chris Wilson <[email protected]> Cc: Arun Siluvery <[email protected]> Cc: Mika Kuoppala <[email protected]> Cc: Dave Gordon <[email protected]> Reviewed-by: Paulo Zanoni <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-04drm/i915: use the yesno helper for loggingJani Nikula3-14/+11
Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-04drm/i915: ignore link rate in TPS3 selectionJani Nikula1-3/+4
TPS3 is mandatory for downstream devices that support HBR2, and Intel platforms that support HBR2 also support TPS3. Whenever TPS3 is supported by both the source and sink, it should be used. In other words, whenever the source and sink are capable of 5.4 Gbps link, we should anyway go for TPS3, regardless of the link rate being selected. Log an error if the sink has advertized HBR2 capability without TPS3 capability. Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-04drm/i915/dp: move TPS3 logic to where it's usedJani Nikula2-15/+17
There is no need to have a separate flag for tps3 as the information is only used at one location. Move the logic there to make it easier to follow. Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-04drm/i915: Future proof panel fitter.Rodrigo Vivi1-12/+6
This is another case where we can consider the default is the newest available and not actually a missed case. No functional change. Signed-off-by: Rodrigo Vivi <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-04drm/i915: Future proof uncore_init.Rodrigo Vivi1-2/+0
Unless future specs tells otherwise we can assume future gens inherit some stuff from the previous so let's handle missed cases when we know tehy should't be there and assume default equals newest one. No functional changes. v2: Remove useless case as pointed out by Ville. Cc: Ville Syrjälä <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-04drm/i915: Future proof interrupt handler.Rodrigo Vivi1-4/+4
These functions are already being called for gen >= 9, so let's be sure when this happens we use whatever is there already for the latest platform. No functional change. Signed-off-by: Rodrigo Vivi <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-04drm/i915/gtt: Avoid calling kcalloc in a loop when allocating temp bitmapsMichał Winiarski1-31/+18
On each call to gen8_alloc_va_range_3lvl we're allocating temporary bitmaps needed for error handling. Unfortunately, when we increase address space size (48b ppgtt) we do additional (512 - 4) calls to kcalloc, increasing latency between exec and actual start of execution on the GPU. Let's just do a single kcalloc, we can also drop the size from free_gen8_temp_bitmaps since it's no longer used. v2: Use GFP_TEMPORARY to make the allocations reclaimable. v3: Drop the 2D array, just allocate a single block. v4: Rebase to handle gen8_preallocate_top_level_pdps. v5: Align misaligned bracket. Cc: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Cc: Michel Thierry <[email protected]> Signed-off-by: Michał Winiarski <[email protected]> Reviewed-by: Chris Wilson <[email protected]> [danvet: Correct kcalloc arguments as suggested by Chris.] Signed-off-by: Daniel Vetter <[email protected]>
2015-09-04drm/i915/skl+: Add YUV pixel format in Capability listKumar, Mahesh1-0/+4
GEN >= 9 supports YUV format for all planes, but it's not exported in Capability list of primary plane. Add YUV formats in skl_primary_formats list. Testcase: igt/kms_universal_plane.c Signed-off-by: Kumar, Mahesh <[email protected]> Cc: Konduru, Chandra <[email protected]> Reviewed-by: Sonika Jindal <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-04drm/i915/skl: Avoid using un-initialized bits_per_pixelKumar, Mahesh1-1/+2
Don't rely on fb->bits_per_pixel as intel_framebuffer_init is not filling bits_per_pixel field of fb-struct for YUV pixel format. This leads to divide by zero error during watermark calculation. Signed-off-by: Kumar, Mahesh <[email protected]> Cc: Konduru, Chandra <[email protected]> Reviewed-by: Sonika Jindal <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-02drm/i915: Don't call intel_get_hpd_pins() when there's no hotplug interruptVille Syrjälä1-8/+14
On GMCH plaforms we are now getting the following spew on aux interrupts: [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000000, dig 0x00000000, pins 0x00000000 [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000000, dig 0x00000000, pins 0x00000000 [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000000, dig 0x00000000, pins 0x00000000 [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000000, dig 0x00000000, pins 0x00000000 [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000000, dig 0x00000000, pins 0x00000000 [drm:intel_dp_aux_ch] dp_aux_ch timeout status 0x71450064 Prevent it by not calling intel_get_hpd_pins() unless one of the HPD interrupt bits are actually set. I already fixed similar annoyance once with 4bca26d0a6518d51a9abe64fbde4b12f04c74053 drm/i915: Use HOTPLUG_INT_STATUS_G4X on VLV/CHV but another source for it got added in fd63e2a972c670887e5e8a08440111d3812c0996 drm/i915: combine i9xx_get_hpd_pins and pch_get_hpd_pins due to pch_get_hpd_pins() being chosen over i9xx_get_hpd_pins() to serve as the new unified piece of code. pch_get_hpd_pins() had the debug print, and i9xx_get_hpd_pins() didn't. Cc: Imre Deak <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-02drm/i915: Rewrite BXT HPD code to conform to pre-existing styleVille Syrjälä2-38/+13
Rewrite the BXT hpd setup to match the way we do it on other platforms: - Throw out BXT_HOTPLUG_CTL since it's the same as PCH_PORT_HOTPLUG - Enable the HPD bits in the DE port IER in gen8_de_irq_postinstall() - Update DE port IMR using bdw_update_port_irq() Also throw out port D from bxt_port_hotplug_long_detect() since BXT only goes up to C. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-02drm/i915: Refactor the hpd irq handling functionsVille Syrjälä1-63/+49
A lot of the hpd irq handling is duplicated code, so refactor it a bit by observing that in several places the only difference is the hpd[] array. So pull the code to a few functions and pass in the hpd[] array from the caller. Another option would be to determine the correct array to use within the functions themselves, but somehow passing it in felt nicer. Further code reduction could be achieved by passing in the hotplug register offset, and the long pulse detection function pointer. But that didn't feel as good for some reason, so I left it at the middle ground. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-02drm/i915: Rewrite bxt_hpd_handler() to look like everyone elseVille Syrjälä1-21/+16
bxt_hpd_handler() looks different to everyone else for no good reason. Rewrite it to use the standard variable namees etc. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-02drm/i915: Reinitialize HPD after runtime D3Ville Syrjälä1-0/+9
Runtime suspends disabled all interrupts, so in order to get them back fully we need to also do the HPD irq setup on runtime resume. Except on VLV/CHV where the display interrupt initialization is part of the display power well powerup. Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-02drm/i915: Add port A HPD support for SPTVille Syrjälä2-3/+22
On SKL the port A HPD has moved to the PCH. Hook it up. Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-02drm/i915: Add port A HPD support for BDWVille Syrjälä1-12/+74
Wire up the port A HPD for BDW. Compared to earlier platforms the interrupt setup is a bit different, but basically everything else looks the same. v2: 0 initialize pin_mask/long_mask due to intel_get_hpd_pins() changes Check for BDW before processing the HPD to not break BXT Set found=true when processing port A HPD Sort out the mess I made of the irq setup in v1 Warn about bad irq mask vs. enable bits in bdw_update_port_irq() (Paulo) Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-02drm/i915: LPT:LP needs port A HPD enabled in both north and southVille Syrjälä1-0/+6
If the CPU and PCH are on the same package we must enabled the port A HPD also in the south hotplug register. To identify the package type we simply look at the PCH type: LPT-H means separate package, and LPT-LP means multi chip package (MCP). v2: Add comment and pimp commit message Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-02drm/i915: Add port A HPD support for IVB/HSWVille Syrjälä1-7/+28
As with ILK/SNB wire up the port A HPD on IVB/HSW. This might be more important on HSW with PSR. BSpec tells us that if the automagic link training performed by the hardware fails for some reason, we're going to get a short HPD and are supposed to re-train the link manyally. v2: 0 initialize pin_mask/long_mask due to intel_get_hpd_pins() changes Add a comment about the pulse duration bits being reserved on HSW+ like we have for LPT+ in ibx_hpd_irq_setup() Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-02drm/i915: Add port A HPD support for ILK/SNBVille Syrjälä1-3/+56
ILK/SNB support port A HPD. While HPD is optional on eDP let's at least try to wite it up so that we might notice if the link has issues. The eDP spec suggests that if HPD is not wired up, one should poll the link status instead. We don't even do that currently. v2: 0 initialize pin_mask/long_mask due to intel_get_hpd_pins() changes Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-02drm/i915: Introduce spt_irq_handler()Ville Syrjälä1-40/+84
Starting from SPT the only interrupts living in the south are GMBUS and HPD. What's worse some of the SPT specific new bits conflict with some other bits on earlier PCH generations. So better not use the cpt_irq_handler() for SPT+ anymore. Also kill the hand rolled port E handling with something more standardish. This also avoids accidentally confusing port B and port E long pulses since the bits occupy the same positions, just in different registers. Also add a comment noting that the short pulse duration bits are reserved on LPT+. The 2ms value we program is 0, so no issue wrt. the MBZ in the spec. v2: Call intel_hpd_irq_handler() only once (Paulo) Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-02drm/i915: Move {pin, long}_mask initialization to caller from ↵Ville Syrjälä1-8/+11
intel_get_hpd_pins() Move the 0 initialization of pin_mask and long_mask from intel_get_hpd_pins() into each caller. This we we can call intel_get_hpd_pins() multiple times to accumulate more pins from several sources. v2: Add a comment explaining the dangers of intel_get_hpd_pins() (Paulo) Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-02drm/i915: Rename BXT PORTA HPD definesVille Syrjälä2-6/+6
The PORTA HPD defines are not BXT specific. They also exist on SPT, and partially already on LPT:LP. Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-02drm/i915: Add HAS_PCH_LPT_LP() macroVille Syrjälä3-10/+8
Make LPT:LP checks look neater by wrapping the details in a new HAS_PCH_LPT_LP() macro. Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-02drm/i915: Factor out ilk_update_display_irq()Ville Syrjälä1-15/+26
Extract the core of ironlake_{enable,disable}_display_irq() into a new function. We'll have further use for it later. v2: Warn about invalid mask vs. enable bits (Paulo) Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-02drm/i915: Extract intel_hpd_enabled_irqs()Ville Syrjälä1-22/+21
Eliminate a bunch of duplicated code that calculates the currently enabled HPD interrupt bits. v2: s/;/:/ in patch subject (Paulo) Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-02drm/i915: Clean up various HPD definesVille Syrjälä1-36/+38
Indent the PORTx_HOTPLUG_... defines appropriately, and fix some space vs. tab issues. v2: Document pre-HSW/LPT bits, and order another tab (Paulo) Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-02drm/i915: Update comments around base bppDaniel Vetter1-5/+1
Forgot to do that in commit d328c9d78d64ca11e744fe227096990430a88477 Author: Daniel Vetter <[email protected]> Date: Fri Apr 10 16:22:37 2015 +0200 drm/i915: Select starting pipe bpp irrespective or the primary plane and it's confusing. Fix it. Cc: Jesse Barnes <[email protected]> Acked-by: Jesse Barnes <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-02Merge tag 'drm-intel-next-fixes-2015-09-02' into drm-intel-next-queuedDaniel Vetter627-17090/+48154
Backmerge -fixes since there's more DDI-E related cleanups on top of the pile of -fixes for skl that just landed for 4.3. Conflicts: drivers/gpu/drm/i915/intel_display.c drivers/gpu/drm/i914/intel_dp.c drivers/gpu/drm/i915/intel_lrc.c Conflicts are all fairly harmless adjacent line stuff. Signed-off-by: Daniel Vetter <[email protected]>
2015-09-02drm/i915: Also record time difference if vblank evasion fails, v2.Maarten Lankhorst2-2/+7
This makes the error message slightly more useful. Changes since v1: - Use ktime_get() while irqs are still disabled. (vsyrjala) Signed-off-by: Maarten Lankhorst <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-02drm/i915: Remove start frame argument to pipe_update_begin/end.Maarten Lankhorst3-15/+14
There's already a per crtc member that can be used for it. Signed-off-by: Maarten Lankhorst <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-02drm/i915: guest i915 notification for Intel GVT-gZhiyuan Lv1-0/+41
When i915 drivers run inside a VM with Intel GVT-g, some explicit notifications are needed from guest to host device model through PV INFO page write. The notifications include: PPGTT create PPGTT destroy They are used for the shadow implementation of PPGTT. Intel GVT-g needs to write-protect the guest pages of PPGTT, and clear the write protection when they end their life cycle. v2: - Use lower_32_bits()/upper_32_bits() for qword operations; - Remove the notification of guest context creation/destroy; Signed-off-by: Zhiyuan Lv <[email protected]> Signed-off-by: Zhi Wang <[email protected]> Reviewed-by: Joonas Lahtinen <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2015-09-02drm/i915: Update PV INFO page definition for Intel GVT-gZhiyuan Lv1-2/+32
Some more definitions in the PV info page are added. They are mainly for the guest notification to Intel GVT-g device model. They are used for Broadwell enabling. The notification of PPGTT page table creation/destroy is to notify GVT-g device model the life cycle of guest page tables. Then device model will implement shadow page table for guests. The notification of context create/destroy is optional. If it is used, the device model will create/destroy shadow context corresponding to the context's life cycle. Guest driver needs to make sure that the context's LRCA and backing storage address unchanged. If it is not used, the device model will perform the context shadow work in the context scheduling time. Signed-off-by: Zhiyuan Lv <[email protected]> Signed-off-by: Zhi Wang <[email protected]> Reviewed-by: Joonas Lahtinen <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
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