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git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas
Pull Renesas clk driver updates from Geert Uytterhoeven
- Add PCIe, PWM, and CAN-FD clocks on R-Car V4M
- Add LCD controller clocks and resets on RZ/G2UL
- Add DMA clocks and resets on RZ/G3S
- Add fractional multiplication PLL support on R-Car Gen4
- Document support for the Renesas RZ/G2M v3.0 (r8a774a3) SoC
- Add support for the RZ/V2H(P) (R9A09G057) SoC
- Miscellaneous fixes and improvements
* tag 'renesas-clk-for-v6.12-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: (30 commits)
clk: renesas: r8a779h0: Add CANFD clock
clk: renesas: Add RZ/V2H(P) CPG driver
clk: renesas: Add family-specific clock driver for RZ/V2H(P)
dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG
clk: renesas: r8a779h0: Add PWM clock
dt-bindings: clock: renesas,cpg-mssr: Document RZ/G2M v3.0 (r8a774a3) clock
clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configs
clk: renesas: rcar-gen4: Remove unused fixed PLL clock types
clk: renesas: rcar-gen4: Remove unused variable PLL2 clock type
clk: renesas: r8a779h0: Model PLL1/2/3/4/6 as fractional PLLs
clk: renesas: r8a779g0: Model PLL1/3/4/6 as fractional PLLs
clk: renesas: r8a779f0: Model PLL1/2/3/6 as fractional PLLs
clk: renesas: r8a779a0: Use defines for PLL control registers
clk: renesas: rcar-gen4: Add support for fractional 9.24 PLLs
clk: renesas: rcar-gen4: Add support for fixed variable PLLs
clk: renesas: rcar-gen4: Add support for variable fractional PLLs
clk: renesas: rcar-gen4: Add support for fractional multiplication
clk: renesas: rcar-gen4: Use defines for common CPG registers
clk: renesas: rcar-gen4: Use FIELD_GET()
clk: renesas: rcar-gen4: Clarify custom PLL clock support
...
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The maximum number of PLL components on SAMA7G5 is 3 (one fractional
part and 2 dividers). Allocate the needed amount of memory for
sama7g5_plls 2d array. Previous code used to allocate 7 array entries for
each PLL. While at it, replace 3 with PLL_COMPID_MAX in the loop which
parses the sama7g5_plls 2d array.
Fixes: cb783bbbcf54 ("clk: at91: sama7g5: add clock support for sama7g5")
Acked-by: Stephen Boyd <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Claudiu Beznea <[email protected]>
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Properties with variable number of items per each device are expected to
have widest constraints in top-level "properties:" block and further
customized (narrowed) in "if:then:". Add missing top-level constraints
for clocks and clock-output-names.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
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This adds support for CMU_TOP which generates clocks for all the
function blocks such as CORE, HSI0/1/2, PERIC0/1 and so on. For
CMU_TOP, PLL_SHARED0,1,2,3,4 and 5 will be the sources of this block
and they will generate bus clocks.
Signed-off-by: Sunyeal Hong <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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pll531x PLL is used in Exynos Auto v920 SoC for shared pll.
pll531x: Integer/fractional PLL with mid frequency FVCO (800 to 3120 MHz)
PLL531x
FOUT = (MDIV x FIN)/(PDIV x 2^SDIV) for integer PLL
FOUT = (MDIV + F/2^32-F[31]) x FIN/(PDIV x 2^SDIV) for fractional PLL
Signed-off-by: Sunyeal Hong <[email protected]>
Reviewed-by: Alim Akhtar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Add dt-schema for ExynosAuto v920 SoC clock controller.
Add device tree clock binding definitions for below CMU blocks.
- CMU_TOP
- CMU_PERIC0/1
- CMU_MISC
- CMU_HSI0/1
Signed-off-by: Sunyeal Hong <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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Exynos7885 SoC has a DWC3 USB Controller with Exynos USB PHY which in
theory supports USB3 SuperSpeed, but is only used as USB2 in all known
devices.
These clocks are needed for everything related to USB.
While at it, also remove the CLK_SET_RATE_PARENT capability of
CLK_MOUT_FSYS_USB30DRD_USER, since it's not actually needed.
Signed-off-by: David Virag <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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pll1418x is used in Exynos7885 SoC for USB PHY clock.
Operation-wise it is very similar to pll0822x, except that MDIV is only
9 bits wide instead of 10, and we use the CON1 register in the PLL
macro's "con" parameter instead of CON3 like this:
PLL(pll_1418x, CLK_FOUT_USB_PLL, "fout_usb_pll", "oscclk",
PLL_LOCKTIME_PLL_USB, PLL_CON0_PLL_USB,
pll_usb_rate_table),
Technically the PLL should work fine with pll0822x code if the PLL
tables are correct, but it's more "correct" to actually update the mask.
Signed-off-by: David Virag <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
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The video driver will be using the newly introduced
dev_pm_genpd_set_hwmode() API to switch the video GDSC
to HW/SW control modes at runtime.
Hence use HW_CTRL_TRIGGER flag instead of HW_CTRL for
video GDSC's.
Signed-off-by: Vedang Nagar <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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Add the CANFD module clock on the Renesas R-Car V4M (R8A779H0) SoC.
Signed-off-by: Cong Dang <[email protected]>
Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/9bf71bfda338ee5411751174b03b9e870cc818e3.1722519424.git.geert+renesas@glider.be
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Add RZ/V2H(P) CPG driver.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
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i.MX95 System Management Control Firmware(SCMI) manages the clock
function, it exposes PLL VCO which could support up to 5GHz rate that
exceeds UINT32_MAX. So add assigned-clock-rates-u64 support
to set rate that exceeds UINT32_MAX.
Signed-off-by: Peng Fan <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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According to msm-5.10 the lucid 5lpe PLLs have require slightly
different configuration that trion / lucid PLLs, it doesn't set
PLL_UPDATE_BYPASS bit. Add corresponding function and use it for the
display clock controller on Qualcomm SM8350 platform.
Fixes: 205737fe3345 ("clk: qcom: add support for SM8350 DISPCC")
Signed-off-by: Dmitry Baryshkov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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Add CLK_SET_RATE_PARENT for several branch clocks. Such clocks don't
have a way to change the rate, so set the parent rate instead.
Fixes: 80a18f4a8567 ("clk: qcom: Add display clock controller driver for SM8150 and SM8250")
Cc: [email protected]
Signed-off-by: Dmitry Baryshkov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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Use the icc-clk framework to enable few clocks to be able to
create paths and use the peripherals connected on those NoCs.
Remove CLK_IGNORE_UNUSED from gpll4_main as all consumers have
been identified.
Reviewed-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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gcc_qdss_tsctr_clk_src (enabled in the boot loaders and dependent
on gpll4_main) was not registered as one of the ipq5332 clocks.
Hence clk_disable_unused() disabled 'gpll4_main' assuming there
were no consumers for 'gpll4_main' resulting in system freeze or
reboots.
Reviewed-by: Dmitry Baryshkov <[email protected]>
Fixes: 3d89d52970fd ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC")
Signed-off-by: Varadarajan Narayanan <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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Unlike MSM SoC, IPQ SoC doesn't use RPM to aggregate bandwidth
requests and scale the NoC frequency. The NoCs are turned on and
set to a specific frequency at boot time and that is used for the
lifetime of the system. Hence interconnect was not considered
previously.
The same approach was used for PCIe and at that point the
consensus was to move to interconnect. Hence implemented the ICC
driver and updating the existing USB driver to use the ICC
driver.
USB uses icc-clk framework to enable the NoC interface clock.
Hence the 'iface' clock is removed from the list of clocks.
Update the clock-names list accordingly.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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clk-for-6.12
Merge IPQ5332 interconnect binding additions through topic branchs to
allow making the constants available in DeviceTree branch as well.
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Add interconnect-cells to clock provider so that it can be
used as icc provider.
Add master/slave ids for Qualcomm IPQ5332 Network-On-Chip
interfaces. This will be used by the gcc-ipq5332 driver
for providing interconnect services using the icc-clk
framework.
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Varadarajan Narayanan <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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Add the Q6 BIMC, LPASS core/adsp SMMU clocks to support audio related
functionality on MSM8998 and APQ variants.
As a final step to entirely enable the required clock tree for the
lpass iommu and audio dsp, add the lpass core/adsp GDSCs.
As a side note, it was found out that disabling the lpass core GDSC
at any time would cause a system lockup (and reboot): disabling
this GDSC will leave the lpass iommu completely unclocked, losing
its state entirely - including the secure contexts that have been
previously set-up from the bootloader/TrustZone.
Losing this IOMMU configuration will trigger a hypervisor fault,
which will reboot the system; the only workaround for this issue
is to declare the lpass core gdsc as always-on.
It should also not be forgotten that this is all about firmware and
there may be a version of it that doesn't enable this GDSC at all
before booting Linux, which is the reason why this specific declaration
wasn't simply omitted.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Signed-off-by: Marc Gonzalez <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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Merge updates to MSM8998 GCC binding include file through topic branch,
to make available the newly added constants to both clock and DeviceTree
branch.
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Add definitions for the Q6 BIMC, LPASS core and adsp smmu clocks,
required to enable audio functionality on MSM8998.
Add the GDSC definitions for the LPASS_ADSP_GDSC and LPASS_CORE_GDSC
as a final step to enable the required clock tree for the lpass iommu
and for the audio dsp itself.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
Signed-off-by: Marc Gonzalez <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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SM_CAMCC_8150 depends on SM_GCC_8150, which inturn depends on ARM64.
Hence add the dependency to avoid below kernel-bot warning.
WARNING: unmet direct dependencies detected for SM_GCC_8150
Depends on [n]: COMMON_CLK [=y] && COMMON_CLK_QCOM [=y] && (ARM64 || COMPILE_TEST [=n])
Selected by [y]:
- SM_CAMCC_8150 [=y] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=y]
Fixes: ea73b7aceff6 ("clk: qcom: Add camera clock controller driver for SM8150")
Reported-by: kernel test robot <[email protected]>
Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
Signed-off-by: Satya Priya Kakitapalli <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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The branch clocks of gcc_cpuss_ahb_clk_src are marked critical
and hence these clocks vote on XO blocking the suspend.
De-register these clocks and its source as there is no rate
setting happening on them.
Fixes: 4433594bbe5d ("clk: qcom: gcc: Add global clock controller driver for SC8180x")
Cc: [email protected]
Signed-off-by: Satya Priya Kakitapalli <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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Update the frequency tables of gcc_sdcc2_apps_clk and gcc_sdcc4_apps_clk
as per the latest frequency plan.
Fixes: 4433594bbe5d ("clk: qcom: gcc: Add global clock controller driver for SC8180x")
Cc: [email protected]
Signed-off-by: Satya Priya Kakitapalli <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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Add the missing GPLL9 pll and fix the gcc_parents_7 data to use
the correct pll hw.
Fixes: 4433594bbe5d ("clk: qcom: gcc: Add global clock controller driver for SC8180x")
Cc: [email protected]
Reviewed-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Satya Priya Kakitapalli <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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Add the missing GPLL9 which is required for the gcc sdcc2 clock.
Fixes: 0fadcdfdcf57 ("dt-bindings: clock: Add SC8180x GCC binding")
Cc: [email protected]
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Satya Priya Kakitapalli <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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QUPv3 clocks support DFS on sc8180x platform but currently the code
changes for it are missing from the driver, this results in not
populating all the DFS supported frequencies and returns incorrect
frequency when the clients request for them. Hence add the DFS
registration for QUPv3 RCGs.
Fixes: 4433594bbe5d ("clk: qcom: gcc: Add global clock controller driver for SC8180x")
Cc: [email protected]
Signed-off-by: Satya Priya Kakitapalli <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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Valid frequencies may result in BCM votes that exceed the max HW value.
Set vote ceiling to BCM_TCS_CMD_VOTE_MASK to ensure the votes aren't
truncated, which can result in lower frequencies than desired.
Fixes: 04053f4d23a4 ("clk: qcom: clk-rpmh: Add IPA clock support")
Cc: [email protected]
Signed-off-by: Mike Tipton <[email protected]>
Reviewed-by: Taniya Das <[email protected]>
Signed-off-by: Imran Shaik <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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On SM8650, the minimum voltage corner supported on MMCX from cmd-db is
sufficient for clock controllers to operate and there is no need to specify
the required-opps. Hence remove the required-opps property from the list of
required properties for SM8650 camcc bindings.
This fixes:
arch/arm64/boot/dts/qcom/sm8650-hdk.dtb: clock-controller@ade0000:
'required-opps' is a required property
arch/arm64/boot/dts/qcom/sm8650-mtp.dtb: clock-controller@ade0000:
'required-opps' is a required property
arch/arm64/boot/dts/qcom/sm8650-qrd.dtb: clock-controller@ade0000:
'required-opps' is a required property
Fixes: 1ae3f0578e0e ("dt-bindings: clock: qcom: Add SM8650 camera clock controller")
Reported-by: Vladimir Zapolskiy <[email protected]>
Closes: https://lore.kernel.org/all/[email protected]/
Reported-by: kernel test robot <[email protected]>
Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
Signed-off-by: Jagadeesh Kona <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Vladimir Zapolskiy <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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On SM8650, the minimum voltage corner supported on MMCX from cmd-db is
sufficient for clock controllers to operate and there is no need to specify
the required-opps. Hence remove the required-opps property from the list of
required properties for SM8650 videocc bindings.
This fixes:
arch/arm64/boot/dts/qcom/sm8650-hdk.dtb: clock-controller@aaf0000:
'required-opps' is a required property
arch/arm64/boot/dts/qcom/sm8650-mtp.dtb: clock-controller@aaf0000:
'required-opps' is a required property
arch/arm64/boot/dts/qcom/sm8650-qrd.dtb: clock-controller@aaf0000:
'required-opps' is a required property
Fixes: a6a61b9701d1 ("dt-bindings: clock: qcom: Add SM8650 video clock controller")
Reported-by: Vladimir Zapolskiy <[email protected]>
Closes: https://lore.kernel.org/all/[email protected]/
Reported-by: kernel test robot <[email protected]>
Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
Signed-off-by: Jagadeesh Kona <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Vladimir Zapolskiy <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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Convert the bindings for the Turing Clock Controller on QCS404 from
the old text format to yaml.
Signed-off-by: Rayyan Ansari <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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X1E80100 LPASS (Low Power Audio Subsystem) clock controller provides reset
support when it is under the control of Q6DSP.
Add x1e80100 compatible to the existing sc8280xp as these reset
controllers have same reg layout and compatible.
Signed-off-by: Srinivas Kandagatla <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Acked-by: Dmitry Baryshkov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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X1E80100 LPASS (Low Power Audio Subsystem) Audio clock controller
provides reset support when it is under the control of Q6DSP.
Add x1e80100 compatible to the existing sc8280xp as these reset
controllers have same reg layout and compatible.
Signed-off-by: Srinivas Kandagatla <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Acked-by: Dmitry Baryshkov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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The MSM8226 has one PLL for its Cortex-A7 cores. The frequencies will be
specified in devicetree.
Signed-off-by: Luca Weiss <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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Add the compatible for the A7PLL found in MSM8226 SoCs.
Signed-off-by: Luca Weiss <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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Allow placing an opp-table as a subnode that can be assigned using
operating-points-v2 to specify the frequency table for the PLL.
Signed-off-by: Luca Weiss <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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Add Graphics Clock Controller (GPUCC) support for SM4450 platform.
Signed-off-by: Ajit Pandey <[email protected]>
Reviewed-by: Konrad Dybcio <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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Add Camera Clock Controller (CAMCC) support for SM4450 platform.
Signed-off-by: Ajit Pandey <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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Add Display Clock Controller (DISPCC) support for SM4450 platform.
Signed-off-by: Ajit Pandey <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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In LUCID EVO PLL CAL_L_VAL and L_VAL bitfields are part of single
PLL_L_VAL register. Update for L_VAL bitfield values in PLL_L_VAL
register using regmap_write() API in __alpha_pll_trion_set_rate
callback will override LUCID EVO PLL initial configuration related
to PLL_CAL_L_VAL bit fields in PLL_L_VAL register.
Observed random PLL lock failures during PLL enable due to such
override in PLL calibration value. Use regmap_update_bits() with
L_VAL bitfield mask instead of regmap_write() API to update only
PLL_L_VAL bitfields in __alpha_pll_trion_set_rate callback.
Fixes: 260e36606a03 ("clk: qcom: clk-alpha-pll: add Lucid EVO PLL configuration interfaces")
Cc: [email protected]
Signed-off-by: Ajit Pandey <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
Acked-by: Vladimir Zapolskiy <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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clk-for-6.12
Merge the SM4450 display, camera and GPU bindings through a topic
branch, to make it possible to merge them into the DeviceTree source
branch as well.
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Add device tree bindings for the graphics clock controller on
Qualcomm SM4450 platform.
Signed-off-by: Ajit Pandey <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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Add device tree bindings for the camera clock controller on
Qualcomm SM4450 platform.
Signed-off-by: Ajit Pandey <[email protected]>
Reviewed-by: Rob Herring (Arm) <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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Add device tree bindings for the display clock controller on
Qualcomm SM4450 platform.
Signed-off-by: Ajit Pandey <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
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Let the kmemdup_array() take care about multiplication and possible
overflows.
Signed-off-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Let the kmemdup_array() take care about multiplication and possible
overflows.
Signed-off-by: Andy Shevchenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Convert the various MediaTek syscon bindings which are a clock provider
into DT schema format. As they are all the same other than compatible
string, combine them into a single schema file.
Signed-off-by: Rob Herring (Arm) <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Conor Dooley <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The "arm" binding directory is for architecture specific and top-level
board bindings. Move all the MediaTek bindings implementing clock
providers from "arm/mediatek/" to "clock/" binding directories.
Signed-off-by: Rob Herring (Arm) <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Acked-by: Conor Dooley <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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