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They are 64bit not 32 for a while now.
Signed-off-by: Christian König <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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We don't need to use the PCI BAR on APUs. This allows us to access
the full VRAM directly without being limited by the BAR size.
v2: squash in 64bit shift fix
Signed-off-by: Christian König <[email protected]>
Reviewed-by: Michel Dänzer <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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We don't need to use the PCI BAR on APUs. This allows us to access
the full VRAM directly without being limited by the BAR size.
v2: squash in 64bit shift fix
Signed-off-by: Christian König <[email protected]>
Reviewed-by: Michel Dänzer <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Return early if it's disabled.
Signed-off-by: Rex Zhu <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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1. current_ps/request_ps not update.
2. compare crrent_ps and request_ps, if same,
don't re-set power state.
Signed-off-by: Rex Zhu <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Signed-off-by: Rex Zhu <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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The vfct table can contain multiple vbios images if the
platform contains multiple GPUs. Noticed by netkas on
phoronix forums. This patch fixes those platforms.
Signed-off-by: Alex Deucher <[email protected]>
Cc: [email protected]
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The vfct table can contain multiple vbios images if the
platform contains multiple GPUs. Noticed by netkas on
phoronix forums. This patch fixes those platforms.
Signed-off-by: Alex Deucher <[email protected]>
Cc: [email protected]
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Move these to the amdgpu directory to match what we
do for other asics.
Acked-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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All of these are available elsewhere.
Acked-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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No longer necessary with the new 58 mc ucode.
bug:
https://bugs.freedesktop.org/show_bug.cgi?id=76490
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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No longer necessary with the new 58 mc ucode.
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Here, If ioremap_nocache will fail. It will return NULL.
Kernel can run into a NULL-pointer dereference.
This error check will avoid NULL pointer dereference.
Signed-off-by: Arvind Yadav <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Here, If ioremap_nocache will fail. It will return NULL.
Kernel can run into a NULL-pointer dereference.
This error check will avoid NULL pointer dereference.
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Arvind Yadav <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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In the case of pass-through, amdgpu.ko may be included into a image
with the hard code ID therefore loading driver with specified virtual
display ID will lose efficacy when the BDF of GPU modifies.So add the
new ID string "all" for it as same as vf case what does.
Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Yintian Tao <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Signed-off-by: Junwei Zhang <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Add the bo creation changes that have been done to the radeon driver in
recent times, e.g. disable GTT WC on 32 bit because it is broken there,
and also disable it generally (and print a warning message) when
CONFIG_X86_PAT is not set.
v2: agd: fix warning in defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
case
Reviewed-by: Michel Dänzer <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Nils Holland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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In smu7_clockpowergating.h, the #ifndef statement which prevents
multiple inclusions of the header file uses _SMU7_CLOCK_POWER_GATING_H_
but the following #define statement uses _SMU7_CLOCK__POWER_GATING_H_.
Signed-off-by: Nicolas Iooss <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Without the custom LRU management the callback is not used any more.
agd: fix trivial warning
Reviewed-by: Sinclair Yeh <[email protected]>
Signed-off-by: Christian König <[email protected]>
Reviewed-and-Tested-by: Roger.He <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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The additional housekeeping had too much CPU overhead,
let's use the BO priorities instead.
agd: also revert hibmc changes
Reviewed-by: Sinclair Yeh <[email protected]>
Signed-off-by: Christian König <[email protected]>
Reviewed-and-Tested-by: Roger.He <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Give kernel allocations a higher priority cause it is often
more work to swap them back in.
Signed-off-by: Christian König <[email protected]>
Reviewed-by: Roger.He <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Keeping groups of BOs on the LRU is to time consuming on command submission.
Instead use the newly added BO priority to give a certain eviction order.
v2: agd: trivial warning fix
Signed-off-by: Christian König <[email protected]>
Reviewed-by: Roger.He <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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This way the driver can specify a priority for a BO which has the effect that
a BO is only evicted when all other BOs with a lower priority are evicted
first.
Reviewed-by: Sinclair Yeh <[email protected]>
Signed-off-by: Christian König <[email protected]>
Reviewed-by: Roger.He <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Not allowing errors here is completely pointless and actually dangerous
cause trying to continue on an error can cause an endless loop.
Reviewed-by: Sinclair Yeh <[email protected]>
Signed-off-by: Christian König <[email protected]>
Reviewed-by: Roger.He <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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For virt, freed mailbox irq should be handled in hw fini, not hw
init. Correct it.
Signed-off-by: Xiangliang Yu <[email protected]>
Reviewed-by: Monk Liu <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Reboot process will call HW fini functions of IP blocks. For virt,
need to send event three before hw fini and send event four after
hw fini.
Signed-off-by: Xiangliang Yu <[email protected]>
Reviewed-by: Monk Liu <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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So we can determine which device the entry is before connecting
a display.
Signed-off-by: Tom St Denis <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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for non-VM submit which is from kernel side, no need
to switch buffer at all.
Signed-off-by: Monk Liu <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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SR-IOV requires the preamble.
Signed-off-by: Monk Liu <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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no need to set it per ib_schedule(), hw won't override
this polling address.
Signed-off-by: Monk Liu <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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to support SRIOV preemption.
v2:
fix emit_frame_size
Signed-off-by: Monk Liu <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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To determine whether the context uses GPUVM or not.
Signed-off-by: Monk Liu <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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those package need to insert into ring buffer for
SRIOV case. they are used to let CP do preemption.
Signed-off-by: Monk Liu <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Write multiple dwords to the ring.
Signed-off-by: Monk Liu <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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META-DATA is used in GFX cmd submit, we have two
format suit for META-DATA-init, one is legacy and another
is for chained-ib preempt, which is used in vulkan
UMD.
v2: drop use CP version number to judge if chain-ib
supports or not, we wait for it mature
Signed-off-by: Monk Liu <[email protected]>
Acked-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Fix up the powergating logic.
Signed-off-by: Rex Zhu <[email protected]>
Ack-by: Tom St Denis <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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The scratch regs are sequential so there's no need to keep
them in an array, we can just return the index of the first
free register + the base register. Also change the array
of bools for keeping track of the free regs to a bitfield.
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Nils Wallménius <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Make pflip atomic friendly. Split the fuinction into
whatever can fail part and the actual flip submit part.
Call the pre-submit function before atomic states
are swapped so in case of error we can fail the
IOCTL.
v2:
Update due to target_vblank code change.
Fix identetation.
Change return type for amdgpu_crtc_submit_flip to void
v3: agd: fix formatting
Signed-off-by: Andrey Grodzovsky <[email protected]>
Reviewed-by Harry Wentland <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Switching to -ENOMEM resolves a hang in case the driver
uses this function in atomic code path.
v2: Update commit message.
v3:
Remove forcing -EINVAL in case of amdgpu_bo_pin fail
since there is no apparent reason for not just passing
through the the return value.
Signed-off-by: Andrey Grodzovsky <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by Harry Wentland <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Use BUG_ON instead of a if condition followed by BUG.
Generated by: scripts/coccinelle/misc/bugon.cocci
Reviewed-by: Christian König <[email protected]>
Reviewd-by: Xiangliang.Yu <[email protected]>
CC: Xiangliang Yu <[email protected]>
Signed-off-by: Julia Lawall <[email protected]>
Signed-off-by: Fengguang Wu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Difference families may have different numbers of rings. Use
the variable rather than a hardcoded number.
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Unlock the resv lock only if we were the ones to lock it in the first
place.
Signed-off-by: Nicolai Hähnle <[email protected]>
Reviewed-by: Edward O'Callaghan <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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ttm_bo_init checks that the reservation object is locked. This is
the caller's responsibility when resv != NULL. Otherwise, the inline
reservation object of the newly allocated buffer is used and must
explicitly be locked.
Uninterruptible w/w locks without an acquire context are always
successful.
v2: use ww_mutex_lock
Signed-off-by: Nicolai Hähnle <[email protected]>
Reviewed-by: Edward O'Callaghan <[email protected]> (v1)
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Fixes: 9e8590861e9 ('drm/amdgpu: add parse clock gating state')
Reported-by: Tom StDenis <[email protected]>
Signed-off-by: Huang Rui <[email protected]>
Reviewed-by: Tom St Denis <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Current amdgpu reset process only works on bare-metal and for
SRIOV many inside it need re-work to adapt to vf device.
This is a temporary workaround to skip gpu reset.
Signed-off-by: Monk Liu <[email protected]>
Signed-off-by: Xiangliang Yu <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Virtual display is default setting for virtualization, enable it.
Signed-off-by: Xiangliang Yu <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Acked-by: Christian König <[email protected]>
Reviewed-by: Monk Liu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Call VI virtualization functions if device is Vf.
Signed-off-by: Xiangliang Yu <[email protected]>
Signed-off-by: Monk Liu <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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For gpu vf device, first need to request full gpu access before
accessing gpu registers, and release full gpu access after the
access is done.
Signed-off-by: Xiangliang Yu <[email protected]>
Signed-off-by: Monk Liu <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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VI has asic specific virt support, which including mailbox and
golden registers init.
Signed-off-by: Xiangliang Yu <[email protected]>
Signed-off-by: Monk Liu <[email protected]>
Signed-off-by: shaoyunl <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Acked-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Add high level interfaces that is not relate to specific asic. So
asic files just need to implement the interfaces to support
virtualization.
Signed-off-by: Xiangliang Yu <[email protected]>
Signed-off-by: Monk Liu <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Reviewed-by: Christian König <[email protected]>
Reviewed-by: Monk Liu <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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