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2021-02-08dmaengine: dw-axi-dmac: remove redundant null check on descColin Ian King1-4/+0
The pointer desc is being null checked twice, the second null check is redundant because desc has not been re-assigned between the checks. Remove the redundant second null check on desc. Fixes: ef6fb2d6f1ab ("dmaengine: dw-axi-dmac: simplify descriptor management") Signed-off-by: Colin Ian King <[email protected]> Tested-by: Sia Jee Heng <[email protected]> Reviewed-by: Sia Jee Heng <[email protected]> Addresses-Coverity: ("Logically dead code") Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-01dmaengine: xilinx_dma: Alloc tx descriptors GFP_NOWAITRichard Fitzgerald1-1/+1
Use GFP_NOWAIT allocation in xilinx_dma_alloc_tx_descriptor(). This is necessary for compatibility with ALSA, which calls dmaengine_prep_dma_cyclic() from an atomic context. Signed-off-by: Richard Fitzgerald <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-01dmaengine: dw-axi-dmac: Virtually split the linked-listSia Jee Heng2-20/+92
AxiDMA driver exposed the dma_set_max_seg_size() to the DMAENGINE. It shall helps the DMA clients to create size-optimized linked-list for the controller. However, there are certain situations where DMA client might not be abled to benefit from the dma_get_max_seg_size() if the segment size can't meet the nature of the DMA client's operation. In the case of ALSA operation, ALSA application and driver expecting to run in a period of larger than 10ms regardless of the bit depth. With this large period, there is a strong request to split the linked-list in the AxiDMA driver. Signed-off-by: Sia Jee Heng <[email protected]> Tested-by: Eugeniy Paltsev <[email protected]> Reviewed-by: Eugeniy Paltsev <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-01dmaengine: dw-axi-dmac: Set constraint to the Max segment sizeSia Jee Heng2-0/+9
Add support for DMA Scatter-Gather (SG) constraint so that DMA clients can handle the AxiDMA limitation. Without supporting DMA constraint the default Max segment size reported by dmaengine is 64KB, which is not supported by Intel KeemBay AxiDMA. Signed-off-by: Sia Jee Heng <[email protected]> Tested-by: Eugeniy Paltsev <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Reviewed-by: Eugeniy Paltsev <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-01dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD registersSia Jee Heng1-0/+26
Add support for Intel KeemBay AxiDMA BYTE and HALFWORD registers programming. Intel KeemBay AxiDMA supports data transfer between device to memory and memory to device operations. This code is needed by I2C, I3C, I2S, SPI and UART which uses FIFO size of 8bits and 16bits to perform memory to device data transfer operation. 0-padding functionality is provided to avoid pre-processing of data on CPU. Signed-off-by: Sia Jee Heng <[email protected]> Tested-by: Eugeniy Paltsev <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Reviewed-by: Eugeniy Paltsev <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-01dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshakeSia Jee Heng1-0/+50
Add support for Intel KeemBay AxiDMA device handshake programming. Device handshake number passed in to the AxiDMA shall be written to the Intel KeemBay AxiDMA hardware handshake registers before DMA operations are started. Signed-off-by: Sia Jee Heng <[email protected]> Tested-by: Eugeniy Paltsev <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Reviewed-by: Eugeniy Paltsev <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-01dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA supportSia Jee Heng1-0/+8
Add support for Intel KeemBay AxiDMA to the .compatible field. The AxiDMA Apb region will be accessible if the compatible string matches the "intel,kmb-axi-dma". Signed-off-by: Sia Jee Heng <[email protected]> Tested-by: Eugeniy Paltsev <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Reviewed-by: Eugeniy Paltsev <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-01dmaengine: drivers: Kconfig: add HAS_IOMEM dependency to DW_AXI_DMACSia Jee Heng1-0/+1
If HAS_IOMEM is not defined and DW_AXI_DMAC is enabled under COMPILE_TEST, the build fails with the following error: dw-axi-dmac-platform.c:(.text+0xc4): undefined reference to `devm_ioremap_resource' Link: https://www.spinics.net/lists/dmaengine/msg25188.html Reported-by: kernel test robot <[email protected]> Signed-off-by: Sia Jee Heng <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-01dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fieldsSia Jee Heng1-0/+14
Add support for Intel KeemBay DMA registers. These registers are required to run data transfer between device to memory and memory to device on Intel KeemBay SoC. Signed-off-by: Sia Jee Heng <[email protected]> Tested-by: Eugeniy Paltsev <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Reviewed-by: Eugeniy Paltsev <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-01dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMASia Jee Heng1-0/+5
Add support for Intel KeemBay AxiDMA to the dw-axi-dmac Schemas DT binding. Signed-off-by: Sia Jee Heng <[email protected]> Reviewed-by: Eugeniy Paltsev <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-01dmaengine: dw-axi-dmac: Support burst residue granularitySia Jee Heng2-7/+38
Add support for DMA_RESIDUE_GRANULARITY_BURST so that AxiDMA can report DMA residue. Existing AxiDMA driver only support data transfer between memory to memory operation, therefore reporting DMA residue to the DMA clients is not supported. Reporting DMA residue to the DMA clients is important as DMA clients shall invoke dmaengine_tx_status() to understand the number of bytes been transferred so that the buffer pointer can be updated accordingly. Signed-off-by: Sia Jee Heng <[email protected]> Tested-by: Eugeniy Paltsev <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Reviewed-by: Eugeniy Paltsev <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-01dmaengine: dw-axi-dmac: Support of_dma_controller_register()Sia Jee Heng2-0/+27
Add support for of_dma_controller_register() so that DMA clients can pass in device handshake number to the AxiDMA driver. DMA clients shall code the device handshake number in the Device tree. When DMA activities are needed, DMA clients shall invoke OF helper function to pass in the device handshake number to the AxiDMA. Without register to the of_dma_controller_register(), data transfer between memory to device and device to memory operations would failed. Signed-off-by: Sia Jee Heng <[email protected]> Tested-by: Eugeniy Paltsev <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Reviewed-by: Eugeniy Paltsev <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-01dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic()Sia Jee Heng2-7/+106
Add support for device_prep_dma_cyclic() callback function to benefit DMA cyclic client, for example ALSA. Existing AxiDMA driver only support data transfer between memory to memory. Data transfer between device to memory and memory to device in cyclic mode would failed if this interface is not supported by the AxiDMA driver. Signed-off-by: Sia Jee Heng <[email protected]> Tested-by: Eugeniy Paltsev <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Reviewed-by: Eugeniy Paltsev <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-01dmaengine: dw-axi-dmac: Support device_prep_slave_sgSia Jee Heng2-0/+155
Add device_prep_slave_sg() callback function so that DMA_MEM_TO_DEV and DMA_DEV_TO_MEM operations in single mode can be supported. Existing AxiDMA driver only support data transfer between memory to memory. Data transfer between device to memory and memory to device in single mode would failed if this interface is not supported by the AxiDMA driver. Signed-off-by: Sia Jee Heng <[email protected]> Tested-by: Eugeniy Paltsev <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Reviewed-by: Eugeniy Paltsev <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-01dmaengine: dw-axi-dmac: Add device_config operationSia Jee Heng2-0/+12
Add device_config() callback function so that the device address can be passed to the dma driver. DMA clients use this interface to pass in the device address to the AxiDMA. Without this interface, data transfer between device to memory and memory to device would failed. Signed-off-by: Sia Jee Heng <[email protected]> Tested-by: Eugeniy Paltsev <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Reviewed-by: Eugeniy Paltsev <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-01dmaengine: dw-axi-dmac: Add device_synchronize() callbackSia Jee Heng1-0/+8
Add support for device_synchronize() callback function to sync with dmaengine_terminate_sync(). Signed-off-by: Sia Jee Heng <[email protected]> Tested-by: Eugeniy Paltsev <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Reviewed-by: Eugeniy Paltsev <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-01dmaengine: dw-axi-dmac: move dma_pool_create() to alloc_chan_resources()Sia Jee Heng2-12/+14
The DMA memory block is created at driver load time and exist for device lifetime. Move the dma_pool_create() to the ->chan_resource() callback function allowing the DMA memory blocks to be created as needed and destroyed when the channel is freed. Signed-off-by: Sia Jee Heng <[email protected]> Tested-by: Eugeniy Paltsev <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Reviewed-by: Eugeniy Paltsev <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-01dmaengine: dw-axi-dmac: simplify descriptor managementSia Jee Heng2-71/+102
Simplify and refactor the descriptor management by removing the redundant Linked List Item (LLI) queue control logic from the AxiDMA driver. The descriptor is split into virtual descriptor and hardware LLI so that only hardware LLI memories are allocated from the DMA memory pool. Up to 64 descriptors can be allocated within a PAGE_SIZE compare to 16 descriptors in previous version. This solves the problem where an ALSA driver expects more than 16 DMA descriptors to run. Signed-off-by: Sia Jee Heng <[email protected]> Tested-by: Eugeniy Paltsev <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Reviewed-by: Eugeniy Paltsev <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-01dt-bindings: dma: Add YAML schemas for dw-axi-dmacSia Jee Heng2-39/+121
YAML schemas Device Tree (DT) binding is the new format for DT to replace the old format. Introduce YAML schemas DT binding for dw-axi-dmac and remove the old version. Signed-off-by: Sia Jee Heng <[email protected]> Reviewed-by: Eugeniy Paltsev <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-01dmaengine: ti: k3-psil: optimize struct psil_endpoint_config for sizeGrygorii Strashko1-7/+6
Optimize struct psil_endpoint_config for size by - reordering fields - grouping bitfields - change mapped_channel_id type to s16 (32K channel is enough) - default_flow_id type to s16 as it's assigned to -1 before: text data bss dec hex filename 12654100 5211472 666904 18532476 11ac87c vmlinux after: 12654100 5208528 666904 18529532 11abcfc vmlinux diff: 2944 bytes Signed-off-by: Grygorii Strashko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-01dmaengine: INTEL_LDMA should depend on X86Geert Uytterhoeven1-1/+2
The Intel Lightning Mountain (LGM) DMA controller is only present on Intel Lightning Mountain SoCs. Hence add a dependency on X86, to prevent asking the user about this driver when configuring a kernel without Intel Lightning Mountain platform support. While at it, fix a misspelling of "Intel". Fixes: 32d31c79a1a4fbc4 ("dmaengine: Add Intel LGM SoC DMA support.") Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-01dmaengine: rcar-dmac: Add support for R-Car V3UGeert Uytterhoeven1-23/+58
The DMACs (both SYS-DMAC and RT-DMAC) on R-Car V3U differ slightly from the DMACs on R-Car Gen2 and other R-Car Gen3 SoCs: 1. The per-channel registers are located in a second register block. Add support for mapping the second block, using the appropriate offsets and stride. 2. The common Channel Clear Register (DMACHCLR) was replaced by a per-channel register. Update rcar_dmac_chan_clear{,_all}() to handle this. As rcar_dmac_init() needs to clear the status before the individual channels are probed, channel index and base address initialization are moved forward. Inspired by a patch in the BSP by Phong Hoang <[email protected]>. Signed-off-by: Geert Uytterhoeven <[email protected]> Tested-by: Wolfram Sang <[email protected]> Tested-by: Yoshihiro Shimoda <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-01dmaengine: rcar-dmac: Add helpers for clearing DMA channel statusGeert Uytterhoeven1-2/+13
Extract the code to clear the status of one or all channels into their own helpers, to prepare for the different handling of the R-Car V3U SoC. Signed-off-by: Geert Uytterhoeven <[email protected]> Tested-by: Wolfram Sang <[email protected]> Tested-by: Yoshihiro Shimoda <[email protected]> Reviewed-by: Wolfram Sang <[email protected]> Reviewed-by: Laurent Pinchart <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-01dmaengine: rcar-dmac: Add for_each_rcar_dmac_chan() helperGeert Uytterhoeven1-12/+10
Add a helper macro for iterating over all DMAC channels, taking into account the channel mask. Use it where appropriate, to simplify code. Restore "reverse Christmas tree" order of local variables while adding a new variable. Signed-off-by: Geert Uytterhoeven <[email protected]> Tested-by: Wolfram Sang <[email protected]> Tested-by: Yoshihiro Shimoda <[email protected]> Reviewed-by: Wolfram Sang <[email protected]> Reviewed-by: Laurent Pinchart <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-01dt-bindings: renesas,rcar-dmac: Add r8a779a0 supportGeert Uytterhoeven1-28/+48
Document the compatible value for the Direct Memory Access Controller blocks in the Renesas R-Car V3U (R8A779A0) SoC. The most visible difference with DMAC blocks on other R-Car SoCs is the move of the per-channel registers to a separate register block. Signed-off-by: Geert Uytterhoeven <[email protected]> Tested-by: Yoshihiro Shimoda <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Laurent Pinchart <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-01-27dmaengine: stedma40: fix 'physical' typoBjorn Helgaas1-1/+1
Fix misspelling of "physical". Signed-off-by: Bjorn Helgaas <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-01-27dmaengine: qcom: bam_dma: Manage clocks when controlled_remotely is setThara Gopinath1-14/+15
When bam dma is "controlled remotely", thus far clocks were not controlled from the Linux. In this scenario, Linux was disabling runtime pm in bam dma driver and not doing any clock management in suspend/resume hooks. With introduction of crypto engine bam dma, the clock is a rpmh resource that can be controlled from both Linux and TZ/remote side. Now bam dma clock is getting enabled during probe even though the bam dma can be "controlled remotely". But due to clocks not being handled properly, bam_suspend generates a unbalanced clk_unprepare warning during system suspend. To fix the above issue and to enable proper clock-management, this patch enables runtim-pm and handles bam dma clocks in suspend/resume hooks if the clock node is present irrespective of controlled_remotely property. Signed-off-by: Thara Gopinath <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Tested-by: John Stultz <[email protected]> Reviewed-by: Shawn Guo <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-01-26dmaengine: idxd: add module parameter to force disable of SVADave Jiang2-1/+13
Add a module parameter that overrides the SVA feature enabling. This keeps the driver in legacy mode even when intel_iommu=sm_on is set. In this mode, the descriptor fields must be programmed with dma_addr_t from the Linux DMA API for source, destination, and completion descriptors. Signed-off-by: Dave Jiang <[email protected]> Link: https://lore.kernel.org/r/161134110457.4005461.13171197785259115852.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <[email protected]>
2021-01-26dmaengine: mmp_tdma: Allow building as a moduleLubomir Rintel1-1/+1
There is no reason the Marvell MMP two-channel audio DMA driver would have to be built-in. Signed-off-by: Lubomir Rintel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-01-26dmaengine: mmp_pdma: Allow building as a moduleLubomir Rintel1-1/+1
There is no reason the Marvell MMP peripheral DMA driver would have to be built-in. Signed-off-by: Lubomir Rintel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-01-26dmaengine: mmp_pdma: Remove mmp_pdma_filter_fn()Lubomir Rintel2-30/+0
It's not used anywhere -- drop it. Signed-off-by: Lubomir Rintel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-01-26dmaengine: remove coh901318 driverArnd Bergmann7-3374/+0
The ST-Ericsson U300 platform is getting removed, so this driver is no longer needed. Signed-off-by: Arnd Bergmann <[email protected]> Reviewed-by: Linus Walleij <[email protected]> Cc: Linus Walleij <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-01-26dmaengine: remove zte zx driverArnd Bergmann4-989/+0
The zte zx platform is getting removed, so this driver is no longer needed. Signed-off-by: Arnd Bergmann <[email protected]> Cc: Jun Nie <[email protected]> Cc: Shawn Guo <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-01-26dmaengine: remove sirfsoc driverArnd Bergmann5-1229/+0
The CSR SiRF prima2/atlas platforms are getting removed, so this driver is no longer needed. Signed-off-by: Arnd Bergmann <[email protected]> Acked-by: Barry Song <[email protected]> Cc: Barry Song <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-01-26dt-bindings: dma: intel-ldma: Fix $ref specifierBjorn Andersson1-1/+1
The $ref for "intel,dma-poll-cnt" is missing an '/', causing dt_binding_check to fail. Fix this. Fixes: afd4df85602d ("dt-bindings: dma: Add bindings for Intel LGM SoC") Signed-off-by: Bjorn Andersson <[email protected]> Acked-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-01-26MAINTAINERS: ioat: remove dmaengine susbstem filesVinod Koul1-2/+0
[1] mentions the IOAT entry contains dmaengine subsystem file. So update the entry and remove the dmaengine files 1: https://lwn.net/Articles/842415/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-01-26MAINTAINERS: dmaengine: add header files directoryVinod Koul1-0/+1
Somehow dmaengine header files are missed in the entry so update it Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-01-26dmaengine: jz4780: Add support for the JZ4760(B)Paul Cercueil1-0/+14
Add support for the JZ4760 and JZ4760B SoCs. Both SoCs have only 5 DMA channels per chip. The JZ4760B introduced the DCKES/DCKEC registers. Signed-off-by: Paul Cercueil <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-01-26dt-bindings: dma: ingenic: Add compatible strings for JZ4760(B) SoCsPaul Cercueil1-0/+2
Add ingenic,jz4760-dma and ingenic,jz4760b-dma compatible strings to support the DMA engines present in the JZ4760 and JZ4760B SoCs. Signed-off-by: Paul Cercueil <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-01-26dmaengine: imx-sdma: Use of_device_get_match_data()Fabio Estevam1-10/+1
Use of_device_get_match_data() to make the code simpler. Signed-off-by: Fabio Estevam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-01-26dmaengine: imx-sdma: Remove platform data supportFabio Estevam2-36/+10
Since 5.10-rc1, i.MX has been converted to a devicetree-only platform. The platform data support in this driver was only used for non-DT platforms. Remove the platform data support as it has no more users. Signed-off-by: Fabio Estevam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-01-17dmaengine: idxd: set DMA channel to be privateDave Jiang1-0/+1
Add DMA_PRIVATE attribute flag to idxd DMA channels. The dedicated WQs are expected to be used by a single client and not shared. While doing NTB testing this mistake was discovered, which prevented ntb_transport from requesting DSA wqs as DMA channels via dma_request_channel(). Reported-by: Srinijia Kambham <[email protected]> Signed-off-by: Dave Jiang <[email protected]> Tested-by: Srinijia Kambham <[email protected]> Fixes: 8f47d1a5e545 ("dmaengine: idxd: connect idxd to dmaengine subsystem") Link: https://lore.kernel.org/r/161074758743.2184057.3388557138816350980.stgit@djiang5-desk3.ch.intel.com Signed-off-by: Vinod Koul <[email protected]>
2021-01-17dmaengine: qcom: gpi: Remove unneeded semicolonXu Wang1-1/+1
fix semicolon.cocci warning: drivers/dma/qcom/gpi.c:1703:2-3: Unneeded semicolon Signed-off-by: Xu Wang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-01-13dmaengine: hsu: disable spurious interruptFerry Toth1-10/+11
On Intel Tangier B0 and Anniedale the interrupt line, disregarding to have different numbers, is shared between HSU DMA and UART IPs. Thus on such SoCs we are expecting that IRQ handler is called in UART driver only. hsu_pci_irq was handling the spurious interrupt from HSU DMA by returning immediately. This wastes CPU time and since HSU DMA and HSU UART interrupt occur simultaneously they race to be handled causing delay to the HSU UART interrupt handling. Fix this by disabling the interrupt entirely. Fixes: 4831e0d9054c ("serial: 8250_mid: handle interrupt correctly in DMA case") Signed-off-by: Ferry Toth <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-01-13dmaengine: ti: k3-udma: Do not initialize ret in tisci channel config functionsPeter Ujfalusi1-7/+7
The ret does not need to be initialized to 0 in the tisci channel config functions. Signed-off-by: Peter Ujfalusi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-01-13dmaengine: ti: k3-udma: Add support for burst_size configuration for mem2memPeter Ujfalusi1-5/+111
The UDMA and BCDMA can provide higher throughput if the burst_size of the channel is changed from it's default (which is 64 bytes) for Ultra-high and high capacity channels. This performance benefit is even more visible when the buffers are aligned with the burst_size configuration. The am654 does not have a way to change the burst size, but it is using 64 bytes burst, so increasing the copy_align from 8 bytes to 64 (and clients taking that into account) can increase the throughput as well. Numbers gathered on j721e: echo 8000000 > /sys/module/dmatest/parameters/test_buf_size echo 2000 > /sys/module/dmatest/parameters/timeout echo 50 > /sys/module/dmatest/parameters/iterations echo 1 > /sys/module/dmatest/parameters/max_channels Prior this patch: ~1.3 GB/s After this patch: ~1.8 GB/s with 1 byte alignment: ~1.7 GB/s Signed-off-by: Peter Ujfalusi <[email protected]> Signed-off-by: Peter Ujfalusi <[email protected]> Tested-by: Kishon Vijay Abraham I <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-01-13dmaengine: Extend the dmaengine_alignment for 128 and 256 bytesPeter Ujfalusi1-0/+2
Some DMA device can benefit with higher order of alignment than the maximum of 64 bytes currently defined. Define 128 and 256 bytes alignment for these devices. Signed-off-by: Peter Ujfalusi <[email protected]> Signed-off-by: Peter Ujfalusi <[email protected]> Tested-by: Kishon Vijay Abraham I <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-01-13dmaengine: ti: k3-udma: Set rflow count for BCDMA split channelsVignesh Raghavendra1-0/+1
BCDMA RX channels have one flow per channel, therefore set the rflow_cnt to rchan_cnt. Without this patch, request for BCDMA RX channel allocation fails as rflow_cnt is 0 thus fails to reserve a rflow for the channel. Fixes: 8844898028d4 ("dmaengine: ti: k3-udma: Add support for BCDMA channel TPL handling") Signed-off-by: Vignesh Raghavendra <[email protected]> Acked-by: Peter Ujfalusi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-01-13dmaengine: qcom: Always inline gpi_update_regNathan Chancellor1-1/+1
When building with CONFIG_UBSAN_UNSIGNED_OVERFLOW, clang decides not to inline gpi_update_reg, which causes a linkage failure around __bad_mask: ld.lld: error: undefined symbol: __bad_mask >>> referenced by bitfield.h:119 (include/linux/bitfield.h:119) >>> dma/qcom/gpi.o:(gpi_update_reg) in archive drivers/built-in.a >>> referenced by bitfield.h:119 (include/linux/bitfield.h:119) >>> dma/qcom/gpi.o:(gpi_update_reg) in archive drivers/built-in.a If gpi_update_reg is not inlined, the mask value will not be known at compile time so the check in field_multiplier stays in the final object file, causing the above linkage failure. Always inline gpi_update_reg so that this check can never fail. Fixes: 5d0c3533a19f ("dmaengine: qcom: Add GPI dma driver") Link: https://github.com/ClangBuiltLinux/linux/issues/1243 Signed-off-by: Nathan Chancellor <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-01-12dmaengine: owl-dma: Fix a resource leak in the remove functionChristophe JAILLET1-0/+1
A 'dma_pool_destroy()' call is missing in the remove function. Add it. This call is already made in the error handling path of the probe function. Fixes: 47e20577c24d ("dmaengine: Add Actions Semi Owl family S900 DMA driver") Signed-off-by: Christophe JAILLET <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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