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2013-07-03drm/radeon: fix endian bug in radeon_atom_get_mclk_range_table()Alex Deucher1-1/+1
Signed-off-by: Alex Deucher <[email protected]>
2013-07-02drm/radeon/dpm: fix compilation with certain versions of gccMike Lothian6-0/+6
Add #include <linux/seq_file.h> to *_dpm.c files Signed-off-by: Alex Deucher <[email protected]>
2013-07-02drm/radeon/dpm: clarify debugfs warningAlex Deucher1-1/+1
For chips without debugfs dpm support say that it's not implemented rather than not supported to avoid confusion about DPM support in general. Signed-off-by: Alex Deucher <[email protected]>
2013-07-01drm/radeon/dpm: add debugfs support for SIAlex Deucher4-0/+26
This allows you to look at the current DPM state via debugfs. Signed-off-by: Alex Deucher <[email protected]>
2013-07-01drm/radeon/dpm: add debugfs support for caymanAlex Deucher4-0/+27
This allows you to look at the current DPM state via debugfs. Signed-off-by: Alex Deucher <[email protected]>
2013-07-01drm/radeon/dpm: add debugfs support for TNAlex Deucher3-0/+24
This allows you to look at the current DPM state via debugfs. Signed-off-by: Alex Deucher <[email protected]>
2013-07-01drm/radeon/dpm: add debugfs support for ON/LNAlex Deucher3-0/+31
This allows you to look at the current DPM state via debugfs. Signed-off-by: Alex Deucher <[email protected]>
2013-07-01drm/radeon/dpm: add debugfs support for 7xx/evergreen/btcAlex Deucher4-0/+39
This allows you to look at the current DPM state via debugfs. Signed-off-by: Alex Deucher <[email protected]>
2013-07-01drm/radeon/dpm: add debugfs support for rv6xxAlex Deucher3-0/+28
This allows you to look at the current DPM state via debugfs. Signed-off-by: Alex Deucher <[email protected]>
2013-07-01drm/radeon/dpm: add infrastructure to support debugfs infoAlex Deucher2-13/+29
This lays the frameworks to report realtime power level feedback. Signed-off-by: Alex Deucher <[email protected]>
2013-07-01drm/radeon/dpm: re-enable state transitions for CaymanAlex Deucher1-5/+0
Was disabled due to stability issues on certain boards caused by the a bug in the parsing of the atom mc reg tables. That's fixed now so re-enable. Signed-off-by: Alex Deucher <[email protected]>
2013-07-01drm/radeon/dpm: re-enable state transitions for BTCAlex Deucher1-3/+0
Was disabled due to stability issues on certain boards caused by the a bug in the parsing of the atom mc reg tables. That's fixed now so re-enable. Signed-off-by: Alex Deucher <[email protected]>
2013-07-01drm/radeon: fix typo in radeon_atom_init_mc_reg_table()Alex Deucher1-1/+2
Bad pointer math. Fixes hangs in state transitions with BTC+ asics. Signed-off-by: Alex Deucher <[email protected]>
2013-07-01drm/radeon/atom: fix endian bug in radeon_atom_init_mc_reg_table()Alex Deucher1-1/+1
Signed-off-by: Alex Deucher <[email protected]>
2013-07-01drm/radeon: remove sumo dpm/uvd bringup leftoversAlex Deucher1-17/+0
Function doesn't do anything useful. Signed-off-by: Alex Deucher <[email protected]>
2013-07-01Merge branch 'drm-nouveau-next' of ↵Dave Airlie138-5449/+7058
git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next - Various fixes that make surviving concurrent piglit more possible. - Buffer object deletion no longer synchronous - Context/register initialisation updates that have been reported to solve some stability issues (particularly on some problematic GF119 chips) - Kernel side support for VP2 video decoding engines * 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (44 commits) drm/nvd0-/disp: handle case where display engine is missing/disabled drm/gr/nvc0-: merge nvc0/nve0 ucode, and use cpp instead of m4 drm/nouveau/bsp/nv84: initial vp2 engine implementation drm/nouveau/vp/nv84: initial vp2 engine implementation drm/nouveau/core: xtensa engine base class implementation drm/nouveau/vdec: fork vp3 implementations from vp2 drm/nouveau/core: move falcon class to engine/ drm/nouveau/kms: don't fail if there's no dcb table entries drm/nouveau: remove limit on gart drm/nouveau/vm: perform a bar flush when flushing vm drm/nvc0/gr: cleanup register lists, and add nvce/nvcf to switches drm/nvc8/gr: update initial register/context values drm/nvc4/gr: update initial register/context values drm/nvc1/gr: update initial register/context values drm/nvc3/gr: update initial register/context values drm/nvc0/gr: update initial register/context values drm/nvd9/gr: update initial register/context values drm/nve4/gr: update initial register/context values drm/nvc0-/gr: bump maximum gpc/tpc limits drm/nvf0/gr: initial register/context setup ...
2013-07-01drm/nvd0-/disp: handle case where display engine is missing/disabledMaarten Lankhorst6-7/+17
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/gr/nvc0-: merge nvc0/nve0 ucode, and use cpp instead of m4Ben Skeggs14-2587/+1270
No code changes, proven by envyas producing identical binaries. Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nouveau/bsp/nv84: initial vp2 engine implementationIlia Mirkin3-14/+16
Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nouveau/vp/nv84: initial vp2 engine implementationIlia Mirkin4-14/+17
Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nouveau/core: xtensa engine base class implementationIlia Mirkin3-0/+209
Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nouveau/vdec: fork vp3 implementations from vp2Ilia Mirkin6-14/+204
Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nouveau/core: move falcon class to engine/Ben Skeggs11-24/+21
Not really "core" per-se. About to merge Ilia's work adding another similar class for the VP2 xtensa engines, so, seems like a good time to move all these to engine/. Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nouveau/kms: don't fail if there's no dcb table entriesBen Skeggs2-7/+9
Fixes module not loading on Tesla K20. Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nouveau: remove limit on gartMaarten Lankhorst1-5/+0
Most graphics cards nowadays have a multiple of this limit as their vram, so limiting GART doesn't seem to make much sense. Signed-off-by: Maarten >Lnkhorst <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nouveau/vm: perform a bar flush when flushing vmMaarten Lankhorst2-0/+8
Appears to fix the regression from "drm/nvc0/vm: handle bar tlb flushes internally". nvidia always seems to do this flush after writing values. Signed-off-by: Maarten Lankhorst <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nvc0/gr: cleanup register lists, and add nvce/nvcf to switchesBen Skeggs6-600/+344
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nvc8/gr: update initial register/context valuesBen Skeggs6-10/+74
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nvc4/gr: update initial register/context valuesBen Skeggs6-9/+62
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nvc1/gr: update initial register/context valuesBen Skeggs6-35/+80
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nvc3/gr: update initial register/context valuesBen Skeggs6-12/+112
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nvc0/gr: update initial register/context valuesBen Skeggs6-544/+1042
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nvd9/gr: update initial register/context valuesBen Skeggs6-74/+482
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nve4/gr: update initial register/context valuesBen Skeggs4-157/+31
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nvc0-/gr: bump maximum gpc/tpc limitsBen Skeggs1-2/+4
Needed for GK110, separate commit to catch any unexpected breaks to other parts of the code. Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nvf0/gr: initial register/context setupBen Skeggs6-482/+1057
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nve7/gr: update initial register/context valuesBen Skeggs4-3/+12
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nve6/gr: update initial register/context valuesBen Skeggs4-113/+383
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nouveau: delay busy bo vma removal until fence signalsBen Skeggs4-15/+108
As opposed to an explicit wait. Allows userspace to not stall waiting on buffer deletion. Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nouveau/vm: make each vma take a reference on its parent vmBen Skeggs1-1/+4
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nouveau/core: remove nouveau_mm.mutex, no more usersBen Skeggs3-5/+2
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nouveau/vm: take subdev mutex, not the mm, protects against race with ↵Ben Skeggs1-16/+17
vm/nvc0 nvc0_vm_flush() accesses the pgd list, which will soon be able to race with vm_unlink() during channel destruction. Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nvc0/vm: handle bar tlb flushes internallyBen Skeggs3-34/+28
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nv50-/vm: take mutex rather than irqsave spinlockBen Skeggs2-10/+4
These operations can take quite some time, and we really don't want to have to hold a spinlock for too long. Now that the lock ordering for vm and the gr/nv84 hw bug workaround has been reversed, it's possible to use a mutex here. Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nv50/vm: remove explicit vm knowledge from enginesBen Skeggs9-66/+31
This reverses the lock ordering between VM and gr/nv84:nvc0. Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nv50/vm: handle bar tlb flushes internallyBen Skeggs3-5/+13
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nvc0/gr: port mp trap handling from calim's kepler codeBen Skeggs1-6/+38
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nve0/gr: attempt to resume after sm trapsBen Skeggs1-16/+6
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nve0/gr: s/tp/tpc/Ben Skeggs1-26/+27
NVIDIA's name... Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nve0/fifo: create our playlists up-front, at startupBen Skeggs1-14/+14
Signed-off-by: Ben Skeggs <[email protected]>
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