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2012-10-03drm/nouveau/gpio: expose the PWM/TOGGLE parameter found in the gpio vbios tableMartin Peres2-0/+10
Signed-off-by: Martin Peres <[email protected]> Reviewed-by: Ben Skeggs <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau: fix pm initialization orderDmitry Eremin-Solenikov1-1/+2
If nouveau_pm_perflvl_get() fails, pm->profiles list will be left uninitialized, which causes oops during nouveau_pm_fini(). Move INIT_LIST_HEAD before call to nouveau_pm_perflvl_get(). Signed-off-by: Dmitry Eremin-Solenikov <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/bios: check that fixed tvdac gpio data is valid before using itBen Skeggs1-7/+11
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau: log channel debug/error messages from client object rather than ↵Ben Skeggs1-5/+5
drm client This will make it more obvious which application caused particular messages. Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau: have drm debugging macros build on top of core macrosBen Skeggs1-13/+6
May kill the DRM version completely at some point, undecided.. Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/core: have client-id be a string, rather than an integerBen Skeggs4-10/+14
Can be somewhat more informative that way... Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nvc0/fifo: re-bash PBUS regs after vm-fault to BARs/PEEPHOLEBen Skeggs1-4/+18
Seems to be required to "re-arm" the engines after a vm fault. Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nvc0/gr: implement initial trap handlerBen Skeggs1-4/+188
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nvc0/gr: rebuild fuc with latest envyasBen Skeggs4-12/+167
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nvc0/ltcg: read LTS count at startupBen Skeggs1-1/+3
Not really sure how to confirm this 100%, but, the numbers match on all the traces I have for NVCx (2 LTS), NVD9 (1LTS) and NVEx (4LTS). Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nve0/gr: enable use of our fuc by defaultBen Skeggs1-1/+1
Graphics acceleration is still disabled by default due to lingering issues that need to be solved. Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nve0/gr: remove 0x404160 bashing from hub fucBen Skeggs2-282/+189
Triggers PIBUS interrupts due to register not existing anymore, and as a result HUB_SET_CHAN times out. After this commit, our fuc loads and can accelerate at least fbcon, X, glxgears and OA on NVE4. NVE7 not tested as of yet. Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nve0/gr: initial fuc implementation, based on fermi's codeBen Skeggs6-69/+3235
Currently identical except the available chipset register lists. This will *not* currently work and is disabled by default because of this. May get merged again later, remains to be seen what further changes will be required. Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nve0/ibus: handle PIBUS interrupts to prevent stormBen Skeggs6-0/+162
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/sw: trap and clear PMC_INTR_0_SOFTWAREBen Skeggs5-0/+12
Came in useful for debugging another issue earlier, so keep it around. Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau: quiet some static-related sparse noiseMarcin Slusarz25-47/+51
Signed-off-by: Marcin Slusarz <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau: constify instances of nouveau_bitfield and nouveau_enum structsMarcin Slusarz12-39/+39
Signed-off-by: Marcin Slusarz <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/fifo: use defines instead of hardcoded class idsBen Skeggs9-12/+20
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/dmaobj: reject unsupported parent types instead of half-succeedingBen Skeggs2-10/+16
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau: add defines for internal class namesBen Skeggs1-14/+35
Will probably flesh the documentation of the classes out a bit too at some later point. Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nv50/fifo: add support for dma channel classBen Skeggs3-7/+72
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nv84/fifo: add support for dma channel classBen Skeggs3-7/+81
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/fifo: version the dma channel class structBen Skeggs6-6/+6
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/fifo: separate object classes for dma channelsBen Skeggs6-5/+10
Future code will use the object class rather than chipset checks in order to identify available channel features. Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau: restore fifo chid information in engine error messagesBen Skeggs15-132/+213
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/core: have fifo store a unique context identifier at attach timeBen Skeggs11-2/+23
This value will match something that's easily available from the engine IRQ handlers, and used to lookup the relevant context. Since the changes in how this is done on each generation match when the major PFIFO changes happened, fifo is responsible for calculating the correct value to avoid duplicating the same code among many engine modules. Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/fifo: add method to lookup fifo chid related to a given objectBen Skeggs2-0/+17
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/core: protect engine context list with hardirq-safe spinlockBen Skeggs4-20/+60
IRQ handlers will need access to engine contexts. Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nv84/fifo: mask only the engine we're waiting on for channel unloadBen Skeggs1-6/+10
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nve0: use async copy engine for ttm buffer moves if availableBen Skeggs7-26/+72
Kepler PFIFO lost the ability to address multiple engines from a single channel, so we need a separate one for the copy engine. v2: Marcin Slusarz <[email protected]> - regression fix: restore hw accelerated buffer copies Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nve0/copy: add initial support for the async copy enginesBen Skeggs4-0/+164
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nve0/fifo: support engine selection when creating fifo channelsBen Skeggs7-13/+64
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/device: return proper error codes if ioremap failsBen Skeggs1-3/+3
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/core: remove some left-over pieces from the porting processBen Skeggs3-21/+0
Reported-by: Marcin Slusarz <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nvc0-/gr: remove reset-after-grctx-construction hackBen Skeggs3-34/+9
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau: add Kconfig options for debug controlBen Skeggs2-9/+29
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau: port remainder of drm code, and rip out compat layerBen Skeggs70-4174/+3095
v2: Ben Skeggs <[email protected]> - fill in nouveau_pm.dev to prevent oops - fix ppc issues (build + OF shadow) Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/device: include the official chipset namesBen Skeggs9-1/+61
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/backlight: remove dependence on nouveau_drv.hBen Skeggs6-59/+60
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau: flatten nv{Read,Write}{MC,VIDEO,FB,EXTDEV}Ben Skeggs6-76/+24
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau: move compat ioctl out of nouveau_drv.hBen Skeggs5-5/+9
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/acpi: move definitions out of nouveau_drv.hBen Skeggs7-36/+40
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/mxm: split up into bios code and a subdev moduleBen Skeggs16-755/+952
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau: start culling unused codeBen Skeggs8-239/+4
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau: port all engines to new engine module formatBen Skeggs146-11099/+14219
This is a HUGE commit, but it's not nearly as bad as it looks - any problems can be isolated to a particular chipset and engine combination. It was simply too difficult to port each one at a time, the compat layers are *already* ridiculous. Most of the changes here are simply to the glue, the process for each of the engine modules was to start with a standard skeleton and copy+paste the old code into the appropriate places, fixing up variable names etc as needed. v2: Marcin Slusarz <[email protected]> - fix find/replace bug in license header v3: Ben Skeggs <[email protected]> - bump indirect pushbuf size to 8KiB, 4KiB barely enough for userspace and left no space for kernel's requirements during GEM pushbuf submission. - fix duplicate assignments noticed by clang v4: Marcin Slusarz <[email protected]> - add sparse annotations to nv04_fifo_pause/nv04_fifo_start - use ioread32_native/iowrite32_native for fifo control registers v5: Ben Skeggs <[email protected]> - rebase on v3.6-rc4, modified to keep copy engine fix intact - nv10/fence: unmap fence bo before destroying - fixed fermi regression when using nvidia gr fuc - fixed typo in supported dma_mask checking Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nvc0-/gr: generate grctx template at init time, not first context ctorBen Skeggs5-604/+460
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nvc0-/gr: share headers between fermi and kepler graphics codeBen Skeggs6-204/+143
v2: Ben Skeggs <[email protected]> - de-inline nv_icmd, triggers some gcc issue causing ctxnv[ce]0.c to take a *very* *very* long time to build on some configs. Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/pageflip: kick flip handling out of engsw and into fenceBen Skeggs17-114/+265
This is all very much a policy thing, and hence will not belong in SW after the rework. engsw now only handles receiving the event to say "can flip now" and makes a callback to perform the actual work. Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau: move some more code around to more appropriate placesBen Skeggs4-342/+336
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nvc0-nve0/graph: rename dev to priv, no code changesBen Skeggs2-5170/+5170
There's a *lot* of code in here, and it's all going to use the PGRAPH priv pointer rather than drm_device after the engine rework. This is handling all the rename-only parts of the change. Signed-off-by: Ben Skeggs <[email protected]>
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