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2017-01-27drm/amd/amdgpu: remove the uncessary parameter for ib schedulerJunwei Zhang13-18/+17
Signed-off-by: Junwei Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu: Bring bo creation in line with radeon driver (v2)Nils Holland1-0/+20
Add the bo creation changes that have been done to the radeon driver in recent times, e.g. disable GTT WC on 32 bit because it is broken there, and also disable it generally (and print a warning message) when CONFIG_X86_PAT is not set. v2: agd: fix warning in defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) case Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Nils Holland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amd/powerplay: fix misspelling in header guardNicolas Iooss1-1/+1
In smu7_clockpowergating.h, the #ifndef statement which prevents multiple inclusions of the header file uses _SMU7_CLOCK_POWER_GATING_H_ but the following #define statement uses _SMU7_CLOCK__POWER_GATING_H_. Signed-off-by: Nicolas Iooss <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/ttm: revert "add optional LRU removal callback v2"Christian König2-14/+5
Without the custom LRU management the callback is not used any more. agd: fix trivial warning Reviewed-by: Sinclair Yeh <[email protected]> Signed-off-by: Christian König <[email protected]> Reviewed-and-Tested-by: Roger.He <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/ttm: revert "implement LRU add callbacks v2"Christian König13-45/+5
The additional housekeeping had too much CPU overhead, let's use the BO priorities instead. agd: also revert hibmc changes Reviewed-by: Sinclair Yeh <[email protected]> Signed-off-by: Christian König <[email protected]> Reviewed-and-Tested-by: Roger.He <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu: double the priority of kernel allocationsChristian König1-0/+2
Give kernel allocations a higher priority cause it is often more work to swap them back in. Signed-off-by: Christian König <[email protected]> Reviewed-by: Roger.He <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu: user BO priority instead of self coding it (v2)Christian König3-79/+5
Keeping groups of BOs on the LRU is to time consuming on command submission. Instead use the newly added BO priority to give a certain eviction order. v2: agd: trivial warning fix Signed-off-by: Christian König <[email protected]> Reviewed-by: Roger.He <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/ttm: add BO priorities for the LRUsChristian König4-27/+52
This way the driver can specify a priority for a BO which has the effect that a BO is only evicted when all other BOs with a lower priority are evicted first. Reviewed-by: Sinclair Yeh <[email protected]> Signed-off-by: Christian König <[email protected]> Reviewed-by: Roger.He <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/ttm: remove allow_errors parameter from ttm_bo_force_list_cleanChristian König1-17/+11
Not allowing errors here is completely pointless and actually dangerous cause trying to continue on an error can cause an endless loop. Reviewed-by: Sinclair Yeh <[email protected]> Signed-off-by: Christian König <[email protected]> Reviewed-by: Roger.He <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu/vi: fix mailbox irq mistakeXiangliang Yu1-3/+3
For virt, freed mailbox irq should be handled in hw fini, not hw init. Correct it. Signed-off-by: Xiangliang Yu <[email protected]> Reviewed-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu: fix reboot failure issue for virtualizationXiangliang Yu1-0/+6
Reboot process will call HW fini functions of IP blocks. For virt, need to send event three before hw fini and send event four after hw fini. Signed-off-by: Xiangliang Yu <[email protected]> Reviewed-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amd/amdgpu: Add PCI info to gca_config debugfsTom St Denis1-1/+7
So we can determine which device the entry is before connecting a display. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu:insert switch buffer only for VM submitMonk Liu1-1/+1
for non-VM submit which is from kernel side, no need to switch buffer at all. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu:Preamble is forbid to be ignored in SRIOVMonk Liu1-1/+2
SR-IOV requires the preamble. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu:set cond_exec polling value to 1 in ring_initMonk Liu2-4/+3
no need to set it per ib_schedule(), hw won't override this polling address. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu:in cntx_ctrl we need insert meta-init for CE/DE(V2)Monk Liu1-1/+9
to support SRIOV preemption. v2: fix emit_frame_size Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu:introduce new flag to identify VM domain for cntx_ctrlMonk Liu2-0/+4
To determine whether the context uses GPUVM or not. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu:implement CE/DE meta-init routinesMonk Liu1-0/+61
those package need to insert into ring buffer for SRIOV case. they are used to let CP do preemption. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu:implement ring_write_multipleMonk Liu1-0/+31
Write multiple dwords to the ring. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu:add META_DATA struct for CSA/SRIOV v2Monk Liu3-0/+120
META-DATA is used in GFX cmd submit, we have two format suit for META-DATA-init, one is legacy and another is for chained-ib preempt, which is used in vulkan UMD. v2: drop use CP version number to judge if chain-ib supports or not, we wait for it mature Signed-off-by: Monk Liu <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu: refine ci uvd dpm code.Rex Zhu1-1/+10
Fix up the powergating logic. Signed-off-by: Rex Zhu <[email protected]> Ack-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu: simplify allocation of scratch regsNils Wallménius5-34/+11
The scratch regs are sequential so there's no need to keep them in an array, we can just return the index of the first free register + the base register. Also change the array of bools for keeping track of the free regs to a bitfield. Reviewed-by: Christian König <[email protected]> Signed-off-by: Nils Wallménius <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu: Refactor flip into prepare submit and submit. (v3)Andrey Grodzovsky2-28/+123
Make pflip atomic friendly. Split the fuinction into whatever can fail part and the actual flip submit part. Call the pre-submit function before atomic states are swapped so in case of error we can fail the IOCTL. v2: Update due to target_vblank code change. Fix identetation. Change return type for amdgpu_crtc_submit_flip to void v3: agd: fix formatting Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu: Switch error code when bo pin fails. (v3)Andrey Grodzovsky1-1/+0
Switching to -ENOMEM resolves a hang in case the driver uses this function in atomic code path. v2: Update commit message. v3: Remove forcing -EINVAL in case of amdgpu_bo_pin fail since there is no apparent reason for not just passing through the the return value. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by Harry Wentland <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu/gfx8: fix bugon.cocci warningsJulia Lawall1-2/+1
Use BUG_ON instead of a if condition followed by BUG. Generated by: scripts/coccinelle/misc/bugon.cocci Reviewed-by: Christian König <[email protected]> Reviewd-by: Xiangliang.Yu <[email protected]> CC: Xiangliang Yu <[email protected]> Signed-off-by: Julia Lawall <[email protected]> Signed-off-by: Fengguang Wu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu: use the num_rings variable for checking vce ringsAlex Deucher1-2/+2
Difference families may have different numbers of rings. Use the variable rather than a hardcoded number. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amd/amdgpu: fix locking in bo creation error pathNicolai Hähnle1-1/+2
Unlock the resv lock only if we were the ones to lock it in the first place. Signed-off-by: Nicolai Hähnle <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amd/amdgpu: lock reservation object while creating shadow boNicolai Hähnle1-0/+9
ttm_bo_init checks that the reservation object is locked. This is the caller's responsibility when resv != NULL. Otherwise, the inline reservation object of the newly allocated buffer is used and must explicitly be locked. Uninterruptible w/w locks without an acquire context are always successful. v2: use ww_mutex_lock Signed-off-by: Nicolai Hähnle <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> (v1) Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu: fix typo of CGTSHuang Rui1-1/+1
Fixes: 9e8590861e9 ('drm/amdgpu: add parse clock gating state') Reported-by: Tom StDenis <[email protected]> Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu: do not reset gpu for virtualizationXiangliang Yu1-0/+3
Current amdgpu reset process only works on bare-metal and for SRIOV many inside it need re-work to adapt to vf device. This is a temporary workaround to skip gpu reset. Signed-off-by: Monk Liu <[email protected]> Signed-off-by: Xiangliang Yu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu/virt: enable virtual displayXiangliang Yu1-0/+4
Virtual display is default setting for virtualization, enable it. Signed-off-by: Xiangliang Yu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu/vi: add support virtualizationXiangliang Yu1-2/+32
Call VI virtualization functions if device is Vf. Signed-off-by: Xiangliang Yu <[email protected]> Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu: request/release full gpu access if device is vfXiangliang Yu2-1/+15
For gpu vf device, first need to request full gpu access before accessing gpu registers, and release full gpu access after the access is done. Signed-off-by: Xiangliang Yu <[email protected]> Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu/virt: implement VI virt operation interfacesXiangliang Yu4-1/+651
VI has asic specific virt support, which including mailbox and golden registers init. Signed-off-by: Xiangliang Yu <[email protected]> Signed-off-by: Monk Liu <[email protected]> Signed-off-by: shaoyunl <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu/virt: add high level interfaces for virtXiangliang Yu2-5/+85
Add high level interfaces that is not relate to specific asic. So asic files just need to implement the interfaces to support virtualization. Signed-off-by: Xiangliang Yu <[email protected]> Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu/virt: use kiq to access registers (v2)Xiangliang Yu4-0/+75
For virtualization, it is must for driver to use KIQ to access registers when it is out of GPU full access mode. v2: agd: rebase Signed-off-by: Xiangliang Yu <[email protected]> Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu/virt: add runtime flagXiangliang Yu1-0/+4
Add new flag to define gpu runtime that is out of full gpu access. Signed-off-by: Xiangliang Yu <[email protected]> Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu/gfx8: implement emit_rreg/wreg functionXiangliang Yu2-0/+38
Implement emit_rreg/wreg function for kiq ring. Signed-off-by: Xiangliang Yu <[email protected]> Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu/ring: add two interfaces to support r/w registers with kiqXiangliang Yu2-0/+4
During virtual runtime, need to send command to kiq ring to read/write GPU registers. Add two interface to support the two actions. Signed-off-by: Xiangliang Yu <[email protected]> Signed-off-by: Monk Linu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu:invoke CSA functions (v2)Monk Liu3-0/+40
Make sure the CSA is mapped. v2: agd: rebase. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu:add new file for SRIOVMonk Liu3-1/+98
for SRIOV usage, CSA is only used per device and each VM will map on it. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu:new field members for SRIOVMonk Liu2-0/+8
and implement CSA functions in this file Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amd/amdgpu: add check that shadow page tables are GPU-accessibleNicolai Hähnle1-3/+6
Skip amdgpu_gem_va_update_vm otherwise. Also clean up the check for the non-shadow page tables using the new helper function. This fixes a crash with the stack trace: amdgpu_gem_va_update_vm -> amdgpu_vm_update_page_directory -> amdgpu_ttm_bind -> amdgpu_gtt_mgr_alloc v2: actually check bo->shadow instead of just checking bo twice Signed-off-by: Nicolai Hähnle <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amd/amdgpu: add check that shadow page directory is GPU-accessibleNicolai Hähnle1-3/+8
Skip amdgpu_gem_va_update_vm when shadow the page directory is swapped out. Clean up the check for non-shadow BOs as well using the new helper function. This fixes a crash with the stack trace: amdgpu_gem_va_update_vm -> amdgpu_vm_update_page_directory -> amdgpu_ttm_bind -> amdgpu_gtt_mgr_alloc Signed-off-by: Nicolai Hähnle <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amd/amdgpu: add amdgpu_bo_gpu_accessible helper functionNicolai Hähnle1-0/+9
Signed-off-by: Nicolai Hähnle <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amd/amdgpu: move eviction counting to amdgpu_bo_move_notifyNicolai Hähnle2-4/+4
This catches evictions of shadow page tables from the GART. Since shadow page tables are always stored in system memory, amdgpu_bo_move is never called for them. This fixes a crash during command submission that occurs when only a shadow page table and no other BOs were evicted since the last submission. Fixes: 1baa439fb2f4e586 ("drm/amdgpu: allocate shadow for pd/pt bo V2") Signed-off-by: Nicolai Hähnle <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/ttm: add evict parameter to ttm_bo_driver::move_notifyNicolai Hähnle10-8/+22
Ensure that the driver can listen to evictions even when they don't take the path through ttm_bo_driver::move. This is crucial for amdgpu, which relies on an eviction counter to skip re-binding page tables when possible. Signed-off-by: Nicolai Hähnle <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu: refine vce3.0 initialize.Rex Zhu2-18/+35
1. disable vce cg when vce hw initialize. 2. initizlize vce clock to 10KHz fo dgpu, so no need to set bypass clock to vce. Change-Id: I934c2c4820cc95c1bfa2fa41ff0f40a0d3cd1c40 Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu: extend profiling mode.Rex Zhu6-26/+154
in profiling mode, powerplay will fix power state as stable as possible.and disable gfx cg and LBPW feature. profile_standard: as a prerequisite, ensure power and thermal sustainable, set clocks ratio as close to the highest clock ratio as possible. profile_min_sclk: fix mclk as profile_normal, set lowest sclk profile_min_mclk: fix sclk as profile_normal, set lowest mclk profile_peak: set highest sclk and mclk, power and thermal not sustainable profile_exit: exit profile mode. enable gfx cg/lbpw feature. Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amd/powerplay: refine DIDT feature in Powerplay.Rex Zhu2-49/+179
Updating SQ DIDT settings and block mask so SQ uses PCC on Polaris11. Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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