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2022-08-03pinctrl: amd: Fix an unused variableMario Limonciello1-1/+0
`char *output_enable` is no longer used once switching to unicode output. Fixes: e8129a076a50 ("pinctrl: amd: Use unicode for debugfs output") Reported-by: kernel test robot <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-26dt-bindings: pinctrl: mt8186: Add and use drive-strength-microampAllen-KH Cheng1-26/+3
Commit e5fabbe43f3f ("pinctrl: mediatek: paris: Support generic PIN_CONFIG_DRIVE_STRENGTH_UA") added support for using drive-strength-microamp instead of mediatek,drive-strength-adv. Similarly to the mt8192 and mt8195, there's no user of property 'mediatek,drive-strength-adv', hence removing it is safe. Fixes: 338e953f1bd1 ("dt-bindings: pinctrl: mt8186: add pinctrl file and binding document") Signed-off-by: Allen-KH Cheng <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-26dt-bindings: pinctrl: mt8186: Add gpio-line-names propertyAllen-KH Cheng1-0/+2
Add the 'gpio-line-names' property to mt8186-pinctrl, as this will be used in devicetrees to describe pin names. Signed-off-by: Allen-KH Cheng <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Acked-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-26ARM: dts: imxrt1170-pinfunc: Add pinctrl binding headerJesse Taube1-0/+1561
Add binding header for i.MXRT1170 pinctrl device tree. Cc: Giulio Benetti <[email protected]> Signed-off-by: Jesse Taube <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-26pinctrl: amd: Use unicode for debugfs outputMario Limonciello1-58/+56
The output is currently split across two lines making it more difficult to parse unless the newlines are removed between pins or it's read in by a parser like Libreoffice Calc or Google docs. To make it easier to follow to the naked eye in a terminal window: * drop the newline in the middle of pin definitions * shorten all output using unicode characters * align all pipe delimitters * output the same phrase even for disabled functions (but with a ∅ character) Signed-off-by: Mario Limonciello <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-26pinctrl: amd: Fix newline declaration in debugfs outputMario Limonciello1-1/+1
Currently the debugfs output for pinctrl-amd puts the first line combined with "GPIO bank". This makes it a little harder to process as the file needs to be manually corrected for the mistake. Change this to be a new line character instead. Signed-off-by: Mario Limonciello <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-26pinctrl: at91: Fix typo 'the the' in commentSlark Xiao1-1/+1
Replace 'the the' with 'the' in the comment. Signed-off-by: Slark Xiao <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-26dt-bindings: pinctrl: st,stm32: Correct 'resets' property nameRob Herring1-2/+2
The correct property name for the reset binding is 'resets', not 'reset'. Assuming actual users are correct, this error didn't show up due to missing 'additionalProperties: false'. Fix the name and add missing 'additionalProperties'. Signed-off-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-26pinctrl: mvebu: Missing a blank line after declarations.Xin Gao1-0/+10
Missing a blank line after declarations. Signed-off-by: Xin Gao <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-26pinctrl: qcom: Add SM6375 TLMM driverKonrad Dybcio3-0/+1554
Add a driver to control the TLMM block on SM6375. This is an adapted version of msm-5.4's pinctrl-blair driver. Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-26dt-bindings: pinctrl: Add DT schema for SM6375 TLMMKonrad Dybcio1-0/+158
Document the TLMM driver for SM6375. Signed-off-by: Konrad Dybcio <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-18dt-bindings: pinctrl: mt8195: Use drive-strength-microamp in examplesAngeloGioacchino Del Regno1-1/+1
The property mediatek,drive-strength-adv was deprecated: change the example for i2c0-pins to use drive-strength-microamp. Fixes: b6d9af2c6b69 ("dt-bindings: pinctrl: mt8195: Add and use drive-strength-microamp") Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Acked-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-18Revert "pinctrl: qcom: spmi-gpio: make the irqchip immutable"Linus Walleij1-12/+10
This reverts commit 7542766e78fc374d81d8c2db214c4b4308645277. It was noted during follow-up that the approach is incorrect. Signed-off-by: Linus Walleij <[email protected]>
2022-07-18pinctrl: imx93: Add MODULE_DEVICE_TABLE()Fabio Estevam1-0/+1
Pass MODULE_DEVICE_TABLE() so that module autoloading can work. This also aligns with the other i.MX8 pinctrl drivers. Signed-off-by: Fabio Estevam <[email protected]> Reviewed-by: Jacky Bai <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-18pinctrl: sunxi: Add driver for Allwinner D1Samuel Holland5-5/+863
This SoC contains a pinctrl with a new register layout. Use the variant parameter to set the right register offsets. This pinctrl also increases the number of functions per pin from 8 to 16, taking advantage of all 4 bits in the mux config field (so far, only functions 0-8 and 14-15 are used). This increases the maximum possible number of functions. Reviewed-by: Heiko Stuebner <[email protected]> Tested-by: Heiko Stuebner <[email protected]> Signed-off-by: Samuel Holland <[email protected]> Reviewed-by: Andre Przywara <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-18pinctrl: sunxi: Make some layout parameters dynamicSamuel Holland2-18/+29
Starting with the D1/D1s/T113 SoC, Allwinner changed the layout of the pinctrl registers. This new layout widens the drive level field, which affects the pull register offset and the overall bank size. In order to support multiple register layouts, some of the layout parameters need to be set based on the pinctrl variant. This requires passing the pinctrl struct pointer to the register/offset calculation functions. Reviewed-by: Jernej Skrabec <[email protected]> Reviewed-by: Heiko Stuebner <[email protected]> Tested-by: Heiko Stuebner <[email protected]> Signed-off-by: Samuel Holland <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-18pinctrl: sunxi: Refactor register/offset calculationSamuel Holland2-123/+89
Starting with the D1/D1s/T113 SoC, Allwinner changed the layout of the pinctrl registers. This new layout widens the drive level field, which affects the pull register offset and the overall bank size. As a first step to support this, combine the register and offset calculation functions, and refactor the math to depend on one constant for field widths instead of three. This minimizes the code size impact of making some of the factors dynamic. While rewriting these functions, move them to the implementation file, since that is the only file where they are used. And make the comment more generic, without mentioning specific offsets/sizes. The callers are updated to expect a shifted mask, and to use consistent terminology (reg/shift/mask/val). Reviewed-by: Heiko Stuebner <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Tested-by: Heiko Stuebner <[email protected]> Signed-off-by: Samuel Holland <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-18pinctrl: sunxi: Support the 2.5V I/O bias modeSamuel Holland5-2/+20
H616 and newer SoCs feature a 2.5V I/O bias mode in addition to the 1.8V and 3.3V modes. This mode is entered by selecting the 3.3V level and disabling the "withstand function". H616 supports this capability on its main PIO only. A100 supports this capability on both its PIO and R-PIO. Reviewed-by: Jernej Skrabec <[email protected]> Tested-by: Heiko Stuebner <[email protected]> Signed-off-by: Samuel Holland <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-18pinctrl: sunxi: Add I/O bias setting for H6 R-PIOSamuel Holland2-3/+5
H6 requires I/O bias configuration on both of its PIO devices. Previously it was only done for the main PIO. The setting for Port L is at bit 0, so the bank calculation needs to account for the pin base. Otherwise the wrong bit is used. Fixes: cc62383fcebe ("pinctrl: sunxi: Support I/O bias voltage setting on H6") Reviewed-by: Jernej Skrabec <[email protected]> Tested-by: Heiko Stuebner <[email protected]> Signed-off-by: Samuel Holland <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-18dt-bindings: pinctrl: Add compatible for Allwinner D1Samuel Holland1-0/+13
D1 contains a pin controller similar to previous SoCs, but with some register layout changes. It includes 6 interrupt-capable pin banks. Acked-by: Krzysztof Kozlowski <[email protected]> Tested-by: Heiko Stuebner <[email protected]> Signed-off-by: Samuel Holland <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-18pinctrl: qcom-pmic-gpio: add support for PMP8074Robert Marko1-0/+2
PMP8074 has 12 GPIO-s with holes on GPIO1 and GPIO12. Signed-off-by: Robert Marko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-18dt-bindings: pinctrl: qcom,pmic-gpio: add PMP8074Robert Marko1-0/+3
Document the compatible for PMP8074 which has 12 GPIO-s with holes at GPIO1 and GPIO12. Signed-off-by: Robert Marko <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-18pinctrl: qcom: spmi-gpio: Add pm8226 compatibilityDominik Kobinski1-0/+1
Add support for pm8226 SPMI GPIOs. The PMIC features 8 GPIOs, with no holes inbetween. Reviewed-by: Bjorn Andersson <[email protected]> Suggested-by: Ivaylo Ivanov <[email protected]> Signed-off-by: Dominik Kobinski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-18pinctrl: core: Use device_match_of_node() helperAndy Shevchenko1-1/+1
Instead of open coding, use device_match_of_node() helper. Signed-off-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-18dt-bindings: pinctrl: mt8195: Add gpio-line-names propertyAngeloGioacchino Del Regno1-0/+2
Add the 'gpio-line-names' property to mt8195-pinctrl, as this will be used in devicetrees to describe pin names. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Nícolas F. R. A. Prado <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-18dt-bindings: pinctrl: mt8195: Add and use drive-strength-microampAngeloGioacchino Del Regno1-25/+2
As was already done for MT8192 in commit b52e695324bb ("dt-bindings: pinctrl: mt8192: Add drive-strength-microamp"), replace the custom mediatek,drive-strength-adv property with the standardized pinconf 'drive-strength-microamp' one. Similarly to the mt8192 counterpart, there's no user of property 'mediatek,drive-strength-adv', hence removing it is safe. Fixes: 69c3d58dc187 ("dt-bindings: pinctrl: mt8195: Add mediatek,drive-strength-adv property") Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Nícolas F. R. A. Prado <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-18dt-bindings: pinctrl: mt8195: Fix name for mediatek,rsel-resistance-in-si-unitAngeloGioacchino Del Regno1-5/+5
When this property was introduced, it contained underscores, but the actual code wants dashes. Change it from mediatek,rsel_resistance_in_si_unit to mediatek,rsel-resistance-in-si-unit. Fixes: 91e7edceda96 ("dt-bindings: pinctrl: mt8195: change pull up/down description") Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Nícolas F. R. A. Prado <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-18pinctrl: at91: remove #ifdef CONFIG_PMClaudiu Beznea1-7/+1
Remove #ifdef CONFIG_PM and use pm_ptr() macro instead. Signed-off-by: Claudiu Beznea <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-18pinctrl: at91-pio4: remove #ifdef CONFIG_PM_SLEEPClaudiu Beznea1-6/+1
Remove #ifdef CONFIG_PM_SLEEP and use pm_sleep_ptr() macro instead. Signed-off-by: Claudiu Beznea <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-11dt-bindings: pinctrl: sunxi: allow vcc-pi-supplyAndre Przywara1-1/+1
The Allwinner H616 SoC contains a VCC_PI pin, which supplies the voltage for GPIO port I. Extend the range of supply port names to include vcc-pi-supply to cover that. Signed-off-by: Andre Przywara <[email protected]> Acked-by: Rob Herring <[email protected]> Acked-by: Samuel Holland <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-11dt-bindings: pinctrl: sunxi: Make interrupts optionalAndre Przywara1-3/+13
The R_PIO pinctrl device on the Allwinner H616 SoC does not have an interrupt (it features only two pins). However the binding requires at least naming one upstream interrupt, plus the #interrupt-cells and interrupt-controller properties. Drop the unconditional requirement for the interrupt properties, and make them dependent on being not this particular pinctrl device. Signed-off-by: Andre Przywara <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Samuel Holland <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-11pinctrl: qcom: Add pinctrl driver for MSM8909Stephan Gerhold3-0/+965
Make it possible to control pins using the TLMM block in the MSM8909 SoC by adding the necessary definitions for GPIOs, groups and functions. The driver is originally taken from the msm-4.9 release [1] from Qualcomm, but cleaned up significantly with several fixes and clarifications. [1]: https://git.codelinaro.org/clo/la/kernel/msm-4.9/-/blob/LF.UM.8.7-22500-8x09.0/drivers/pinctrl/qcom/pinctrl-msm8909.c Signed-off-by: Stephan Gerhold <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-11dt-bindings: pinctrl: Add DT schema for qcom,msm8909-tlmmStephan Gerhold1-0/+152
Document the "qcom,msm8909-tlmm" compatible for the TLMM/pin control block in the MSM8909 SoC, together with the allowed GPIOs and functions. Signed-off-by: Stephan Gerhold <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-11pinctrl: starfive: Serialize adding groups and functionsJianlong Huang1-0/+5
The pinctrl dt_node_to_map method may be called in parallel which leads us to call pinconf_generic_add_group and pinconf_generic_add_function in parallel. This is not supported though and leads to errors, so add a mutex to serialize these calls. Signed-off-by: Jianlong Huang <[email protected]> Signed-off-by: Emil Renner Berthing <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-10Merge tag 'renesas-pinctrl-for-v5.20-tag2' of ↵Linus Walleij12-6/+5610
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.20 (take two) - Add support for the RZ/V2M and R-Car V4H SoCs, - Miscellaneous fixes and improvements.
2022-07-10pinctrl: amd: Remove contact informationBasavaraj Natikar1-2/+0
Remove contact information. Signed-off-by: Basavaraj Natikar <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-10pinctrl: amd: Don't save/restore interrupt status and wake status bitsBasavaraj Natikar1-2/+9
Saving/restoring interrupt and wake status bits across suspend can cause the suspend to fail if an IRQ is serviced across the suspend cycle. Signed-off-by: Mario Limonciello <[email protected]> Signed-off-by: Basavaraj Natikar <[email protected]> Fixes: 79d2c8bede2c ("pinctrl/amd: save pin registers over suspend/resume") Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-10pinctrl: amd: Use devm_platform_get_and_ioremap_resourceBasavaraj Natikar1-8/+3
Use devm_platform_get_and_ioremap_resource() to simplify code. Signed-off-by: Basavaraj Natikar <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-10Merge tag 'intel-pinctrl-v5.20-1' of ↵Linus Walleij10-54/+471
gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.20-1 * Update MAINTAINERS to set the Intel pin control status to Supported * Switch Intel pin control drivers to use struct pingroup The following is an automated git shortlog grouped by driver: baytrail: - Switch to to embedded struct pingroup cherryview: - Switch to to embedded struct pingroup intel: - Add Intel Meteor Lake pin controller support - Drop no more used members of struct intel_pingroup - Switch to to embedded struct pingroup - Embed struct pingroup into struct intel_pingroup lynxpoint: - Switch to to embedded struct pingroup MAINTAINERS: - Update Intel pin control to Supported Merge branch 'ib-v5.20-amd-pinctrl': - Merge branch 'ib-v5.20-amd-pinctrl' merrifield: - Switch to to embedded struct pingroup
2022-07-10pinctrl: qcom: spmi-gpio: make the irqchip immutableRobert Marko1-10/+12
Commit 6c846d026d49 ("gpio: Don't fiddle with irqchips marked as immutable") added a warning to indicate if the gpiolib is altering the internals of irqchips. Following this change the following warning is now observed for the SPMI PMIC pinctrl driver: gpio gpiochip1: (200f000.spmi:pmic@0:gpio@c000): not an immutable chip, please consider fixing it! Fix this by making the irqchip in the SPMI PMIC pinctrl driver immutable. Signed-off-by: Robert Marko <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Tested-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-07-05pinctrl: renesas: r8a779g0: Add missing MODSELx for AVBxKuninori Morimoto1-28/+30
AVB1 needs MODSEL6, AVB2 needs MODSEL5 settings. This patch adds missing MODSELx settings for the affected pins. Signed-off-by: Kuninori Morimoto <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2022-07-05pinctrl: renesas: r8a779g0: Add missing MODSELx for TSN0Kuninori Morimoto1-10/+13
TSN0 needs MODSEL4 settings. This patch adds missing MODSELx settings for the affected pins. Signed-off-by: Kuninori Morimoto <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2022-07-05pinctrl: renesas: r8a779g0: Add missing ERROROUTC_AKuninori Morimoto1-3/+4
This patch adds missing ERROROUTC_A settings. Current existing ERROROUTC should be _B, this patch tidies it up. Signed-off-by: Kuninori Morimoto <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2022-07-05pinctrl: renesas: r8a779g0: Add missing PWMKuninori Morimoto1-56/+84
R-Car V4H has PWM/PWM_A/PWM_B, but current PFC setting is mixed. This patch adds missing PWM settings, and tidies these up. According to Document, GP3_14 Function4 is PWM2_A, but we can't select it at P1SR3[27:24]. This patch just ignore it for now. Signed-off-by: Kuninori Morimoto <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2022-07-05pinctrl: renesas: r8a779g0: Add missing FlexRayKuninori Morimoto1-2/+4
This patch adds missing FlexRay pins. Because Document (Rev.0.51) has 2x FXR_TXENA/B pin with no suffix (_A, _B), this patch names them as _X. Signed-off-by: Kuninori Morimoto <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2022-07-05pinctrl: renesas: r8a779g0: Add missing TPU0TOx_AKuninori Morimoto1-8/+51
This patch adds missing TPU0TOx_A. Signed-off-by: Kuninori Morimoto <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2022-07-05pinctrl: renesas: r8a779g0: Add missing CANFD5_BKuninori Morimoto1-3/+17
This patch adds missing CANFD5_B. Signed-off-by: Kuninori Morimoto <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2022-07-05pinctrl: renesas: r8a779g0: Add missing SCIF1_XKuninori Morimoto1-8/+43
This patch adds missing SCIF1_X. Because Document (Rev.0.51) has 2x SCIF1 with no suffix (_A, _B), this patch names it as _X. Signed-off-by: Kuninori Morimoto <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2022-07-05pinctrl: renesas: r8a779g0: Add missing SCIF3Kuninori Morimoto1-18/+53
R-Car V4H has SCIF3 and SCIF3_A, but current PFC setting is mixed. This patch cleans up SCIF3/SCIF3_A, based on Rev.0.51. Signed-off-by: Kuninori Morimoto <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2022-07-05pinctrl: renesas: r8a779g0: Add missing HSCIF1_XKuninori Morimoto1-8/+45
This patch adds missing HSCIF1. Because Document (Rev.0.51) has 2x HSCIF1 with no suffix (_A, _B), this patch names it as _X. Signed-off-by: Kuninori Morimoto <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
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