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2013-07-01drm/i915: Remove duplicated WaForceL3Serialization:vlvVille Syrjälä1-4/+0
No need to apply WaForceL3Serialization:vlv twice. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Damien Lespiau <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-07-01drm/i915: don't scream into dmesg when a modeset failsDaniel Vetter1-2/+2
There are legit cases, e.g. when userspace asks for something impossible. So tune it down to debug output like we do with all other userspace-triggerable warnings. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66111#c5 Reviewed-by: Chris Wilson <[email protected]> [danvet: Rebased.] Signed-off-by: Daniel Vetter <[email protected]>
2013-07-01drm/i915: Fix up sdvo hpd pins for i965g/gmDaniel Vetter2-18/+8
Bspec seems to be full of lies, at least it disagress with reality: Two systems corrobated that SDVO hpd bits are the same as on gen3. v2: Update comment a bit. Cc: Arthur Ranyan <[email protected]> Cc: Chris Wilson <[email protected]> Tested-by: Chris Wilson <[email protected]> Reported-and-tested-by: Alex Fiestas <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=58405 Cc: [email protected] Acked-by: Chris Wilson <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-07-01drm/i915: Introduce an HAS_IPS() macroDamien Lespiau3-3/+5
Follow the trend and don't code conditions with platforms but with features. Signed-off-by: Damien Lespiau <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-07-01drm/i915: fix build warning on format specifier mismatchJani Nikula1-1/+1
drivers/gpu/drm/i915/i915_gem.c: In function ‘i915_gem_object_bind_to_gtt’: drivers/gpu/drm/i915/i915_gem.c:3002:3: warning: format ‘%ld’ expects argument of type ‘long int’, but argument 5 has type ‘size_t’ [-Wformat] v2: Use %zu instead of %d. Two char patch, and 100% wrong. (Ville) Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-07-01drm/i915: tune down DIDL warning about too many outputsDaniel Vetter1-4/+4
Nothing the user (nor we) really can do about this, but upsets a nice quiet boot. Note that this happens mostly on SDVs where OEMs obviously haven't had a chance yet to appropriately trim the output list. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=65988 Reviewed-by: Damien Lespiau <[email protected]> [danvet: Amend commit message a bit to clarify a question from Paulo.] Signed-off-by: Daniel Vetter <[email protected]>
2013-07-01drm/i915: make compact dma scatter lists creation work with SWIOTLB backend.Konrad Rzeszutek Wilk1-3/+12
Git commit 90797e6d1ec0dfde6ba62a48b9ee3803887d6ed4 ("drm/i915: create compact dma scatter lists for gem objects") makes certain assumptions about the under laying DMA API that are not always correct. On a ThinkPad X230 with an Intel HD 4000 with Xen during the bootup I see: [drm:intel_pipe_set_base] *ERROR* pin & fence failed [drm:intel_crtc_set_config] *ERROR* failed to set mode on [CRTC:3], err = -28 Bit of debugging traced it down to dma_map_sg failing (in i915_gem_gtt_prepare_object) as some of the SG entries were huge (3MB). That unfortunately are sizes that the SWIOTLB is incapable of handling - the maximum it can handle is a an entry of 512KB of virtual contiguous memory for its bounce buffer. (See IO_TLB_SEGSIZE). Previous to the above mention git commit the SG entries were of 4KB, and the code introduced by above git commit squashed the CPU contiguous PFNs in one big virtual address provided to DMA API. This patch is a simple semi-revert - were we emulate the old behavior if we detect that SWIOTLB is online. If it is not online then we continue on with the new compact scatter gather mechanism. An alternative solution would be for the the '.get_pages' and the i915_gem_gtt_prepare_object to retry with smaller max gap of the amount of PFNs that can be combined together - but with this issue discovered during rc7 that might be too risky. Reported-and-Tested-by: Konrad Rzeszutek Wilk <[email protected]> CC: Chris Wilson <[email protected]> CC: Imre Deak <[email protected]> CC: Daniel Vetter <[email protected]> CC: David Airlie <[email protected]> CC: <[email protected]> Signed-off-by: Konrad Rzeszutek Wilk <[email protected]> Cc: [email protected] Signed-off-by: Daniel Vetter <[email protected]>
2013-07-01drm/i915: Fix PCH detect with multiple ISA bridges in VMRui Guo1-2/+16
In some virtualized environments (e.g. XEN), there is irrelevant ISA bridge in the system. To work reliably, we should scan trhough all the ISA bridge devices and check for the first match, instead of only checking the first one. Signed-off-by: Rui Guo <[email protected]> [danvet: Fixup conflict with the num_pch_pll removal. And add subsystem header to the commit message headline.] Signed-off-by: Daniel Vetter <[email protected]>
2013-07-01drm/i915: rename intel_dp_destroy to intel_dp_connector_destroyPaulo Zanoni1-2/+2
Because it's the function that destroys the connector, not the encoder. And we already have intel_dp_encoder_destroy. This has annoyed me for a long time. Signed-off-by: Paulo Zanoni <[email protected]> Reviewed-by: Zoltan Nyul <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-07-01Merge branch 'drm-nouveau-next' of ↵Dave Airlie138-5449/+7058
git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next - Various fixes that make surviving concurrent piglit more possible. - Buffer object deletion no longer synchronous - Context/register initialisation updates that have been reported to solve some stability issues (particularly on some problematic GF119 chips) - Kernel side support for VP2 video decoding engines * 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (44 commits) drm/nvd0-/disp: handle case where display engine is missing/disabled drm/gr/nvc0-: merge nvc0/nve0 ucode, and use cpp instead of m4 drm/nouveau/bsp/nv84: initial vp2 engine implementation drm/nouveau/vp/nv84: initial vp2 engine implementation drm/nouveau/core: xtensa engine base class implementation drm/nouveau/vdec: fork vp3 implementations from vp2 drm/nouveau/core: move falcon class to engine/ drm/nouveau/kms: don't fail if there's no dcb table entries drm/nouveau: remove limit on gart drm/nouveau/vm: perform a bar flush when flushing vm drm/nvc0/gr: cleanup register lists, and add nvce/nvcf to switches drm/nvc8/gr: update initial register/context values drm/nvc4/gr: update initial register/context values drm/nvc1/gr: update initial register/context values drm/nvc3/gr: update initial register/context values drm/nvc0/gr: update initial register/context values drm/nvd9/gr: update initial register/context values drm/nve4/gr: update initial register/context values drm/nvc0-/gr: bump maximum gpc/tpc limits drm/nvf0/gr: initial register/context setup ...
2013-07-01drm/nvd0-/disp: handle case where display engine is missing/disabledMaarten Lankhorst6-7/+17
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/gr/nvc0-: merge nvc0/nve0 ucode, and use cpp instead of m4Ben Skeggs14-2587/+1270
No code changes, proven by envyas producing identical binaries. Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nouveau/bsp/nv84: initial vp2 engine implementationIlia Mirkin3-14/+16
Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nouveau/vp/nv84: initial vp2 engine implementationIlia Mirkin4-14/+17
Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nouveau/core: xtensa engine base class implementationIlia Mirkin3-0/+209
Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nouveau/vdec: fork vp3 implementations from vp2Ilia Mirkin6-14/+204
Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nouveau/core: move falcon class to engine/Ben Skeggs11-24/+21
Not really "core" per-se. About to merge Ilia's work adding another similar class for the VP2 xtensa engines, so, seems like a good time to move all these to engine/. Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nouveau/kms: don't fail if there's no dcb table entriesBen Skeggs2-7/+9
Fixes module not loading on Tesla K20. Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nouveau: remove limit on gartMaarten Lankhorst1-5/+0
Most graphics cards nowadays have a multiple of this limit as their vram, so limiting GART doesn't seem to make much sense. Signed-off-by: Maarten >Lnkhorst <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nouveau/vm: perform a bar flush when flushing vmMaarten Lankhorst2-0/+8
Appears to fix the regression from "drm/nvc0/vm: handle bar tlb flushes internally". nvidia always seems to do this flush after writing values. Signed-off-by: Maarten Lankhorst <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nvc0/gr: cleanup register lists, and add nvce/nvcf to switchesBen Skeggs6-600/+344
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nvc8/gr: update initial register/context valuesBen Skeggs6-10/+74
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nvc4/gr: update initial register/context valuesBen Skeggs6-9/+62
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nvc1/gr: update initial register/context valuesBen Skeggs6-35/+80
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nvc3/gr: update initial register/context valuesBen Skeggs6-12/+112
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nvc0/gr: update initial register/context valuesBen Skeggs6-544/+1042
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nvd9/gr: update initial register/context valuesBen Skeggs6-74/+482
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nve4/gr: update initial register/context valuesBen Skeggs4-157/+31
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nvc0-/gr: bump maximum gpc/tpc limitsBen Skeggs1-2/+4
Needed for GK110, separate commit to catch any unexpected breaks to other parts of the code. Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nvf0/gr: initial register/context setupBen Skeggs6-482/+1057
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nve7/gr: update initial register/context valuesBen Skeggs4-3/+12
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nve6/gr: update initial register/context valuesBen Skeggs4-113/+383
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nouveau: delay busy bo vma removal until fence signalsBen Skeggs4-15/+108
As opposed to an explicit wait. Allows userspace to not stall waiting on buffer deletion. Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nouveau/vm: make each vma take a reference on its parent vmBen Skeggs1-1/+4
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nouveau/core: remove nouveau_mm.mutex, no more usersBen Skeggs3-5/+2
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nouveau/vm: take subdev mutex, not the mm, protects against race with ↵Ben Skeggs1-16/+17
vm/nvc0 nvc0_vm_flush() accesses the pgd list, which will soon be able to race with vm_unlink() during channel destruction. Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nvc0/vm: handle bar tlb flushes internallyBen Skeggs3-34/+28
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nv50-/vm: take mutex rather than irqsave spinlockBen Skeggs2-10/+4
These operations can take quite some time, and we really don't want to have to hold a spinlock for too long. Now that the lock ordering for vm and the gr/nv84 hw bug workaround has been reversed, it's possible to use a mutex here. Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nv50/vm: remove explicit vm knowledge from enginesBen Skeggs9-66/+31
This reverses the lock ordering between VM and gr/nv84:nvc0. Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nv50/vm: handle bar tlb flushes internallyBen Skeggs3-5/+13
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nvc0/gr: port mp trap handling from calim's kepler codeBen Skeggs1-6/+38
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nve0/gr: attempt to resume after sm trapsBen Skeggs1-16/+6
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nve0/gr: s/tp/tpc/Ben Skeggs1-26/+27
NVIDIA's name... Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nve0/fifo: create our playlists up-front, at startupBen Skeggs1-14/+14
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nva3/clk: minor improvements to fractional N calculationBen Skeggs1-3/+11
Helps us to get identical numbers to the binary driver for (at least) Kepler memory PLLs, and fixes a rounding error. Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nouveau/fb: initialise vram controller as pfb sub-objectBen Skeggs45-733/+1313
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nouveau/clk: change init ordering, no longer needed by devinitBen Skeggs1-2/+2
And, will depend on FB/VOLT/DAEMON being ready when it gets initialised so that it can set/restore clocks. Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nouveau/devinit: move simple pll setting routines to devinitBen Skeggs24-487/+628
These are pretty much useless for reclocking purposes. Lets make it clearer what they're for and move them to DEVINIT to signify they're for the very simple PLL setting requirements of running the init tables. Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nouveau: pass generic subdev to calculation routinesBen Skeggs7-18/+17
Signed-off-by: Ben Skeggs <[email protected]>
2013-07-01drm/nve0/ce: stub interrupt handlerBen Skeggs2-0/+17
Signed-off-by: Ben Skeggs <[email protected]>
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