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2017-03-29drm/amdgpu:use clear_ring to clr RBMonk Liu3-1/+3
In resume routine, we need clr RB prior to the ring test of engine, otherwise some engine hang duplicated during GPU reset. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:imple ring clearMonk Liu1-0/+7
we can use it clear ring buffer instead of fullfill 0, which is not correct for engine Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:alloc mqd backupMonk Liu2-0/+11
this is required for restoring the mqds after GPU reset. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Xiangliang Yu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:new field in_reset introduced for gfxMonk Liu1-0/+1
use it to seperate driver load and gpu reset/resume because gfx IP need different approach for different hw_init trigger source Signed-off-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:RUNTIME flag should clr laterMonk Liu1-3/+1
this flag will get cleared by request gpu access Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Xiangliang Yu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:use work instead of delay-workMonk Liu2-20/+18
no need to use a delay work since we don't know how much time hypervisor takes on FLR, so just polling and waiting in a work. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Xiangliang Yu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:no kiq for mailbox registers accessMonk Liu1-16/+16
Use no kiq version reg access due to: 1) better performance 2) INTR context consideration (some routine in mailbox is in INTR context e.g.xgpu_vi_mailbox_rcv_irq) Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Xiangliang Yu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:Refine handshake of mailboxKen Xue1-1/+23
Signed-off-by: Ken Xue <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Xiangliang Yu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:impl RREG32 no kiq versionMonk Liu2-13/+20
some registers are PF & VF copy, and we can safely use mmio method to access them. and sometime we are forbid to use kiq to access registers for example in INTR context. we need a MACRO that always disable KIQ for regs accessing Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Xiangliang Yu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:use MACRO like other placesMonk Liu1-4/+2
Change-Id: Ica8f86577a50d817119de4b4fb95068dc72652a9 Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: simplify reservation handling during buffer creationNicolai Hähnle1-13/+4
By using ttm_bo_init_reserved instead of the manual initialization of the reservation object, the reservation lock will be properly unlocked and destroyed when the TTM BO initialization fails. Actual deadlocks caused by the missing unlock should have been fixed by "drm/ttm: never add BO that failed to validate to the LRU list", superseding the flawed fix in commit 38fc4856ad98 ("drm/amdgpu: fix a potential deadlock in amdgpu_bo_create_restricted()"). This change fixes remaining recursive locking errors that can be seen with lock debugging enabled, and avoids the error of freeing a locked mutex. As an additional minor bonus, buffers created with resv == NULL and the AMDGPU_GEM_CREATE_VRAM_CLEARED flag are now only added to the global LRU list after the fill commands have been issued. v2: use amdgpu_bo_unreserve instead of ttm_bo_unreserve Fixes: 12a852219583 ("drm/amdgpu: improve AMDGPU_GEM_CREATE_VRAM_CLEARED handling (v2)") Signed-off-by: Nicolai Hähnle <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/ttm: add ttm_bo_init_reservedNicolai Hähnle2-15/+98
This variant of ttm_bo_init returns the validated buffer object with the reservation lock held when resv == NULL. This is convenient for callers that want to use the BO immediately, e.g. for initializing its contents. Signed-off-by: Nicolai Hähnle <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/ttm: fix the documentation of ttm_bo_initNicolai Hähnle1-1/+5
As the comment says: callers of ttm_bo_init cannot rely on having the only reference to the BO when the function returns successfully. Signed-off-by: Nicolai Hähnle <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29Revert "drm/amdgpu: fix a potential deadlock in amdgpu_bo_create_restricted()"Nicolai Hähnle1-4/+1
This reverts commit 38fc4856ad98f230bc91da0421dec69e4aee40f8, which introduces a use-after-free. The underlying bug should be properly fixed with "drm/ttm: never add BO that failed to validate to the LRU list". Cc: zhoucm1 <[email protected]> Signed-off-by: Nicolai Hähnle <[email protected]> Tested-by: Samuel Pitoiset <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/ttm: never add BO that failed to validate to the LRU listNicolai Hähnle1-5/+7
Fixes a potential race condition in amdgpu that looks as follows: Task 1: attempt ttm_bo_init, but ttm_bo_validate fails Task 1: add BO to global list anyway Task 2: grabs hold of the BO, waits on its reservation lock Task 1: releases its reference of the BO; never gives up the reservation lock The patch "drm/amdgpu: fix a potential deadlock in amdgpu_bo_create_restricted()" attempts to fix that by releasing the reservation lock in amdgpu code; unfortunately, it introduces a use-after-free when this race _doesn't_ happen. This patch should fix the race properly by never adding the BO to the global list in the first place. Cc: zhoucm1 <[email protected]> Signed-off-by: Nicolai Hähnle <[email protected]> Tested-by: Samuel Pitoiset <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: expose GPU sensor related informationAlex Deucher3-1/+97
This includes shader/memory clocks, temperature, GPU load, etc. v2: - add sub-queries for AMDPGU_INFO_GPU_SENSOR_* - do not break the ABI v3: - return -ENOENT when amdgpu_dpm == 0 - expose more sensor queries v4: - s/GPU_POWER/GPU_AVG_POWER/ - improve VDDNB/VDDGFX query description - fix amdgpu_dpm check v5: - agd: fix warning v6: - agd: bump version Signed-off-by: Samuel Pitoiset <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: expose amdgpu_sensors on pre-powerplay chipsSamuel Pitoiset1-0/+6
read_sensor() has been recently implemented for dpm based boards which means amdgpu_sensors can now be exposed. v2: - make sure read_sensor is not NULL on dpm chips - keep sanity check for powerplay chips v3: - make sure amdgpu_dpm != 0 Cc: Tom St Denis <[email protected]> Reviewed-by: Tom St Denis <[email protected]> Signed-off-by: Samuel Pitoiset <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: implement read_sensor() for pre-powerplay chipsSamuel Pitoiset4-1/+121
Add the GPU temperature, the shader clock and eventually the memory clock (as well as the GPU load on CI). The main goal is to expose this info to the userspace like Radeon. v2: - add AMDGPU_PP_SENSOR_GPU_LOAD on CI - update the commit description Signed-off-by: Samuel Pitoiset <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/radeon: allow unaligned shader loads on CIKMarek Olšák2-3/+7
Set alignment mode to unaligned on CIK to align with amdgpu. This is needed for unaligned loads to work properly in mesa. The current setting requires dword alignment. Signed-off-by: Marek Olšák <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: fix PRT teardown on VM fini v3Christian König2-26/+82
v2: new approach fixing this by registering a fence callback for all users of the VM on teardown v3: agd: rebase Signed-off-by: Christian König <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add OOM fallback on PRT teardown (v2)Christian König1-6/+22
Don't assume kmalloc will always succeed. v2: agd: rebase Signed-off-by: Christian König <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: minor PRT turnoff fix (v2)Christian König1-7/+5
When two VMs stop using PRT support at the same time we might not disable it in the right order otherwise. v2: agd: rebase Signed-off-by: Christian König <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: change pte definitions to 64 bitAlex Xie1-1/+1
Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Xie <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: fix PTE definesChristian König1-7/+7
Those should be 64bit, even on a 32bit system. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amd/amdgpu: Update read_sensor calls to have size parameter (v3)Tom St Denis8-27/+64
This update allows sensors to return more than 1 value and indicates to the caller how many bytes are written. The debugfs interface has been updated to handle reading all of the values. Simply seek to the enum value (multiplied by 4) and then read as many bytes as the sensor provides. (v2): Don't set size to 4 before reading GPU_POWER (v3): agd: rebase Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: implement PRT for GFX8 v2Christian König1-0/+57
Enable/disable the handling globally for now and print a warning when we enable it for the first time. v2: set correct register Signed-off-by: Junwei Zhang <[email protected]> Signed-off-by: Christian König <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: implement PRT for GFX7 v2Christian König1-0/+57
Enable/disable the handling globally for now and print a warning when we enable it for the first time. v2: set correct register Signed-off-by: Junwei Zhang <[email protected]> Signed-off-by: Christian König <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: implement PRT for GFX6 v2Christian König3-0/+60
Enable/disable the handling globally for now and print a warning when we enable it for the first time. v2: write to the correct register, adjust bits to that hw generation v3: fix compilation, add the missing register bit definitions Signed-off-by: Christian König <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: IOCTL interface for PRT support v4Junwei Zhang5-27/+64
Till GFX8 we can only enable PRT support globally, but with the next hardware generation we can do this on a per page basis. Keep the interface consistent by adding PRT mappings and enable support globally on current hardware when the first mapping is made. v2: disable PRT support delayed and on all error paths v3: PRT and other permissions are mutal exclusive, PRT mappings don't need a BO. v4: update PRT mappings durign CS as well, make va_flags 64bit Signed-off-by: Junwei Zhang <[email protected]> Signed-off-by: Christian König <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add basic PRT support (v2)Christian König3-11/+98
Future hardware generations can handle PRT flags on a per page basis, but current hardware can only turn it on globally. Add the basic handling for both, a global callback to enable/disable triggered by setting a per mapping flag. v2: agd: rebase fixes Signed-off-by: Christian König <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add support for BO_VAs without BO v2Christian König1-6/+14
For PRT support we need mappings which aren't backed by any memory. v2: fix parameter checking Signed-off-by: Christian König <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:use hw_init for sriov_gpu_resetMonk Liu1-6/+6
no suspend invoked so after VF FLR by host, we just call hw_init to reinitialize IPs. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected] Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amd/powerplay: implement gpu power display for smu7_hwmgrEric Huang1-0/+33
Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amd/powerplay: add power consumption display support in debugfsEric Huang2-0/+19
The additional output are: vddc power in Watt; vddci power in Watt; max gpu power in Watt; average gpu power in Watt. Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amd/powerplay: change parameter type pointer from int32_t to void in ↵Eric Huang6-36/+36
read sensor As well as fix print format for uint32_t type. Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amd/amdgpu: add power profile support for CIEric Huang2-0/+259
Signed-off-by: Eric Huang <[email protected]> Acked-by: Rex Zhu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amd/powerplay: add power profile support for PolarisEric Huang3-0/+67
Signed-off-by: Eric Huang <[email protected]> Acked-by: Rex Zhu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amd/powerplay: add power profile support for FijiEric Huang3-1/+68
Signed-off-by: Eric Huang <[email protected]> Acked-by: Rex Zhu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amd/powerplay: add power profile support for tongaEric Huang3-0/+66
Signed-off-by: Eric Huang <[email protected]> Acked-by: Rex Zhu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amd/powerplay: add power profile support for SMU7Eric Huang3-0/+86
Signed-off-by: Eric Huang <[email protected]> Acked-by: Rex Zhu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amd/powerplay: reapply power profile when force dpm level to autoEric Huang1-3/+19
Signed-off-by: Eric Huang <[email protected]> Acked-by: Rex Zhu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amd/amdgpu: add power profile sysfs entryEric Huang6-1/+382
Add the sysfs entries pp_gfx_power_profile and pp_compute_power_profile which give user a way to set power profile through parameters minimum sclk, minimum mclk, activity threshold, up hysteresis and down hysteresis only when the entry power_dpm_force_performance_level is in default value "auto". It is read and write. Example: echo 500 800 20 0 5 > /sys/class/drm/card0/device/pp_*_power_profile cat /sys/class/drm/card0/device/pp_*_power_profile 500 800 20 0 5 Note: first parameter is sclk in MHz, second is mclk in MHz, third is activity threshold in percentage, fourth is up hysteresis in ms and fifth is down hysteresis in ms. echo set > /sys/class/drm/card0/device/pp_*_power_profile To set power profile state if it exists. echo reset > /sys/class/drm/card0/device/pp_*_power_profile To restore default state and clear previous setting. Signed-off-by: Eric Huang <[email protected]> Acked-by: Rex Zhu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:cleanup no needed bracesMonk Liu1-6/+3
Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:don't return error for debugfs failedMonk Liu1-1/+0
Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:add lock_reset for SRIOVMonk Liu3-0/+4
this lock is used for sriov_gpu_reset, only get this mutex can run into sriov_gpu_reset. we have couple source triggers gpu_reset for SRIOV: 1) submit timedout and trigger reset voluntarily 2) invalid instruction detected by ENGINE and trigger reset voluntarily 2) hypervisor found world switch hang and trigger flr and notify guest to do reset. all need take care and we need a mutex to protect the consistency of reset routine. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:change kiq lock nameMonk Liu2-6/+6
Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:implement SRIOV gpu_reset (v2)Monk Liu2-1/+156
implement SRIOV gpu_reset for future use. it wil be called from: 1) job timeout 2) privl access or instruction error interrupt 3) hypervisor detect VF hang v2: agd: rebase on upstream Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:divide KCQ mqd init to sw and hwMonk Liu1-65/+42
sw part only invoked once during sw_init. hw part invoked during first drv load and resume later. that way we cannot alloc mqd in hw/resume, we only keep mqd allocted in sw_init routine. and hw_init routine only kmap and set it. Signed-off-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:minor cleanupMonk Liu1-4/+1
Signed-off-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:no need use sriov vf checksMonk Liu1-9/+4
We ultimately want to re-use this for bare metal, so no need to have vf checks in the KIQ code itself since kiq itself is currently only used in VF cases. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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