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2017-03-29drm/amdgpu: add uvd enc ring type and functionsLeo Liu1-1/+2
Reviewed-by: Christian König <[email protected]> Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add uvd enc run queueLeo Liu1-0/+1
Reviewed-by: Christian König <[email protected]> Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add uvd enc ringsLeo Liu2-1/+4
And initialize them Reviewed-by: Christian König <[email protected]> Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: move amdgpu_vce structure to vce headerLeo Liu2-28/+26
Reviewed-by: Christian König <[email protected]> Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: move amdgpu_uvd structure to uvd headerLeo Liu2-29/+27
Reviewed-by: Christian König <[email protected]> Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add a ring func for end commandLeo Liu2-0/+4
Reviewed-by: Christian König <[email protected]> Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add DF MGCG flagHuang Rui1-0/+1
Acked-by: Christian König <[email protected]> Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add DRM MGCG headerHuang Rui1-0/+1
Acked-by: Christian König <[email protected]> Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add asic callback to get memsize registerAlex Deucher5-1/+23
Newer asics use different registers so abstract it. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: check function points valid before use. (v3)Rex Zhu1-14/+18
v2: agd: integrate Christian's comments. v3: print error message if call fails Reviewed-by: Christian König <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add a callback to set vm mapping flagsAlex Xie5-9/+57
This lets each asic set whichever flags it supports. Signed-off-by: Alex Xie <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: set GART PTE asic specific flagsAlex Xie5-3/+8
Set asic specific gart pte flags in the gmc IP module for each asic. Signed-off-by: Alex Xie <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add a ucode size member into firmware infoHuang Rui2-2/+7
This will be used for newer asics. Acked-by: Christian König <[email protected]> Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: expand pte flags to uint64_tChunming Zhou11-25/+25
Necessary for new asics. Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu/ih: store the full context idAlex Deucher15-36/+38
The contextID field (formerly known as src_data) of the IH vector stores client specific information about an interrupt. It was expanded from 32 bits to 128 on newer asics. Expand the src_id field to handle this. Reviewed-by: Harry Wentland <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: switch ih handling to two levels (v3)Alex Deucher34-105/+193
Newer asics have a two levels of irq ids now: client id - the IP src id - the interrupt src within the IP v2: integrated Christian's comments. v3: fix rebase fail in SI and CIK Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Ken Wang <[email protected]> Reviewed-by: Ken Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add 64bit doorbell functions (v2)Ken Wang2-0/+42
Newer asics need 64 bit doorbells. v2: fix comment (Nils) Reviewed-by: Christian König <[email protected]> Signed-off-by: Ken Wang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add 64bit wb functionsKen Wang3-13/+78
Newer asics need 64 bit writeback slots. Reviewed-by: Christian König <[email protected]> Signed-off-by: Ken Wang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: change wptr to 64 bits (v2)Ken Wang15-83/+107
Newer asics need 64 bit wptrs. If the wptr is now smaller than the rptr that doesn't indicate a wrap-around anymore. v2: integrate Christian's comments. Signed-off-by: Ken Wang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: init aperture definitions (v2)Junwei Zhang5-7/+55
v2: agd: move apertures to mc structure Signed-off-by: Flora Cui <[email protected]> Reviewed-by: Jammy Zhou <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: Merge pre/postclose hooksDaniel Vetter3-18/+2
Again no apparent explanation for the split except hysterical raisins. Merging them also makes it a bit more obviuos what's going on wrt the runtime pm refdancing. Cc: Alex Deucher <[email protected]> Cc: Christian König <[email protected]> Cc: [email protected] Reviewed-by: Christian König <[email protected]> Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/radeon: Merge pre/postclose hooksDaniel Vetter2-31/+14
Again no apparent explanation for the split except hysterical raisins. Merging them also makes it a bit more obviuos what's going on wrt the runtime pm refdancing. Cc: Alex Deucher <[email protected]> Cc: Christian König <[email protected]> Cc: [email protected] Reviewed-by: Christian König <[email protected]> Signed-off-by: Daniel Vetter <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: trace fence details in amdgpu_sched_run_jobAndres Rodriguez1-2/+9
This information is intended to provide the required data to associate amdgpu tracepoints with their corresponding dma_fence_* events. Reviewed-by: Christian König <[email protected]> Signed-off-by: Andres Rodriguez <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: make trace format uniform csv name=valueAndres Rodriguez1-2/+2
Most of the traces have uniform format except for two of them. Having all the traces match makes it simple to run awk on the ftrace output. Reviewed-by: Christian König <[email protected]> Signed-off-by: Andres Rodriguez <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu/gfx8: move CE&DE meta data structure to vi_structs.hXiangliang Yu3-120/+114
Because different HWs have different definition for CE & DE meta data, follow mqd design to move the structures to vi_structs.h. And change the prefix from amdgpu to vi as the structures is only for VI family. Signed-off-by: Xiangliang Yu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amd/amdgpu: add DID for Polaris10Junshan Fang1-0/+1
Signed-off-by: Junshan Fang <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add polaris12 to virtual dce handlingAlex Deucher1-1/+2
Was missed when polaris12 support was added. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: remove unused sync testingChristian König3-89/+0
Not used in a while. Signed-off-by: Christian König <[email protected]> Reviewed-by: Ken Wang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amd/powerplay: simplify avfs control code in smu7Eric Huang1-5/+4
Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amd/powerplay: add function avfs control in smu7Eric Huang1-0/+20
Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amd/powerplay: add voltage change support through pp_tableEric Huang2-1/+12
Disable avfs to make voltage change take effect. Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/radeon: remove useless and potentially wrong messageAndy Shevchenko1-4/+1
There is no need to repeat information that printed by PCI core at boot time. Besides that printing was potentially wrong since resource_size_t might be bigger than 32 bits and there is a dedicated specifier for such type, i.e. %pap. Someone can fix it and use even better approach, i.e. %pR. Signed-off-by: Andy Shevchenko <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: print full bios version in dmesg.Rex Zhu2-14/+9
v2: fix merge error. Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Xiaojie Yuan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: disable HDP flushes on APUsChristian König1-2/+10
We completely bypass the HDP now. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29gpu: drm: amd/radeon: Convert printk(KERN_<LEVEL> to pr_<level>Joe Perches39-252/+155
Use a more common logging style. Miscellanea: o Coalesce formats and realign arguments o Neaten a few macros now using pr_<level> Signed-off-by: Joe Perches <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm: Use pr_cont where appropriateJoe Perches2-68/+73
Using 'printk("\n")' is not preferred anymore and using printk to continue logging messages now produces multiple line logging output unless the continuations use KERN_CONT. Convert these uses to appropriately use pr_cont or a single printk where possible. Miscellanea: o Use a temporary const char * instead of multiple printks o Remove trailing space from logging by using a leading space instead Signed-off-by: Joe Perches <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: put gtt at 0 in the internal address spaceAlex Deucher1-1/+1
There still seem to be some blocks that make accesses in the lower part of the address space. This works around this. Reviewed-by: Junwei Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu/vce2: fix vce bar programmingAlex Deucher1-8/+9
Program the VCE BAR and offsets properly. The current code was carried over from a limitation from older VCE versions. Reviewed-by: Junwei Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drivers/gpu: Convert remaining uses of pr_warning to pr_warnJoe Perches6-15/+15
To enable eventual removal of pr_warning This makes pr_warn use consistent for drivers/gpu Prior to this patch, there were 15 uses of pr_warning and 20 uses of pr_warn in drivers/gpu Acked-by: Christian König <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Signed-off-by: Joe Perches <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amd: Spelling s/SDMA_WRTIE_SUB_OPCODE_TILED/SDMA_WRITE_SUB_OPCODE_TILED/Geert Uytterhoeven2-2/+2
Reviewed-by: Christian König <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]> Cc: Alex Deucher <[email protected]> Cc: Christian König <[email protected]> Cc: [email protected]@lists.freedesktop.org Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/radeon/dp_auxch: Ratelimit aux transfer debug messagesLyude1-1/+2
Aux transfers always fail with non-zero status flags when there's nothing connected on the port, so we don't usually need to see all of the debugging information from it. Also, we try reprobing a -lot-, so without ratelimiting most of the kernel log is filled up with messages from radeon_dp_aux_transfer_native. Signed-off-by: Lyude <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu/powerplay: enable LEDs on Fiji boardsAlex Deucher2-0/+35
This enables the LEDs that light up based on DPM states on some Fiji boards. bug: https://bugs.freedesktop.org/show_bug.cgi?id=97590 Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: rename amdgpu_gca_config to amdgpu_gfx_configJunwei Zhang1-2/+2
Signed-off-by: Junwei Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: Fix module unload hang by KIQ IRQ setTrigger Huang1-6/+4
In some cases, manually insmod/rmmod amdgpu is necessary. When unloading amdgpu, the KIQ IRQ enable/disable function will case system hang. The root cause is, in the sequence of function amdgpu_fini, the sw_fini of IP block AMD_IP_BLOCK_TYPE_GFX will be invoked earlier than that of AMD_IP_BLOCK_TYPE_IH. So continue to use the variable freed by AMD_IP_BLOCK_TYPE_GFX will cause system hang. Signed-off-by: Trigger Huang <[email protected]> Reviewed-by: Xiangliang Yu < [email protected]> Reviewed-by: Monk Liu <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: bump driver version for new lds buffer queryAlex Deucher1-1/+2
v2: agd: bump version Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: export gfx config double offchip LDS buffers (v3)Junwei Zhang6-0/+33
v2: move the config struct to drm_amdgpu_info_device v3: move the config feature to amdgpu_gca_config Signed-off-by: Junwei Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu/gfx: free memory of mqd backupXiangliang Yu1-0/+2
Need to free mqd backup when destroying ring. Signed-off-by: Xiangliang Yu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Monk Liu <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu/virt: fix typoXiangliang Yu1-8/+8
When send messages to hypervior, the messages format should be is idh_request, not idh_event. Signed-off-by: Xiangliang Yu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Monk Liu <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: change pointer of mqd_ptr & mqd_backup to voidXiangliang Yu3-11/+19
vi_mqd is only used by VI family but mqd_ptr and mqd_backup is common for all ASIC, so change the pointer to void. Signed-off-by: Xiangliang Yu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu:fix kiq_resume routine (V2)Monk Liu2-11/+35
v2: use in_rest to fix compute ring test failure issue which occured after FLR/gpu_reset. we need backup a clean status of MQD which was created in drv load stage, and use it in resume stage, otherwise KCQ and KIQ all may faild in ring/ib test. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Xiangliang Yu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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