aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2021-02-06mei: implement client dma setup.Alexander Usyskin6-1/+446
Implement HBM message protocol to setup and tear down DMA buffer on behalf of an client. On top there DMA buffer allocation and its life time management. Signed-off-by: Alexander Usyskin <[email protected]> Signed-off-by: Tomas Winkler <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-06mei: hbm: add client dma hbm messagesAlexander Usyskin1-0/+53
Define structures for client DMA HBM protocol. The protocol requires passing dma buffer address and the buffer id. Signed-off-by: Alexander Usyskin <[email protected]> Signed-off-by: Tomas Winkler <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-06mei: add support for client dma capabilityAlexander Usyskin4-1/+23
Client DMA capability indicates whether the firmware supports setting up a direct DMA channel between the host and me client. The DMA capabilities are supported from firmware HBM version 2.2 and newer. Signed-off-by: Alexander Usyskin <[email protected]> Signed-off-by: Tomas Winkler <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-06mei: allow clients on bus to communicate in remove callbackAlexander Usyskin4-4/+11
Introduce new intermediate state to allow the clients on the bus to communicate with the firmware from the remove handler. This is to enable to perform a clean shutdown. Signed-off-by: Alexander Usyskin <[email protected]> Signed-off-by: Tomas Winkler <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-06soundwire: bus: use no_pm IO routines for all interrupt handlingPierre-Louis Bossart1-13/+13
There is no need to play with pm_runtime reference counts, if needed the codec drivers are already explicitly resumed. Signed-off-by: Pierre-Louis Bossart <[email protected]> Reviewed-by: Rander Wang <[email protected]> Signed-off-by: Bard Liao <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-06soundwire: bus: use sdw_write_no_pm when setting the bus scale registersPierre-Louis Bossart1-3/+3
When a Slave device is resumed, it may resume the bus and restart the enumeration. During that process, we absolutely don't want to call regular read/write routines which will wait for the resume to complete, otherwise a deadlock occurs. This patch fixes the same problem as the previous one, but is split to make the life of linux-stable maintainers less painful. Fixes: 29d158f90690 ('soundwire: bus: initialize bus clock base and scale registers') Signed-off-by: Pierre-Louis Bossart <[email protected]> Reviewed-by: Rander Wang <[email protected]> Signed-off-by: Bard Liao <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-06soundwire: bus: use sdw_update_no_pm when initializing a devicePierre-Louis Bossart1-2/+14
When a Slave device is resumed, it may resume the bus and restart the enumeration. During that process, we absolutely don't want to call regular read/write routines which will wait for the resume to complete, otherwise a deadlock occurs. Fixes: 60ee9be25571 ('soundwire: bus: add PM/no-PM versions of read/write functions') Signed-off-by: Pierre-Louis Bossart <[email protected]> Reviewed-by: Rander Wang <[email protected]> Signed-off-by: Bard Liao <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-06soundwire: Revert "soundwire: debugfs: use controller id instead of link_id"Vinod Koul1-1/+1
This reverts commit 6d5e7af1f6f5 ("soundwire: debugfs: use controller id instead of link_id") for now while we arrive at a better way for this. Signed-off-by: Vinod Koul <[email protected]>
2021-02-06phy: cpcap-usb: Simplify bool conversionYang Li1-1/+1
Fix the following coccicheck warning: ./drivers/phy/motorola/phy-cpcap-usb.c:146:31-36: WARNING: conversion to bool not needed here Reported-by: Abaci Robot <[email protected]> Signed-off-by: Yang Li <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-06phy: qcom-qmp: make a const array static, makes object smallerColin Ian King1-1/+1
Don't populate the const array cfg1_settings on the stack but instead make it static. Makes the object code smaller by 24 bytes: Before: text data bss dec hex filename 73585 20240 64 93889 16ec1 drivers/phy/qualcomm/phy-qcom-qmp.o After: text data bss dec hex filename 73465 20336 64 93865 16ea9 drivers/phy/qualcomm/phy-qcom-qmp.o (gcc version 10.2.0) Signed-off-by: Colin Ian King <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-06phy: zynqmp: Simplify code by using dev_err_probe()Michal Simek1-7/+4
Use already prepared dev_err_probe() introduced by commit a787e5400a1c ("driver core: add device probe log helper"). It simplifies EPROBE_DEFER handling. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/0df30548f721b10475a6cc5659beda102fec3c87.1612444300.git.michal.simek@xilinx.com Signed-off-by: Vinod Koul <[email protected]>
2021-02-06phy: qcom-qmp: Add support for SM8350 UFS phyVinod Koul1-0/+127
Add the tables for init sequences for UFS QMP phy found in SM8350 SoC. Signed-off-by: Vinod Koul <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-06phy: qcom-qmp: Add UFS V5 registers found in SM8350Vinod Koul1-0/+47
Add the registers for UFS found in SM8350. The UFS phy used in SM8350 seems to have same offsets as V5 phy, although Documentation for that is lacking. Signed-off-by: Vinod Koul <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-06dt-bindings: phy: qcom,qmp: Add SM8350 UFS PHY bindingsVinod Koul1-0/+1
Add the compatible strings for the UFS PHY found on SM8350 SoC. Signed-off-by: Vinod Koul <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2021-02-05Merge tag 'mhi-for-v5.12' of ↵Greg Kroah-Hartman4-145/+461
git://git.kernel.org/pub/scm/linux/kernel/git/mani/mhi into char-misc-next Manivannan writes: MHI changes for v5.12 Loic improved the MHI PCI generic controller by adding support for DIAG channel, PCI error handling, suspend/recovery/resume, and health check. Loic also added support for resetting the MHI device as per the MHI specification. This includes writing to a specific register for default cases and looking for controller specific callback when provided. Along with this Loic, also added a new API which gets the number for free TREs (Transfer Ring Elements) from the MHI core. The client drivers can make use of this API and the current consumer is the "mhi-net" driver. For taking both the "mhi-net" driver change and the API change, we created "mhi-net-immutable" branch for this patch and merged the same into net-next and mhi-next. Carl added a patch which lets the controller driver to pass the custom IRQ flags for BHI and MHI event interrupts to the MHI core. The current consumer of this feature is the ath11k MHI controller driver. For taking both the changes, we created "mhi-ath11k-immutable" branch for this patch and merged into ath11k-next and mhi-next. Finally, Loic cleaned up the MHI queue APIs and fixed the shared MSI vector support. * tag 'mhi-for-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/mhi: bus: mhi: pci_generic: Increase num of elements in hw event ring mhi: pci_generic: Print warning in case of firmware crash bus: mhi: core: Add helper API to return number of free TREs mhi: core: Factorize mhi queuing mhi: use irq_flags if controller driver configures it mhi: pci_generic: Fix shared MSI vector support mhi: unconstify mhi_event_config bus: mhi: Ensure correct ring update ordering with memory barrier mhi: pci_generic: Set irq moderation value to 1ms for hw channels mhi: pci_generic: Add diag channels mhi: pci_generic: Increase controller timeout value mhi: pci_generic: Add health-check mhi: pci_generic: Add PCI error handlers mhi: pci_generic: Add suspend/resume/recovery procedure mhi: pci_generic: Add support for reset mhi: pci_generic: Enable burst mode for hardware channels mhi: pci-generic: Increase number of hardware events bus: mhi: core: Add device hardware reset support
2021-02-05coresight: etm4x: Fix merge resolution for amba reworkUwe Kleine-König1-3/+4
This was non-trivial to get right because commits c23bc382ef0e ("coresight: etm4x: Refactor probing routine") and 5214b563588e ("coresight: etm4x: Add support for sysreg only devices") changed the code flow considerably. With this change the driver can be built again. Fixes: 0573d3fa4864 ("Merge branch 'devel-stable' of git://git.armlinux.org.uk/~rmk/linux-arm into char-misc-next") Signed-off-by: Uwe Kleine-König <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-05bus: mhi: pci_generic: Increase num of elements in hw event ringLoic Poulain1-1/+1
We met some sporadic modem crashes during high throughput testing, this has been root caused to a lack of elements in the event ring. Indeed, the modem is simply crashing when event ring becomes empty. It appears that the total number event ring elements is too low given the performances of the modem (IPA hardware accelerator). This change increases the number of elements in the hardware event ring to 2048, which is aligned with what is defined in downstream version: https://source.codeaurora.org/quic/la/kernel/msm-4.14/tree/arch/arm64/boot/dts/qcom/sm8150-mhi.dtsi?h=msm-4.14#n482 With this change, modem coes not crash anymore. Note: An event ring element is 16-Byte, so the total memory usage of a hardware event ring is now 32KB. Signed-off-by: Loic Poulain <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]>
2021-02-05mhi: pci_generic: Print warning in case of firmware crashLoic Poulain1-0/+10
Print warning when MHI detects sys error. Signed-off-by: Loic Poulain <[email protected]> Reviewed-by: Hemant Kumar <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]>
2021-02-05nvmem: qcom-spmi-sdam: Fix uninitialized pdev pointerSubbaraman Narayanamurthy1-4/+3
"sdam->pdev" is uninitialized and it is used to print error logs. Fix it. Since device pointer can be used from sdam_config, use it directly thereby removing pdev pointer. Fixes: 40ce9798794f ("nvmem: add QTI SDAM driver") Cc: [email protected] Signed-off-by: Subbaraman Narayanamurthy <[email protected]> Signed-off-by: Srinivas Kandagatla <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-05nvmem: Kconfig: Correct typo in NVMEM_RMEMNicolas Saenz Julienne1-1/+1
s/drivers/driver/ as the configuration selects a single driver. Suggested-by: Randy Dunlap <[email protected]> Acked-by: Randy Dunlap <[email protected]> Signed-off-by: Nicolas Saenz Julienne <[email protected]> Signed-off-by: Srinivas Kandagatla <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-05Merge branch 'devel-stable' of git://git.armlinux.org.uk/~rmk/linux-arm into ↵Greg Kroah-Hartman31-200/+157
char-misc-next This merges from linux-arm at 860660fd829e ("ARM: 9055/1: mailbox: arm_mhuv2: make remove callback return void") into char-misc-next to get the amba fixes from Uwe. Cc: Uwe Kleine-König <[email protected]> Cc: Russell King <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-05Merge tag 'icc-5.12-rc1' of ↵Greg Kroah-Hartman14-550/+1286
git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into char-misc-next Georgi writes: interconnect changes for 5.12 Here are the interconnect changes for the 5.12-rc1 merge window consisting of driver updates. Driver changes: - Refactoring and consolidation of drivers. - New driver for MSM8939 platforms. - New driver for SDX55 platforms. Signed-off-by: Georgi Djakov <[email protected]> * tag 'icc-5.12-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc: interconnect: qcom: Add SDX55 interconnect provider driver dt-bindings: interconnect: Add Qualcomm SDX55 DT bindings interconnect: qcom: Add MSM8939 interconnect provider driver dt-bindings: interconnect: Add Qualcomm MSM8939 DT bindings dt-bindings: interconnect: single yaml file for RPM interconnect drivers interconnect: qcom: qcs404: use shared code interconnect: qcom: Consolidate interconnect RPM support
2021-02-04ARM: 9055/1: mailbox: arm_mhuv2: make remove callback return voidUwe Kleine-König1-3/+1
My build tests failed to catch that amba driver that would have needed adaption in commit 3fd269e74f2f ("amba: Make the remove callback return void"). Change the remove function to make the driver build again. Link: https://lore.kernel.org/r/[email protected] Reported-by: kernel test robot <[email protected]> Fixes: 3fd269e74f2f ("amba: Make the remove callback return void") Acked-by: Viresh Kumar <[email protected]> Signed-off-by: Uwe Kleine-König <[email protected]> Signed-off-by: Russell King <[email protected]>
2021-02-04misc: rtsx: init of rts522a add OCP power off when no card is presentRicky Wu1-0/+5
Power down OCP for power consumption when no SD/MMC card is present Cc: [email protected] Signed-off-by: Ricky Wu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-04speakup: Make dectlk flush timeout configurableSamuel Thibault5-2/+23
In case the serial port or cable got faulty, we may not be getting acknowledgements any more. The driver then currently waits for 4s to avoid jamming the device. This makes this delay configurable. Signed-off-by: Samuel Thibault <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-04speakup ABI: Advertise synth parameters for all synthsSamuel Thibault1-15/+15
The parameters were advertised for the "soft" synth, but they are available for all synths. Signed-off-by: Samuel Thibault <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-04nvmem: core: skip child nodes not matching bindingAhmad Fatoum1-1/+3
The nvmem cell binding applies to all eeprom child nodes matching "^.*@[0-9a-f]+$" without taking a compatible into account. Linux drivers, like at24, are even more extensive and assume _all_ at24 eeprom child nodes to be nvmem cells since e888d445ac33 ("nvmem: resolve cells from DT at registration time"). Since df5f3b6f5357 ("dt-bindings: nvmem: stm32: new property for data access"), the additionalProperties: True means it's Ok to have other properties as long as they don't match "^.*@[0-9a-f]+$". The barebox bootloader extends the MTD partitions binding to EEPROM and can fix up following device tree node: &eeprom { partitions { compatible = "fixed-partitions"; }; }; This is allowed binding-wise, but drivers using nvmem_register() like at24 will fail to parse because the function expects all child nodes to have a reg property present. This results in the whole EEPROM driver probe failing despite the device tree being correct. Fix this by skipping nodes lacking a reg property instead of returning an error. This effectively makes the drivers adhere to the binding because all nodes with a unit address must have a reg property and vice versa. Fixes: e888d445ac33 ("nvmem: resolve cells from DT at registration time"). Signed-off-by: Ahmad Fatoum <[email protected]> Signed-off-by: Srinivas Kandagatla <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-04nvmem: Add driver to expose reserved memory as nvmemNicolas Saenz Julienne4-0/+108
Firmware/co-processors might use reserved memory areas in order to pass data stemming from an nvmem device otherwise non accessible to Linux. For example an EEPROM memory only physically accessible to firmware, or data only accessible early at boot time. In order to expose this data to other drivers and user-space, the driver models the reserved memory area as an nvmem device. Tested-by: Tim Gover <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Nicolas Saenz Julienne <[email protected]> Signed-off-by: Srinivas Kandagatla <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-04dt-bindings: nvmem: Add bindings for rmem driverNicolas Saenz Julienne1-0/+49
Firmware/co-processors might use reserved memory areas in order to pass data stemming from an nvmem device otherwise non accessible to Linux. For example an EEPROM memory only physically accessible to firmware, or data only accessible early at boot time. Introduce the dt-bindings to nvmem's rmem. Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Nicolas Saenz Julienne <[email protected]> Signed-off-by: Srinivas Kandagatla <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-04nvmem: imx-iim: Use of_device_get_match_data()Fabio Estevam1-6/+1
The retrieval of driver data via of_device_get_match_data() can make the code simpler. Use of_device_get_match_data() to simplify the code. Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Srinivas Kandagatla <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-04nvmem: core: Fix a resource leak on error in nvmem_add_cells_from_of()Dan Carpenter1-0/+1
This doesn't call of_node_put() on the error path so it leads to a memory leak. Fixes: 0749aa25af82 ("nvmem: core: fix regression in of_nvmem_cell_get()") Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Srinivas Kandagatla <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-04cxl: Simplify bool conversionYang Li1-1/+1
Fix the following coccicheck warning: ./drivers/misc/cxl/sysfs.c:181:48-53: WARNING: conversion to bool not needed here Reported-by: Abaci Robot <[email protected]> Reviewed-by: Andrew Donnellan <[email protected]> Acked-by: Frederic Barrat <[email protected]> Signed-off-by: Yang Li <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-04coresight: etm4x: Handle accesses to TRCSTALLCTLRSuzuki K Poulose2-4/+7
TRCSTALLCTLR register is only implemented if TRCIDR3.STALLCTL == 0b1 Make sure the driver touches the register only it is implemented. Link: https://lore.kernel.org/r/[email protected] Cc: [email protected] Cc: Mathieu Poirier <[email protected]> Cc: Mike Leach <[email protected]> Cc: Leo Yan <[email protected]> Signed-off-by: Suzuki K Poulose <[email protected]> Signed-off-by: Mathieu Poirier <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-04coresight: Add support for v8.4 SelfHosted tracingJonathan Zhou1-0/+25
v8.4 tracing extensions added support for trace filtering controlled by TRFCR_ELx. This must be programmed to allow tracing at EL1/EL2 and EL0. The timestamp used is the virtual time. Also enable CONTEXIDR_EL2 tracing if we are running the kernel at EL2. Link: https://lore.kernel.org/r/[email protected] Cc: Catalin Marinas <[email protected]> Cc: Mike Leach <[email protected]> Cc: Will Deacon <[email protected]> Reviewed-by: Mathieu Poirier <[email protected]> Signed-off-by: Jonathan Zhou <[email protected]> [ Move the trace filtering setup etm_init_arch_data() and clean ups] Signed-off-by: Suzuki K Poulose <[email protected]> Signed-off-by: Mathieu Poirier <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-04arm64: Add TRFCR_ELx definitionsJonathan Zhou1-0/+11
Add definitions for the Arm v8.4 SelfHosted trace extensions registers. [ split the register definitions to separate patch rename some of the symbols ] Link: https://lore.kernel.org/r/[email protected] Cc: Will Deacon <[email protected]> Acked-by: Catalin Marinas <[email protected]> Signed-off-by: Jonathan Zhou <[email protected]> Signed-off-by: Suzuki K Poulose <[email protected]> Signed-off-by: Mathieu Poirier <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-04dts: bindings: coresight: ETM system register access only unitsSuzuki K Poulose1-1/+4
Document the bindings for ETMs with system register accesses. Link: https://lore.kernel.org/r/[email protected] Cc: [email protected] Cc: Mathieu Poirier <[email protected]> Cc: Mike Leach <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Suzuki K Poulose <[email protected]> Signed-off-by: Mathieu Poirier <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-04coresight: etm4x: Add support for sysreg only devicesSuzuki K Poulose1-5/+63
Add support for devices with system instruction access only. They don't have a memory mapped interface and thus are not AMBA devices. System register access is not permitted to TRCPDCR and thus skip access to them. Link: https://lore.kernel.org/r/[email protected] Cc: Mike Leach <[email protected]> Signed-off-by: Suzuki K Poulose <[email protected]> Signed-off-by: Mathieu Poirier <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-04coresight: etm4x: Run arch feature detection on the CPUSuzuki K Poulose1-2/+4
As we are about to add support for system register based devices, we don't get an AMBA pid. So, the detection code could check the system registers running on the CPU to check for the architecture specific features. Thus we move the arch feature detection to run on the CPU. We cannot always read the PID from the HW, as the PID could be overridden by DT for broken devices. So, use the PID from AMBA layer if available. Link: https://lore.kernel.org/r/[email protected] Cc: Mathieu Poirier <[email protected]> Cc: Mike Leach <[email protected]> Cc: [email protected] Signed-off-by: Suzuki K Poulose <[email protected]> Signed-off-by: Mathieu Poirier <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-04coresight: etm4x: Refactor probing routineSuzuki K Poulose1-23/+39
CoreSight ETM with system register access may not have a memory mapped i/o access. Refactor the ETM specific probing into a common routine to allow reusing the code for such ETMs. Link: https://lore.kernel.org/r/[email protected] Cc: Mike Leach <[email protected]> Signed-off-by: Suzuki K Poulose <[email protected]> Signed-off-by: Mathieu Poirier <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-04coresight: etm4x: Detect system instructions supportSuzuki K Poulose1-0/+39
ETM v4.4 onwards adds support for system instruction access to the ETM. Detect the support on an ETM and switch to using the mode when available. Link: https://lore.kernel.org/r/[email protected] Cc: Mike Leach <[email protected]> Signed-off-by: Suzuki K Poulose <[email protected]> Signed-off-by: Mathieu Poirier <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-04coresight: etm4x: Add necessary synchronization for sysreg accessSuzuki K Poulose1-0/+13
As per the specification any update to the TRCPRGCTLR must be synchronized by a context synchronization event (in our case an explicist ISB) before the TRCSTATR is checked. Link: https://lore.kernel.org/r/[email protected] Cc: Mike Leach <[email protected]> Signed-off-by: Suzuki K Poulose <[email protected]> Signed-off-by: Mathieu Poirier <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-04coresight: etm4x: Expose trcdevarch via sysfsSuzuki K Poulose2-0/+9
Expose the TRCDEVARCH register via the sysfs for component detection. Given that the TRCIDR1 may not completely identify the ETM component and instead need to use TRCDEVARCH, expose this via sysfs for tools to use it for identification. Link: https://lore.kernel.org/r/[email protected] Cc: Mike Leach <[email protected]> Signed-off-by: Suzuki K Poulose <[email protected]> Signed-off-by: Mathieu Poirier <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-04coresight: etm4x: Use TRCDEVARCH for component discoverySuzuki K Poulose1-23/+23
We have been using TRCIDR1 for detecting the ETM version. This is in preparation for the future IP support. Link: https://lore.kernel.org/r/[email protected] Cc: Mike Leach <[email protected]> Signed-off-by: Suzuki K Poulose <[email protected]> Signed-off-by: Mathieu Poirier <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-04coresight: etm4x: Detect access early on the target CPUSuzuki K Poulose1-5/+40
In preparation to detect the support for system instruction support, move the detection of the device access to the target CPU. Link: https://lore.kernel.org/r/[email protected] Cc: Mike Leach <[email protected]> Signed-off-by: Suzuki K Poulose <[email protected]> Signed-off-by: Mathieu Poirier <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-04coresight: etm4x: Handle ETM architecture versionSuzuki K Poulose2-4/+58
We are about to rely on TRCDEVARCH for detecting the ETM and its architecture version, falling back to TRCIDR1 if the former is not implemented (in older broken implementations). Also, we use the architecture version information to make some decisions. Streamline the architecture version handling by adding helpers. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Suzuki K Poulose <[email protected]> Signed-off-by: Mathieu Poirier <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-04coresight: etm4x: Clean up exception level masksSuzuki K Poulose3-46/+60
etm4_get_access_type() calculates the exception level bits for use in address comparator registers. This is also used by the TRCVICTLR register by shifting to the required position. This patch cleans up the logic to make etm4_get_access_type() calculate a generic mask which can be used by all users by shifting to their field. No functional changes intended. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Suzuki K Poulose <[email protected]> Signed-off-by: Mathieu Poirier <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-04coresight: etm4x: Cleanup secure exception level masksSuzuki K Poulose2-12/+7
We rely on the ETM architecture version to decide whether Secure EL2 is available on the CPU for excluding the level for address comparators and viewinst main control register. We must instead use the TRCDIDR3.EXLEVEL_S field to detect the supported levels. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Suzuki K Poulose <[email protected]> Signed-off-by: Mathieu Poirier <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-04coresight: etm4x: Check for Software LockSuzuki K Poulose1-14/+26
The Software lock is not implemented for system instructions based accesses. So, skip the lock register access in such cases. Link: https://lore.kernel.org/r/[email protected] Cc: Mike Leach <[email protected]> Signed-off-by: Suzuki K Poulose <[email protected]> Signed-off-by: Mathieu Poirier <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-04coresight: etm4x: Define DEVARCH register fieldsSuzuki K Poulose2-2/+44
Define the fields of the DEVARCH register for identifying a component as an ETMv4.x unit. Going forward, we use the DEVARCH register for the component identification, rather than the TRCIDR3. Link: https://lore.kernel.org/r/[email protected] Cc: Mike Leach <[email protected]> Signed-off-by: Suzuki K Poulose <[email protected]> Signed-off-by: Mathieu Poirier <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2021-02-04coresight: etm4x: Hide sysfs attributes for unavailable registersSuzuki K Poulose2-0/+57
Some of the management registers in ETMv4.x are not accessible via system register instructions. Thus we must hide the sysfs files exposing them to the userspace, to prevent system crashes. This patch adds an is_visible() routine to control the visibility at runtime for the registers that may not be accessed. Link: https://lore.kernel.org/r/[email protected] Cc: Mathieu Poirier <[email protected]> Cc: Mike Leach <[email protected]> Signed-off-by: Suzuki K Poulose <[email protected]> Signed-off-by: Mathieu Poirier <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.