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2023-08-07drm/msm/a2xx: Call adreno_gpu_init() earlierFabio Estevam1-4/+4
The adreno_is_a20x() and adreno_is_a225() functions rely on the GPU revision, but such information is retrieved inside adreno_gpu_init(), which is called afterwards. Fix this problem by caling adreno_gpu_init() earlier, so that the GPU information revision is available when adreno_is_a20x() and adreno_is_a225() run. Tested on a imx53-qsb board. Fixes: 21af872cd8c6 ("drm/msm/adreno: add a2xx") Signed-off-by: Fabio Estevam <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/543456/ Signed-off-by: Rob Clark <[email protected]>
2023-08-07drm/msm/a6xx: Fix up GMU region reservationsKonrad Dybcio1-4/+4
Change the order of region allocations to make the addresses match downstream. This shouldn't matter very much, but helps eliminate one more difference when comparing register accesses. Also, make the log region 16K long. That's what it is, unconditionally on A6xx and A7xx. Signed-off-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/543338/ Signed-off-by: Rob Clark <[email protected]>
2023-08-07drm/msm/a6xx: Improve GMU force shutdown sequenceKonrad Dybcio1-0/+7
The GMU force shutdown sequence involves some additional register cleanup which was not implemented previously. Do so. Signed-off-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/543340/ Signed-off-by: Rob Clark <[email protected]>
2023-08-07drm/msm/a6xx: Ensure clean GMU state in a6xx_gmu_fw_startKonrad Dybcio1-0/+6
While it's not very well understood, there is some sort of a fault handler implemented in the GMU firmware which triggers when a certain bit is set, resulting in the M3 core not booting up the way we expect it to. Write a magic value to a magic register to hopefully prevent that from happening. Signed-off-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/543335/ Signed-off-by: Rob Clark <[email protected]>
2023-08-07drm/msm/a6xx: Skip empty protection ranges entriesKonrad Dybcio1-2/+5
Some specific SKUs leave certain protection range registers empty. Allow for that behavior. Signed-off-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/543334/ Signed-off-by: Rob Clark <[email protected]>
2023-08-07drm/msm/a6xx: Use descriptive bitfield names for CP_PROTECT_CNTLKonrad Dybcio1-1/+4
We have the necessary information, so explain which bit does what. Signed-off-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/543332/ Signed-off-by: Rob Clark <[email protected]>
2023-08-07drm/msm/a6xx: Add some missing header definitionsKonrad Dybcio2-0/+5
Add a definition of the GMU_AHB_FENCE_STATUS_CLR reg and CP_PROTECT_CNTL bitfields. This may be substituted with a mesa header sync. Signed-off-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/543330/ Signed-off-by: Rob Clark <[email protected]>
2023-08-07drm/msm/a6xx: Fix misleading commentRob Clark1-2/+2
The range is actually len+1. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Akhil P Oommen <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/545099/
2023-08-07drm/msm/adreno: Switch to chip-id for identifying GPURob Clark7-105/+115
Since the revision becomes an opaque identifier with future GPUs, move away from treating different ranges of bits as having a given meaning. This means that we need to explicitly list different patch revisions in the device table. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/549782/
2023-08-07dt-bindings: drm/msm/gpu: Extend bindings for chip-idRob Clark1-0/+6
Upcoming GPUs use an opaque chip-id for identifying the GPU. Signed-off-by: Rob Clark <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/549778/
2023-08-07drm/msm/adreno: Move adreno info to configRob Clark4-17/+8
Let's just stash it in adreno_platform_config rather than looking it up in N different places. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/549777/
2023-08-07drm/msm/adreno: Add helper for formating chip-idRob Clark3-16/+17
This is used in a few places, including one that is parsed by userspace tools. So let's standardize it a bit better. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/549774/
2023-08-07drm/msm/adreno: Add adreno familyRob Clark3-18/+70
Sometimes it is useful to know the sub-generation (or "family"). And in any case, this helps us get away from infering the generation from the numerical chip-id. v2: Fix is_a2xx() typo Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/549773/
2023-08-07drm/msm/adreno: Bring the a630 family togetherRob Clark2-5/+6
All of these are derivatives of a630. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/549770/
2023-08-07drm/msm/adreno: Move speedbin mapping to device tableRob Clark3-155/+97
This simplifies the code. v2: Use a table of structs instead of flat uint32_t[] Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/549769/
2023-08-07drm/msm/adreno: Allow SoC specific gpu device table entriesRob Clark2-4/+31
There are cases where there are differences due to SoC integration. Such as cache-coherency support, and (in the next patch) e-fuse to speedbin mappings. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/549767/
2023-08-07drm/msm/adreno: Use quirk to identify cached-coherent supportRob Clark2-7/+17
It is better to explicitly list it. With the move to opaque chip-id's for future devices, we should avoid trying to infer things like generation from the numerical value. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/549765/
2023-08-07drm/msm/adreno: Use quirk identify hw_aprivRob Clark3-2/+6
Rather than just open coding a list of gpu-id matches. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/549764/
2023-08-07drm/msm/adreno: Remove redundant revn paramRob Clark3-16/+9
This just duplicates what is in adreno_info, and can cause confusion if used before it is set. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/549761/
2023-08-07drm/msm/adreno: Remove redundant gmem size paramRob Clark5-8/+8
Even in the ocmem case, the allocated ocmem buffer size should match the requested size. v2: Move stray hunk to previous patch, make OCMEM size mismatch an error condition. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/549759/
2023-08-07drm/msm/adreno: Remove GPU nameRob Clark3-34/+5
No real need to have marketing names in the kernel. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/549757/
2023-08-07Merge branch 'msm-fixes' into msm-nextRob Clark8-12/+37
Back-merge msm-fixes to resolve conflicts. Signed-off-by: Rob Clark <[email protected]>
2023-08-04drm/msm/dpu: fix the irq index in dpu_encoder_phys_wb_wait_for_commit_doneDmitry Baryshkov1-1/+2
Since commit 1e7ac595fa46 ("drm/msm/dpu: pass irq to dpu_encoder_helper_wait_for_irq()") the dpu_encoder_phys_wb_wait_for_commit_done expects the IRQ index rather than the IRQ index in phys_enc->intr table, however writeback got the older invocation in place. This was unnoticed for several releases, but now it's time to fix it. Fixes: d7d0e73f7de3 ("drm/msm/dpu: introduce the dpu_encoder_phys_* for writeback") Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/550924/ Link: https://lore.kernel.org/r/[email protected]
2023-08-04drm/msm/dpu: initialise clk_rate to 0 in _dpu_core_perf_get_core_clk_rateDmitry Baryshkov1-0/+1
When removing the core perf tune overrides, I also occasionaly removed the initialisation of the clk_rate variable. Initialise it to 0 to let max() correctly calculate the maximum of requested clock rates. Reported-by: Dan Carpenter <[email protected]> Fixes: 6a4bc73915af ("drm/msm/dpu: drop separate dpu_core_perf_tune overrides") Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/551321/ Link: https://lore.kernel.org/r/[email protected]
2023-08-04drm/msm/dpu: clean up some inconsistent indentingJiapeng Chong1-3/+3
No functional modification involved. drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c:183 dpu_core_perf_crtc_check() warn: inconsistent indenting. Reported-by: Abaci Robot <[email protected]> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=6096 Signed-off-by: Jiapeng Chong <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/551313/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
2023-08-04drm/msm/mdp5: Don't leak some plane stateDaniel Vetter1-2/+1
Apparently no one noticed that mdp5 plane states leak like a sieve ever since we introduced plane_state->commit refcount a few years ago in 21a01abbe32a ("drm/atomic: Fix freeing connector/plane state too early by tracking commits, v3.") Fix it by using the right helpers. Fixes: 21a01abbe32a ("drm/atomic: Fix freeing connector/plane state too early by tracking commits, v3.") Cc: Maarten Lankhorst <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Rob Clark <[email protected]> Cc: Abhinav Kumar <[email protected]> Cc: Dmitry Baryshkov <[email protected]> Cc: [email protected] Cc: [email protected] Reported-and-tested-by: [email protected] Cc: [email protected] Signed-off-by: Daniel Vetter <[email protected]> Reviewed-by: Rob Clark <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/551236/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
2023-08-04drm/msm/dpu: Drop encoder vsync_eventJessica Zhang2-87/+1
Drop vsync_event and vsync_event_work handlers as they are unnecessary. In addition drop the dpu_enc_ktime_template event class as it will be unused after the vsync_event handlers are dropped. Signed-off-by: Jessica Zhang <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/550983/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
2023-08-03drm/msm/dpu: fix DSC 1.2 enc subblock lengthDmitry Baryshkov1-2/+2
Both struct dpu_dsc_sub_blks instances declare enc subblock length to be 0x100, while the actual length is 0x9c (last register having offset 0x98). Reduce subblock length to remove the empty register space from being dumped. Fixes: 0d1b10c63346 ("drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets") Reviewed-by: Abhinav Kumar <[email protected]> Reviewed-by: Marijn Suijten <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/550999/ Link: https://lore.kernel.org/r/[email protected]
2023-08-03drm/msm/dpu: fix DSC 1.2 block lengthsDmitry Baryshkov5-19/+19
All DSC_BLK_1_2 declarations incorrectly pass 0x29c as the block length. This includes the common block itself, enc subblocks and some empty space around. Change that to pass 0x4 instead, the length of common register block itself. Fixes: 0d1b10c63346 ("drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets") Reported-by: Ryan McCann <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Marijn Suijten <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/550998/ Link: https://lore.kernel.org/r/[email protected]
2023-08-03drm/msm/dpu: increase memtype count to 16 for sm8550Jonathan Marek2-2/+22
sm8550 has 16 vbif clients. This fixes the extra 2 clients (DMA4/DMA5) not having their memtype initialized. This fixes DMA4/DMA5 planes not displaying correctly. Fixes: efcd0107727c ("drm/msm/dpu: add support for SM8550") Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Tested-by: Neil Armstrong <[email protected]> # on SM8550-QRD Patchwork: https://patchwork.freedesktop.org/patch/550968/ Link: https://lore.kernel.org/r/[email protected] [DB: fixed the Fixes tag] Signed-off-by: Dmitry Baryshkov <[email protected]>
2023-08-02drm/msm/dpu: drop dpu_core_perf_destroy()Dmitry Baryshkov3-17/+0
This function does nothing, just clears one struct field. Drop it now. Acked-by: Konrad Dybcio <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/550210/ Link: https://lore.kernel.org/r/[email protected]
2023-08-02drm/msm/dpu: move max clock decision to dpu_kms.Dmitry Baryshkov3-17/+15
dpu_core_perf should not make decisions on the maximum possible core clock rate. Pass the value from dpu_kms_hw_init() and drop handling of core_clk from dpu_core_perf.c Reviewed-by: Abhinav Kumar <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/550201/ Link: https://lore.kernel.org/r/[email protected]
2023-08-02drm/msm/dpu: remove extra clk_round_rate() callDmitry Baryshkov1-2/+0
The dev_pm_opp_set_rate() already contains a call for clk_round_rate for the passed value. Stop calling it manually from _dpu_core_perf_get_core_clk_rate(). It is slightly incorrect to call it this way, as we should round the final calculated clock rate rather than rounding all the intermediate values. Reviewed-by: Abhinav Kumar <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/550212/ Link: https://lore.kernel.org/r/[email protected]
2023-08-02drm/msm/dpu: remove unused fields from struct dpu_core_perfDmitry Baryshkov3-10/+1
Remove dpu_core_perf::dev and dpu_core_perf::debugfs_root fields, they are not used by the code. Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/550200/ Link: https://lore.kernel.org/r/[email protected]
2023-08-02drm/msm/dpu: use dpu_perf_cfg in DPU core_perf codeDmitry Baryshkov3-48/+35
Simplify dpu_core_perf code by using only dpu_perf_cfg instead of using full-featured catalog data. Acked-by: Konrad Dybcio <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/550198/ Link: https://lore.kernel.org/r/[email protected]
2023-08-02drm/msm/dpu: drop the dpu_core_perf_crtc_update()'s stop_req paramDmitry Baryshkov3-11/+10
The stop_req is true only in the dpu_crtc_disable() case, when crtc->enable has already been set to false. This renders the stop_req argument useless. Remove it completely. Reviewed-by: Abhinav Kumar <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/550206/ Link: https://lore.kernel.org/r/[email protected]
2023-08-02drm/msm/dpu: rework indentation in dpu_core_perfDmitry Baryshkov1-6/+4
dpu_core_perf.c contains several multi-line conditions which are hard to comprehent because of the indentation. Rework the identation of these conditions to make it easier to understand them. Reviewed-by: Abhinav Kumar <[email protected]> Acked-by: Konrad Dybcio <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/550197/ Link: https://lore.kernel.org/r/[email protected]
2023-08-02drm/msm/dpu: drop separate dpu_core_perf_tune overridesDmitry Baryshkov2-20/+11
The values in struct dpu_core_perf_tune are fixed per the core perf mode. Drop the 'tune' values and substitute them with known values when performing perf management. Note: min_bus_vote was not used at all, so it is just silently dropped. Reviewed-by: Abhinav Kumar <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/550208/ Link: https://lore.kernel.org/r/[email protected]
2023-08-02drm/msm/dpu: bail from _dpu_core_perf_crtc_update_bus if there are no ICC pathsDmitry Baryshkov1-3/+3
Skip bandwidth aggregation and return early if there are no interconnect paths defined for the DPU device. Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/550195/ Link: https://lore.kernel.org/r/[email protected]
2023-08-02drm/msm/dpu: drop enum dpu_core_perf_data_bus_idDmitry Baryshkov1-13/+0
Drop the leftover of bus-client -> interconnect conversion, the enum dpu_core_perf_data_bus_id. Fixes: cb88482e2570 ("drm/msm/dpu: clean up references of DPU custom bus scaling") Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/550194/ Link: https://lore.kernel.org/r/[email protected]
2023-08-02drm/msm/dpu: drop BWC features from DPU_MDP_foo namespaceDmitry Baryshkov1-7/+0
The feature bits DPU_MDP_BWC, DPU_MDP_UBWC_1_0, and DPU_MDP_UBWC_1_5 are not used by the driver, drop them completely. Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/550056/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
2023-08-02drm/msm/dpu: drop UBWC configurationDmitry Baryshkov17-128/+0
As the DPU driver has switched to fetching data from MDSS driver, we can now drop the UBWC and highest_bank_bit parts of the DPU hw catalog. Reviewed-by: Abhinav Kumar <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/550058/ Link: https://lore.kernel.org/r/[email protected]
2023-08-02drm/msm/dpu: use MDSS data for programming SSPPDmitry Baryshkov6-13/+33
Switch to using data from MDSS driver to program the SSPP fetch and UBWC configuration. As a side-effect, this also swithes the DPU driver from DPU_HW_UBWC_VER_xx values to the UBWC_x_y enum, which reflects the hardware register values. Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/550054/ Link: https://lore.kernel.org/r/[email protected]
2023-08-02drm/msm/mdss: populate missing dataDmitry Baryshkov1-2/+19
As we are going to use MDSS data for DPU programming, populate missing MDSS data. The UBWC 1.0 and no UBWC cases do not require MDSS programming, so skip them. Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/550055/ Link: https://lore.kernel.org/r/[email protected]
2023-08-02drm/msm/mdss: export UBWC dataDmitry Baryshkov2-17/+40
DPU programming requires knowledge of some of UBWC parameters. This results in duplication of UBWC data between MDSS and DPU drivers. Export the required data from MDSS driver. Reviewed-by: Abhinav Kumar <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/550052/ Link: https://lore.kernel.org/r/[email protected]
2023-08-02drm/msm/mdss: rename ubwc_version to ubwc_enc_versionDmitry Baryshkov1-15/+15
Rename the ubwc_version field to ubwc_enc_version, it denotes the version of the UBWC encoder, not the "UBWC version". Reviewed-by: Abhinav Kumar <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/550051/ Link: https://lore.kernel.org/r/[email protected]
2023-08-02drm/msm/mdss: correct UBWC programming for SM8550Dmitry Baryshkov1-2/+17
The SM8550 platform employs newer UBWC decoder, which requires slightly different programming. Fixes: a2f33995c19d ("drm/msm: mdss: add support for SM8550") Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/550049/ Link: https://lore.kernel.org/r/[email protected]
2023-08-02drm/msm/dpu: drop compatibility INTR definesDmitry Baryshkov6-22/+9
While reworking interrupts masks, it was easier to keep old MDP_INTFn_7xxx_INTR and MDP_INTFn_7xxx_TEAR_INTR symbols. Now it is time to drop them and use unified symbol names. Reviewed-by: Neil Armstrong <[email protected]> Reviewed-by: Marijn Suijten <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/549656/ Link: https://lore.kernel.org/r/[email protected]
2023-08-02drm/msm/dpu: drop now-unused mdss_irqs field from hw catalogDmitry Baryshkov17-135/+0
Now as the list of the interrupts is constructed from the catalog data, drop the mdss_irqs field from catalog. Reviewed-by: Neil Armstrong <[email protected]> Reviewed-by: Marijn Suijten <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/549659/ Link: https://lore.kernel.org/r/[email protected]
2023-08-02drm/msm/dpu: autodetect supported interruptsDmitry Baryshkov2-1/+18
Declaring the mask of supported interrupts proved to be error-prone. It is very easy to add a bit with no corresponding backing block or to miss the INTF TE bit. Replace this with looping over the enabled INTF blocks to setup the irq mask. Reviewed-by: Marijn Suijten <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/549654/ Link: https://lore.kernel.org/r/[email protected]
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