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2018-05-18drm/etnaviv: switch MMU page tables to writecombine memoryLucas Stach2-59/+49
We are likely to write multiple page entries at once and already ensure proper write buffer flushing before GPU submit, so this improves CPU time usage in the submit path without any downsides. Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Philipp Zabel <[email protected]>
2018-05-18drm/etnaviv: remove register loggingLucas Stach5-67/+5
I'm not aware of any case where tracing GPU register manipulation at the kernel level would have been useful. It only adds more indirections and adds to the code size. Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
2018-05-18drm/etnaviv: remove cycling through MMU address spaceLucas Stach2-16/+1
This was useful on MMUv1 GPUs, which don't generate proper faults, when the GPU write caches weren't fully understood and not properly handled by the kernel driver. As this has been fixed for quite some time, the cycling though the MMU address space needlessly spreads out the MMU mappings. Signed-off-by: Lucas Stach <[email protected]>
2018-05-18drm/etnaviv: correct timeout calculationRussell King1-8/+17
The old way did clamp the jiffy conversion and thus caused the timeouts to become negative after some time. Also it didn't work with userspace which actually fills the upper 32bits of the 64bit timestamp value. clock_gettime() is 32-bit on 32-bit architectures. Using 64-bit timespec math, like we do in this commit, means that when a wrap occurs, the specified timeout goes into the past and we can't request a timeout in the future. As the Linux implementation of CLOCK_MONOTONIC is reasonable and starts at 0, the first such timer wrap will occur after approx. 68 years of system uptime. Signed-off-by: Russell King <[email protected]> Signed-off-by: Lucas Stach <[email protected]>
2018-05-18gpu: host1x: Fix compiler errors by converting to dma_addr_tEmil Goode2-2/+2
The compiler is complaining with the following errors: drivers/gpu/host1x/cdma.c:94:48: error: passing argument 3 of ‘dma_alloc_wc’ from incompatible pointer type [-Werror=incompatible-pointer-types] drivers/gpu/host1x/cdma.c:113:48: error: passing argument 3 of ‘dma_alloc_wc’ from incompatible pointer type [-Werror=incompatible-pointer-types] The expected pointer type of the third argument to dma_alloc_wc() is dma_addr_t but phys_addr_t is passed. Change the phys member of struct push_buffer to be dma_addr_t so that we pass the correct type to dma_alloc_wc(). Also check pb->mapped for non-NULL in the destroy function as that is the right way of checking if dma_alloc_wc() was successful. Signed-off-by: Emil Goode <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2018-05-18Merge branch 'linux-4.18' of git://github.com/skeggsb/linux into drm-nextDave Airlie322-7999/+15430
The main thing here is the addition of support for Volta GV100 GPUs, everything else basically restructuring display / graphics init code to make it possible to fit Volta support in more nicely. There's a bunch of improvements/fixes scattered in there for earlier GPUs too, particularly graphics engine init on all GPUs from Fermi onwards. Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/CACAvsv7sjDKyR43n+6=iLC+ExGhBTLRLdKqwrhcfJWjEAndK0g@mail.gmail.com
2018-05-18drm/nouveau/gr/gf100-: insert some WFIs during gr initBen Skeggs2-0/+6
Inserted wait-for-gr-idle in the places it seems that RM does it, seems to prevent some random mmio timeouts on Quadro GV100. Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/clk: Use list_for_each_entry_from_reverseArushi Singhal1-6/+4
It's better to use "list_for_each_entry_from_reverse" for iterating list than "for loop" as it makes the code more clear to read. This patch replace "for loop" with "list_for_each_entry_from_reverse" and "start" variable with "cstate" which helps in refactoring the code and also "cstate" variable is more commonly used in the other functions. changes in v2: "start" variable is removed, before "cstate" variable was removed but "cstate" is more common so preferred "cstate" over "start". Signed-off-by: Arushi Singhal <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau: fix temp/pwm visibility, skip hwmon when no sensors existIlia Mirkin1-3/+13
A NV34 GPU was seeing temp and pwm entries in hwmon, which would error out when read. These should not have been visible, but also the whole hwmon object should just not have been registered in the first place. Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau: fix nouveau_dsm_get_client_id()'s return typeLuc Van Oostenryck1-1/+1
The method struct vga_switcheroo_handler::get_client_id() is defined as returning an 'enum vga_switcheroo_client_id' but the implementation in this driver, nouveau_dsm_get_client_id(), returns an 'int'. Fix this by returning 'enum vga_switcheroo_client_id' in this driver too. Signed-off-by: Luc Van Oostenryck <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau: fix mode_valid's return typeLuc Van Oostenryck1-1/+1
The method struct drm_connector_helper_funcs::mode_valid is defined as returning an 'enum drm_mode_status' but the driver implementation for this method uses an 'int' for it. Fix this by using 'enum drm_mode_status' in the driver too. Signed-off-by: Luc Van Oostenryck <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/gr/gv100: initial supportBen Skeggs12-3/+395
Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/ce/gv100: initial supportBen Skeggs6-0/+54
Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/fifo/gv100: initial supportBen Skeggs21-11/+779
Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/kms/gv100: initial supportBen Skeggs21-7/+918
Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/disp/gv100: initial supportBen Skeggs26-9/+1544
Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/dma/gv100: initial supportBen Skeggs6-0/+159
Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/therm/gv100: initial supportBen Skeggs1-0/+1
Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/pmu/gv100: initial supportBen Skeggs1-0/+1
Appears to be compatible with GP102. Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/fault/gv100: initial supportBen Skeggs4-1/+213
Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/bar/gv100: initial supportBen Skeggs1-0/+1
Appears to be compatible with GM107. Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/mmu/gv100: initial supportBen Skeggs6-0/+137
VEID support hacked in here, as it's the most convenient place for now. Will be refined once it's better understood. Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/ltc/gv100: initial supportBen Skeggs1-0/+1
Appears to be compatible with GP102. Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/fb/gv100: initial supportBen Skeggs6-1/+52
Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/imem/gv100: initial supportBen Skeggs1-0/+1
Can't imagine this will be any different. Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/tmr/gv100: initial supportBen Skeggs1-0/+1
Appears to be compatible with GK20A. Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/bus/gv100: initial supportBen Skeggs1-0/+1
Appears to be compatible with GF100. Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/mc/gv100: initial supportBen Skeggs1-0/+1
Appears to be compatible with GP100. Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/fuse/gv100: initial supportBen Skeggs1-0/+1
Appears to be compatible with GM107. Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/i2c/gv100: initial supportBen Skeggs1-0/+1
Appears to be compatible with GM200. Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/gpio/gv100: initial supportBen Skeggs1-0/+1
Appears to be compatible with GK104. Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/ibus/gv100: initial supportBen Skeggs1-0/+1
Appears to be compatible with GM200. Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/top/gv100: initial supportBen Skeggs2-1/+3
Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/devinit/gv100: initial supportBen Skeggs6-1/+85
Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/bios/pll: limits table 5.0Ben Skeggs1-1/+18
Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/bios/gv100: initial supportBen Skeggs2-1/+5
No real surprises here so far. Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/pci/gv100: initial supportBen Skeggs1-0/+1
Appears to be compatible with GP100. Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/core: recognise gv100Ben Skeggs5-0/+11
Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/core: increase maximum number of copy engines to 9Ben Skeggs3-3/+15
Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/kms/nv50-: initial overlay supportBen Skeggs16-15/+364
Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/kms/gk104-: add support for [XA]2R10G10B10 formatsBen Skeggs6-3/+57
Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/kms/gk104-: support additional cursor sizesBen Skeggs7-16/+65
Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/kms/nv50-: separate blocklinear vs linear pitchBen Skeggs8-17/+28
Will be required to support Volta. Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/kms/nv50-: handle degamma LUT from window channelsBen Skeggs17-171/+462
Required to eventually support DRM colour management APIs, and to support Volta. Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/kms/nv50-: plane updates don't always require image_set()Ben Skeggs2-32/+32
When only the position of a window changes, there's no need to submit an image update as well. Will be required to support the overlays, and Volta windows. Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/kms/nv50-: store window visibility in stateBen Skeggs2-8/+21
Window visibility is going to become a little more complicated with the upcoming LUT changes, so store the calculated value to avoid needing to recalculate the armed state again. Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/kms/nv50-: simplify swap interval handlingBen Skeggs2-9/+3
This is just cleaning up some left-overs from when we needed a custom legacy page flip implementation. Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/kms/nv50-: decouple window state changes, and update method ↵Ben Skeggs2-4/+16
submisssion This will be required to support Volta. Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/kms/nv50-: simplify tracking of channel interlocksBen Skeggs20-86/+224
Instead of windows returning their core channel interlock mask if they know core has been modified, it's recorded unconditionally and used if required when update methods are emitted. This will be required to support Volta. Signed-off-by: Ben Skeggs <[email protected]>
2018-05-18drm/nouveau/kms/nv50-: determine MST support from DP Info TableBen Skeggs3-3/+12
GV100 doesn't support MST, use the information provided in VBIOS tables to detect its presence instead. Signed-off-by: Ben Skeggs <[email protected]>
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