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2022-03-15dt-bindings: pinctrl: qcom: Add sc8280xp TLMM bindingBjorn Andersson1-0/+151
The Qualcomm SC8280XP platform contains a single block of registers for the TLMM block. This provides pinconf and pinmux for 228 GPIOs, 2 UFS_RESET pins and one SDC interface. Signed-off-by: Bjorn Andersson <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15pinctrl: microchip-sgpio: wait until output is actually setMichael Walle1-1/+68
Right now, when a gpio value is set, the actual hardware pin gets set asynchronously. When linux write the output register, it takes some time until it is actually propagated to the output shift registers. If that output port is connected to an I2C mux for example, the linux driver assumes the I2C bus is already switched although it is not. Fortunately, there is a single shot mode with a feedback: you can trigger the single shot and the hardware will clear that bit once it has finished the clocking and strobed the load signal of the shift registers. This can take a considerable amount of time though. Measuremens have shown that it takes up to a whole burst cycle gap which is about 50ms on the largest setting. Therefore, we have to mark the output bank as sleepable. To avoid unnecessary waiting, just trigger the single shot if the value was actually changed. Signed-off-by: Michael Walle <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15pinctrl: microchip-sgpio: return error in spgio_output_set()Michael Walle1-8/+8
Make sgpio_output_set() return an error value. Don't just ignore the return value of any regmap access but propagate it to our callers. Even if the accesses never fail, this is a preparation patch to add single shot mode where we need to poll a bit and thus we might get -ETIMEDOUT. Signed-off-by: Michael Walle <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15pinctrl: microchip-sgpio: use regmap_update_bits()Michael Walle1-11/+4
Convert sgpio_clrsetbits() to use regmap_update_bits() and drop the spinlocks because regmap already takes care of the locking. Signed-off-by: Michael Walle <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15pinctrl: microchip-sgpio: don't do RMW for interrupt ack registerMichael Walle1-1/+8
The interrupt ack register has the usual "write one to clear" semantics. No read-modify-write is required here. This is also a preparation patch to change the sgpio_clrsetbits() to use regmap_update_bits() which don't write the value if it is not changed. Signed-off-by: Michael Walle <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15pinctrl: microchip-sgpio: lock RMW accessMichael Walle1-0/+15
Protect any RMW access to the registers by a spinlock. Fixes: 7e5ea974e61c ("pinctrl: pinctrl-microchip-sgpio: Add pinctrl driver for Microsemi Serial GPIO") Signed-off-by: Michael Walle <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15pinctrl: ocelot: Fix interrupt parsingHoratiu Vultur1-2/+2
In the blamed commit, it removes the duplicate of_node assignment in the driver. But the driver uses this before calling into of_gpio_dev_init to determine if it needs to assign an IRQ chip to the GPIO. The fixes consists in using the platform_get_irq_optional Fixes: 8a8d6bbe1d3bc7 ("pinctrl: Get rid of duplicate of_node assignment in the drivers") Signed-off-by: Horatiu Vultur <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15pinctrl: imx: Reduce printk message level for empty nodesAlexander Stein1-1/+1
iomuxc_snvs from imx6ull supports 2 boot mode and 10 tamper pins. Probably most users won't use them, causing this error message during boot: no groups defined in /soc/bus@2200000/iomuxc-snvs@2290000 This is actually not an error in this case, so reduce the level accordingly. Signed-off-by: Alexander Stein <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15pinctrl: zynq: use module_platform_driver to simplify the codeSrinivas Neeli1-5/+2
module_platform_driver() makes the code simpler by eliminating boilerplate code. Signed-off-by: Srinivas Neeli <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15pinctrl: qcom: cleanup commentsTom Rix2-3/+3
Add leading space to spdx tag Replacements voilates to violates sepearte to separate Signed-off-by: Tom Rix <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15dt-bindings: pinctrl: mt8195: Add mediatek,drive-strength-adv propertyTinghan Shen1-0/+35
Extend driving support for I2C pins on SoC mt8195. This property is already documented in mediatek,mt8183-pinctrl.yaml. Signed-off-by: Tinghan Shen <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15pinctrl: mediatek: pinctrl-mtk-common: Simplify with dev_err_probe()AngeloGioacchino Del Regno1-14/+11
Use the dev_err_probe() helper to simplify error handling during probe. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15pinctrl: mediatek: pinctrl-paris: Simplify with dev_err_probe()AngeloGioacchino Del Regno1-12/+7
Use the dev_err_probe() helper to simplify error handling during probe. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15pinctrl: mediatek: pinctrl-moore: Simplify with dev_err_probe()AngeloGioacchino Del Regno1-16/+9
Use the dev_err_probe() helper to simplify error handling during probe. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15pinctrl: mediatek: paris: Support generic PIN_CONFIG_DRIVE_STRENGTH_UAChen-Yu Tsai1-0/+99
Some of the MediaTek chips that utilize the Paris pinctrl driver library support a lower drive strength (<= 1mA) than the standard drive strength settings (2~16 mA) on certain pins. This was previously supported by the custom MTK_PIN_CONFIG_DRV_ADV parameter along with the "mediatek,drive-strength-adv" device tree property. The drive strength values for this hardware are 125, 250, 500, and 1000 mA, and can be readily described by the existing "drive-strength-microamp" property, which then gets parsed by the generic pinconf library into the parameter PIN_CONFIG_DRIVE_STRENGTH_UA. Add support for PIN_CONFIG_DRIVE_STRENGTH_UA while keeping the old custom parameter around for backward compatibility. Signed-off-by: Chen-Yu Tsai <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15pinctrl: mediatek: paris: Rework mtk_pinconf_{get,set} switch/case logicChen-Yu Tsai1-83/+61
The current code deals with optional features by testing for the function pointers and returning -ENOTSUPP if it is not valid. This is done for multiple pin config settings and results in the code that handles the supporting cases to get indented by one level. This is aggrevated by the fact that some features require another level of conditionals. Instead of assigning the same error code in all unsupported optional feature cases, simply have that error code as the default, and break out of the switch/case block whenever a feature is unsupported, or an error is returned. This reduces indentation by one level for the useful code. Also replace the goto statements with break statements. The result is the same, as the gotos simply exit the switch/case block, which can also be achieved with a break statement. With the latter the intent is clear and easier to understand. Signed-off-by: Chen-Yu Tsai <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15pinctrl: mediatek: paris: Skip custom extra pin config dump for virtual GPIOsChen-Yu Tsai1-0/+3
Virtual GPIOs do not have any hardware state associated with them. Any attempt to read back hardware state for these pins result in error codes. Skip dumping extra pin config information for these virtual GPIOs. Fixes: 184d8e13f9b1 ("pinctrl: mediatek: Add support for pin configuration dump via debugfs.") Signed-off-by: Chen-Yu Tsai <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15pinctrl: mediatek: paris: Drop extra newline in mtk_pctrl_show_one_pin()Chen-Yu Tsai1-8/+4
The caller of mtk_pctrl_show_one_pin() is responsible for printing the full line. mtk_pctrl_show_one_pin(), called through mtk_pctrl_dbg_show(), should only produce a string containing the extra information the driver wants included. Drop the extra newlines. Also unbreak the line that is only slightly over 80 characters to make it easier on the eye, and get rid of the braces now that each block in the conditionals is just one line. Fixes: 184d8e13f9b1 ("pinctrl: mediatek: Add support for pin configuration dump via debugfs.") Fixes: fb34a9ae383a ("pinctrl: mediatek: support rsel feature") Signed-off-by: Chen-Yu Tsai <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15pinctrl: mediatek: paris: Fix pingroup pin config state readbackChen-Yu Tsai1-5/+3
mtk_pconf_group_get(), used to read back pingroup pin config state, simply returns a set of configs saved from a previous invocation of mtk_pconf_group_set(). This is an unfiltered, unvalidated set passed in from the pinconf core, which does not match the current hardware state. Since the driver library is designed to have one pin per group, pass through mtk_pconf_group_get() to mtk_pinconf_get(), to read back the current pin config state of the only pin in the group. Also drop the assignment of pin config state to the group. Fixes: 805250982bb5 ("pinctrl: mediatek: add pinctrl-paris that implements the vendor dt-bindings") Signed-off-by: Chen-Yu Tsai <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15pinctrl: mediatek: paris: Fix "argument" argument type for mtk_pinconf_get()Chen-Yu Tsai1-2/+1
For mtk_pinconf_get(), the "argument" argument is typically returned by pinconf_to_config_argument(), which holds the value for a given pinconf parameter. It certainly should not have the type of "enum pin_config_param", which describes the type of the pinconf parameter itself. Change the type to u32, which matches the return type of pinconf_to_config_argument(). Fixes: 805250982bb5 ("pinctrl: mediatek: add pinctrl-paris that implements the vendor dt-bindings") Signed-off-by: Chen-Yu Tsai <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15pinctrl: mediatek: paris: Fix PIN_CONFIG_BIAS_* readbackChen-Yu Tsai1-10/+6
When reading back pin bias settings, if the pin is not in the corresponding bias state, the function should return -EINVAL. Fix this in the mediatek-paris pinctrl library so that the read back state is not littered with bogus a "input bias disabled" combined with "pull up" or "pull down" states. Fixes: 805250982bb5 ("pinctrl: mediatek: add pinctrl-paris that implements the vendor dt-bindings") Signed-off-by: Chen-Yu Tsai <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15pinctrl: pinconf-generic: Print arguments for bias-pull-*Chen-Yu Tsai1-3/+3
The bias-pull-* properties, or PIN_CONFIG_BIAS_PULL_* pin config parameters, accept optional arguments in ohms denoting the strength of the pin bias. Print these values out in debugfs as well. Fixes: eec450713e5c ("pinctrl: pinconf-generic: Add flag to print arguments") Signed-off-by: Chen-Yu Tsai <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Tested-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15pinctrl: mediatek: Fix missing of_node_put() in mtk_pctrl_initMiaoqian Lin1-0/+2
The device_node pointer is returned by of_parse_phandle() with refcount incremented. We should use of_node_put() on it when done. Fixes: a6df410d420a ("pinctrl: mediatek: Add Pinctrl/GPIO driver for mt8135.") Signed-off-by: Miaoqian Lin <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15pinctrl: nuvoton: Add driver for WPCM450Jonathan Neuschäfer5-1/+1171
This driver is based on the one for NPCM7xx, because the WPCM450 is a predecessor of those SoCs. Notable differences: - On WPCM450, the GPIO registers are not organized in multiple banks, but rather placed continually into the same register block. This affects how register offsets are computed. - Pinmux nodes can explicitly select GPIO mode, whereas in the npcm7xx driver, this happens automatically when a GPIO is requested. Some functionality implemented in the hardware was (for now) left unused in the driver, specifically blinking and pull-up/down. Signed-off-by: Jonathan Neuschäfer <[email protected]> Reported-by: kernel test robot <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15dt-bindings: pinctrl: Add Nuvoton WPCM450Jonathan Neuschäfer1-0/+160
This binding is heavily based on the one for NPCM7xx, because the hardware is similar. There are some notable differences, however: - The addresses of GPIO banks are not physical addresses but simple indices (0 to 7), because the GPIO registers are not laid out in convenient blocks. - Pinmux settings can explicitly specify that the GPIO mode is used. Certain pins support blink patterns in hardware. This is currently not modelled in the DT binding. Signed-off-by: Jonathan Neuschäfer <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15pinctrl: ocelot: fix duplicate debugfs entryMichael Walle1-0/+1
This driver can have up to two regmaps. If the second one is registered its debugfs entry will have the same name as the first one and the following error will be printed: [ 2.242568] debugfs: Directory 'e2004064.pinctrl' with parent 'regmap' already present! Give the second regmap a name to avoid this. Fixes: 076d9e71bcf8 ("pinctrl: ocelot: convert pinctrl to regmap") Signed-off-by: Michael Walle <[email protected]> Reviewed-by: Colin Foster <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15pinctrl: ocelot: fix confops resource indexMichael Walle1-1/+1
Prior to commit ad96111e658a ("pinctrl: ocelot: combine get resource and ioremap into single call") the resource index was 1, now it is 0. But 0 is the base region for the pinctrl block. Fix it. I noticed this because there was an error that the memory region was ioremapped twice. Fixes: ad96111e658a ("pinctrl: ocelot: combine get resource and ioremap into single call") Signed-off-by: Michael Walle <[email protected]> Reviewed-by: Colin Foster <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15pinctrl: imx93: Add pinctrl driver supportJacky Bai3-0/+280
Add i.MX93 pinctrl driver Signed-off-by: Jacky Bai <[email protected]> Signed-off-by: Peng Fan <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15dt-bindings: pinctrl: imx93: Add pinctrl bindingPeng Fan1-0/+85
Add pinctrl binding doc for i.MX93 Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15pinctrl: canonical rsel resistance selection propertyGuodong Liu1-1/+1
Change "mediatek,rsel_resistance_in_si_unit" to "mediatek,rsel-resistance-in-si-unit" Fixes: fb34a9ae383a ("pinctrl: mediatek: support rsel feature") Signed-off-by: Guodong Liu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15pinctrl: add pinctrl driver on mt8186Guodong Liu4-0/+3465
This commit includes pinctrl driver for mt8186. Signed-off-by: Guodong Liu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-03-15dt-bindings: pinctrl: mt8186: add pinctrl file and binding documentGuodong Liu2-0/+1471
1. This patch adds pinctrl file for mt8186. 2. This patch adds mt8186 compatible node in binding document. Signed-off-by: Guodong Liu <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-02-28Merge tag 'intel-pinctrl-v5.18-1' of ↵Linus Walleij6-41/+689
gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v5.18-1 * Introduce support for Alder Lake-N (required to revert misplaced ID) * Add support for Raptor Lake-S * Add support for Ice Lake-N (MacBookPro16,2) * Miscellaneous fixes The following is an automated git shortlog grouped by driver: alderlake: - Add Intel Alder Lake-N pin controller support - Add Raptor Lake-S ACPI ID baytrail: - Clear direct_irq_en flag on broken configs icelake: - Add Ice Lake-N PCH pin controller support intel: - Fix a glitch when updating IRQ flags on a preconfigured line - fix unexpected interrupt Place correctly CONFIG_PINCTRL_ST in the Makefile: - Place correctly CONFIG_PINCTRL_ST in the Makefile tigerlake: - Revert "Add Alder Lake-M ACPI ID"
2022-02-27Merge tag 'renesas-pinctrl-for-v5.18-tag2' of ↵Linus Walleij32-3126/+3915
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.18 (take two) - Share more pin group data, to reduce kernel size and ease review, - Improve the pin control table validator, - Add support for the new R-Car S4-8 SoC, - Miscellaneous fixes and improvements.
2022-02-25pinctrl: renesas: r8a779f0: Add Ethernet pins, groups, and functionsGeert Uytterhoeven1-0/+288
Add pins, groups, and functions for the Ethernet Time-Sensitive Networking (TSN) interfaces on the Renesas R-Car S4-8 (R8A779F0) SoC. Based on a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/r/e0a1dc7d2435d28811e3acb361dae050eb3aabc9.1645457792.git.geert+renesas@glider.be
2022-02-25pinctrl: renesas: r8a779f0: Add QSPI pins, groups, and functionsGeert Uytterhoeven1-0/+56
Add pins, groups, and functions for the Quad SPI Controllers on the Renesas R-Car S4-8 (R8A779F0) SoC. Based on a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/r/cd7f7feeabebf268adc9e050e348230e93b40829.1645457792.git.geert+renesas@glider.be
2022-02-25pinctrl: renesas: r8a779f0: Add PCIe pins, groups, and functionGeert Uytterhoeven1-0/+27
Add pins, groups, and function for the PCIe Controllers on the Renesas R-Car S4-8 (R8A779F0) SoC. Extracted from a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/r/b2f95db490d13e8cb7d97a63d58d47933317e28a.1645457792.git.geert+renesas@glider.be
2022-02-25pinctrl: renesas: r8a779f0: Add MSIOF pins, groups, and functionsGeert Uytterhoeven1-0/+240
Add pins, groups, and function for the Clock-Synchronized Serial Interfaces with FIFO (MSIOF) on the Renesas R-Car S4-8 (R8A779F0) SoC. Based on a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/r/c625769714b1027a756dd2ed4a017eb24708a041.1645457792.git.geert+renesas@glider.be
2022-02-25pinctrl: renesas: r8a779f0: Add MMC pins, groups, and functionGeert Uytterhoeven1-0/+61
Add pins, groups, and function for the MMC interface on the Renesas R-Car S4-8 (R8A779F0) SoC. Based on a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/r/81a35c1fac4616d25501942848eb9662d477f9ef.1645457792.git.geert+renesas@glider.be
2022-02-25pinctrl: renesas: r8a779f0: Add INTC-EX pins, groups, and functionGeert Uytterhoeven1-0/+61
Add pins, groups, and function for the Interrupt Controller for External Devices (INTC-EX) on the Renesas R-Car S4-8 (R8A779F0) SoC. Based on a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/r/dc6e25da42ac4bd19ca31b5b32b43a10a0e1aa7e.1645457792.git.geert+renesas@glider.be
2022-02-25pinctrl: renesas: r8a779f0: Add HSCIF pins, groups, and functionsGeert Uytterhoeven1-0/+132
Add pins, groups, and functions for the High Speed Serial Communication Interfaces with FIFO (HSCIF) on the Renesas R-Car S4-8 (R8A779F0) SoC. Based on a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/r/2b85b8857c1189fa6ee33e2f57fe746d740481d1.1645457792.git.geert+renesas@glider.be
2022-02-25pinctrl: renesas: r8a779f0: Add I2C pins, groups, and functionsGeert Uytterhoeven1-0/+90
Add pins, groups, and functions for the I2C Bus Interfaces (I2C) on the Renesas R-Car S4-8 (R8A779F0) SoC. Extracted from a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/r/217f5b3e3888b5899c375d3cb1ec8780f6a9e19b.1645457792.git.geert+renesas@glider.be
2022-02-25pinctrl: renesas: r8a779f0: Add SCIF pins, groups, and functionsGeert Uytterhoeven1-0/+147
Add pins, groups, and functions for the Serial Communication Interfaces with FIFO (SCIF) on the Renesas R-Car S4-8 (R8A779F0) SoC. Extracted from a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/r/6369359a53483291ee536787c8a232462ff1b3a9.1645457792.git.geert+renesas@glider.be
2022-02-25pinctrl: renesas: Initial R8A779F0 PFC supportGeert Uytterhoeven5-0/+1037
Add initial Pin Function Controller (PFC) support for the Renesas R-Car S4-8 (R8A779F0) SoC, including bias, drive strength and voltage control. Based on a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <[email protected]> Acked-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/r/fd8201da404b7b0897130b254380ffc97f437266.1645457792.git.geert+renesas@glider.be
2022-02-25pinctrl: renesas: Add PORT_GP_CFG_19 macrosGeert Uytterhoeven1-2/+6
Add PORT_GP_CFG_19() and PORT_GP_19() helper macros, to be used by the r8a779f0 subdriver. Based on a larger patch in the BSP by LUU HOAI. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/r/f7fc711d065f78911bac1b616880ba3dbc858158.1645457792.git.geert+renesas@glider.be
2022-02-25dt-bindings: pinctrl: renesas,pfc: Document r8a779f0 supportLUU HOAI1-0/+1
Document Pin Function Controller (PFC) support for the Renesas R-Car S4-8 (R8A779F0) SoC. Signed-off-by: LUU HOAI <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/r/d51828853396773be2d6837f3301ac9da8b6f29e.1645457792.git.geert+renesas@glider.be
2022-02-24pinctrl: renesas: Remove unneeded #include <linux/gpio.h>Geert Uytterhoeven5-5/+0
Linus reports that some Renesas pin control sub-drivers are still including <linux/gpio.h> instead of <linux/gpio/driver.h>. As these sub-drivers don't need either, the includes can just be removed. Reported-by: Linus Walleij <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/578825d779b45af745cc7623c7f69d2ddeadac4b.1645605227.git.geert+renesas@glider.be
2022-02-24pinctrl: renesas: checker: Fix miscalculation of number of statesGeert Uytterhoeven1-2/+3
The checker failed to validate all enum IDs in the description of a register with fixed-width register fields, due to a miscalculation of the number of described states: each register field of n bits can have "1 << n" possible states, not "1". Increase SH_PFC_MAX_ENUMS accordingly, now more enum IDs are checked (SH-Mobile AG5 has more than 4000 enum IDs defined). Fixes: 12d057bad683b1c6 ("pinctrl: sh-pfc: checker: Add check for enum ID conflicts") Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/6d8a6a05564f38f9d20464c1c17f96e52740cf6a.1645460429.git.geert+renesas@glider.be
2022-02-23pinctrl: icelake: Add Ice Lake-N PCH pin controller supportAndy Shevchenko1-8/+283
This adds pinctrl/GPIO support for Intel Ice Lake-N PCH. The Ice Lake-N PCH GPIO is based on the same version of the Intel GPIO hardware than Intel Cannon Lake with different set of pins and ACPI ID. Signed-off-by: Andy Shevchenko <[email protected]> Acked-by: Mika Westerberg <[email protected]>
2022-02-23pinctrl: alderlake: Add Intel Alder Lake-N pin controller supportAndy Shevchenko1-1/+315
This change driver adds pinctrl/GPIO support for Intel Alder Lake-N SoC. The GPIO controller is based on the next generation GPIO hardware but still compatible with the one supported by the Intel core pinctrl/GPIO driver. Signed-off-by: Andy Shevchenko <[email protected]> Acked-by: Mika Westerberg <[email protected]>
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