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2022-02-22pinctrl: renesas: r8a77980: Share MMC pin group dataGeert Uytterhoeven1-21/+5
Pin groups mmc_data[14] are subsets of mmc_data8. This reduces kernel size by 40 bytes. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/32d708f423a3f0aa6c3cc87a9d5d3fa6686ab8c7.1640269757.git.geert+renesas@glider.be
2022-02-22pinctrl: renesas: r8a77970: Share MMC pin group dataGeert Uytterhoeven1-21/+5
Pin groups mmc_data[14] are subsets of mmc_data8. This reduces kernel size by 40 bytes. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/9354645f58c12a275923046fe913cfc9602ca710.1640269757.git.geert+renesas@glider.be
2022-02-22pinctrl: renesas: r8a7794: Share MMC pin group dataGeert Uytterhoeven1-20/+5
Pin groups mmc_data[14] are subsets of mmc_data8. This reduces kernel size by 40 bytes. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/ebeda8834f00ff07799cd6dc36aebae17f378e31.1640269757.git.geert+renesas@glider.be
2022-02-22pinctrl: renesas: r8a7791: Share MMC pin group dataGeert Uytterhoeven1-23/+8
Pin groups mmc_data[14] are subsets of mmc_data8. Treat mmc_data8_b the same for consistency. Note that there is no need to define 1-bit and 4-bit wide subsets for the b-variant, as they're identical to the normal variants. This reduces kernel size by 40 bytes. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/be1f11c87e51224e043291f4d8e28b620811ac76.1640269757.git.geert+renesas@glider.be
2022-02-22pinctrl: renesas: r8a7790: Share MMC pin group dataGeert Uytterhoeven1-40/+10
Pin groups mmc[01]_data[14] are subsets of mmc[01]_data8. This reduces kernel size by 80 bytes. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/0990a63016ab87d16c19097bc43d79595c0c8b87.1640269757.git.geert+renesas@glider.be
2022-02-22pinctrl: renesas: r8a7779: Share MMC pin group dataGeert Uytterhoeven1-40/+10
Pin groups mmc[01]_data[14] are subsets of mmc[01]_data8. This reduces kernel size by 80 bytes. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/3484b3cd6b4ca19788fafc01f5ead4e067275e8d.1640269757.git.geert+renesas@glider.be
2022-02-22pinctrl: renesas: r8a7778: Share MMC pin group dataGeert Uytterhoeven1-13/+5
Pin groups mmc_data[14] are subsets of mmc_data8. This reduces kernel size by 40 bytes. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/d3bf7dfda2952a0265171f82024931d490d9178a.1640269757.git.geert+renesas@glider.be
2022-02-22pinctrl: renesas: r8a77470: Share MMC pin group dataGeert Uytterhoeven1-47/+8
Pin groups mmc_data[14] and sdhi1_data[14] are subsets of mmc_data8. Pin group sdhi1_ctrl can be an alias for mmc_ctrl. This reduces kernel size by 96 bytes. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/e3d19e19f7666dbcefeec351a5096a86348404ae.1640269757.git.geert+renesas@glider.be
2022-02-22pinctrl: renesas: r8a7740: Share MMC pin group dataGeert Uytterhoeven1-38/+10
Pin groups mmc0_data[14]_[01] are subsets of mmc0_data8_[01]. This reduces kernel size by 80 bytes. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/4b15d28bb8ac24417be83b1defe0bbb908abc1e6.1640269757.git.geert+renesas@glider.be
2022-02-22pinctrl: renesas: r8a73a4: Share MMC pin group dataGeert Uytterhoeven1-38/+10
Pin groups mmc[01]_data[14] are subsets of mmc[01]_data8. This reduces kernel size by 80 bytes. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/ad30961d71631577c2bdbf8dfa4874c9585caba9.1640269757.git.geert+renesas@glider.be
2022-02-22pinctrl: renesas: sh73a0: Share LCD pin group dataGeert Uytterhoeven1-120/+16
Pin groups lcd{,2}_data{8,9,12,16,18} are subsets of lcd{,2}_data24. This reduces kernel size by 1008 bytes. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/32561ca31b590424f494351a737473200102bf8c.1640269757.git.geert+renesas@glider.be
2022-02-22pinctrl: renesas: r8a7740: Share LCD pin group dataGeert Uytterhoeven1-117/+13
Pin groups lcd0_data{8,9,12,16,18} are subsets of lcd0_data24_0. Pin groups lcd1_data{8,9,12,16,18} are subsets of lcd1_data24. This reduces kernel size by 1008 bytes. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/2018113779b3084c4175b04bb32acf2de0557a37.1640269757.git.geert+renesas@glider.be
2022-02-22pinctrl: renesas: sh73a0: Share KEYIN pin group dataGeert Uytterhoeven1-30/+6
Pin groups keysc_in[567] are subsets of keysc_in8. This reduces kernel size by 144 bytes. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/6d11be0accdaf4a42ce2a64e64201ab0670d65db.1640269757.git.geert+renesas@glider.be
2022-02-22pinctrl: renesas: r8a7791: Share HSCIF1 pin group dataGeert Uytterhoeven1-8/+1
Pin group hscif1_data_e can be an alias for hscif1_data_c. This reduces kernel size by 16 bytes. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/5afdfcaa24d41ebc50af37ff5da055203744f8b5.1640269757.git.geert+renesas@glider.be
2022-02-22pinctrl: renesas: emev2: Share CF pin group dataGeert Uytterhoeven1-13/+4
Pin group cf_data8 is a subset of cf_data16. This reduces kernel size by 64 bytes. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/370d823be136cc9ead7051915a1454252a57efc4.1640269757.git.geert+renesas@glider.be
2022-02-22pinctrl: renesas: r8a7740: Share BSC pin group dataGeert Uytterhoeven1-43/+10
Pin groups bsc_data{8,16} are subsets of bsc_data32. Pin groups bsc_rd_we{8,16} are subsets of bsc_rd_we32. This reduces kernel size by 232 bytes. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/556873f8392b1a7d1a2cf9c10abb5e6c283f11cc.1640269757.git.geert+renesas@glider.be
2022-02-22pinctrl: renesas: Add generic support for resizable busesGeert Uytterhoeven13-1163/+999
The VIN_DATA_PIN_GROUP() macro and vin_data{12,16,} unions are used to define multiple VIN data groups with different numbers of lanes, while referring to a single array of data pins, thus saving memory. However, the same feature would be useful for other resizable buses, like MMC, SDHI, QSPI, LCD, BSC, ... Rework the mechanism for generic use: - Use the new SH_PFC_PIN_GROUP_SUBSET() helper to remove the need for bus-specific unions, - Rename VIN_DATA_PIN_GROUP() to BUS_DATA_PIN_GROUP(), - Rename the macro parameters to better reflect their purposes, - Move the macro up, where it belongs. Update all individual pin control drivers for the above changes. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/cccfcfd01eb8ab7a587b084c4ddbf97293bd7291.1640269757.git.geert+renesas@glider.be
2022-02-22pinctrl: renesas: Add generic support for pin group subsetsGeert Uytterhoeven1-0/+12
It is fairly common for the pins in a pin group to be a subset of the pins in another pin group. Add a macro for defining a pin group that refers to a subset of an array of pins. This allows pin groups to share pin data, and thus save memory. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/b56c4257aee1eab698bae2cf7a08aa05775c0a77.1640269757.git.geert+renesas@glider.be
2022-02-22pinctrl: renesas: Rename SH_PFC_PIN_GROUP{,_ALIAS} argsGeert Uytterhoeven1-6/+6
Rename the arguments of the SH_PFC_PIN_GROUP_ALIAS() and SH_PFC_PIN_GROUP() macros, to better reflect their purposes. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/495fd5cd910d59489f4c1336e4a02da3679b5ffb.1640269757.git.geert+renesas@glider.be
2022-02-22pinctrl: renesas: Reformat macros defining struct initializersGeert Uytterhoeven1-61/+54
Reformat all macros that define structure initializers, to visually resemble structure definitions: - Move the opening curly brace to the previous line, - Move the closing curly brace to the first position, - Reduce indentation of the block to a single TAB, decreasing the need for line breaks, - Align backslashes for line continuation to the last TAB block where possible, Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/03a1eed3c4f57d7b14ef53ab49e04de10d0e383c.1640269757.git.geert+renesas@glider.be
2022-02-22pinctrl: renesas: Rename sh_pfc_soc_operations instancesGeert Uytterhoeven14-38/+38
Some instances of struct sh_pfc_soc_operations are called "<soc>_pfc_ops", others are called "<soc>_pinmux_ops" or just "pinmux_ops". Settle on the first variant, to avoid confusion with "struct pinmux_ops" in the pinctrl core, and to increase consistency. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/2ab33ad1d6a20a57d16922678b78810fa55b7fc0.1640269757.git.geert+renesas@glider.be
2022-02-22pinctrl: renesas: r8a77470: Reduce size for narrow VIN1 channelGeert Uytterhoeven1-2/+2
The second video-in channel on RZ/G1C has only 12 data lanes, but the pin control driver uses the vin_data union, which is meant for 24 data lanes, thus wasting space. Fix this by using the vin_data12 union instead. This reduces kernel size by 96 bytes. Fixes: 50f3f2d73e3426ba ("pinctrl: sh-pfc: Reduce kernel size for narrow VIN channels") Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/52716fa89139f6f92592633edb52804d4c5e18f0.1640269757.git.geert+renesas@glider.be
2022-02-22pinctrl: renesas: r8a7794: Add range checking to .pin_to_pocctrl()Geert Uytterhoeven1-0/+3
The .pin_to_pocctrl() implementation for R-Car E2 does not perform a full range check, unlike on all other SoCs. Add the range check, so the checker can validate better the consistency of the pin control tables. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/d23767ad7152327654192d7191f4b8ae19493966.1640269510.git.geert+renesas@glider.be
2022-02-19pinctrl: sunxi: Use unique lockdep classes for IRQsSamuel Holland1-0/+9
This driver, like several others, uses a chained IRQ for each GPIO bank, and forwards .irq_set_wake to the GPIO bank's upstream IRQ. As a result, a call to irq_set_irq_wake() needs to lock both the upstream and downstream irq_desc's. Lockdep considers this to be a possible deadlock when the irq_desc's share lockdep classes, which they do by default: ============================================ WARNING: possible recursive locking detected 5.17.0-rc3-00394-gc849047c2473 #1 Not tainted -------------------------------------------- init/307 is trying to acquire lock: c2dfe27c (&irq_desc_lock_class){-.-.}-{2:2}, at: __irq_get_desc_lock+0x58/0xa0 but task is already holding lock: c3c0ac7c (&irq_desc_lock_class){-.-.}-{2:2}, at: __irq_get_desc_lock+0x58/0xa0 other info that might help us debug this: Possible unsafe locking scenario: CPU0 ---- lock(&irq_desc_lock_class); lock(&irq_desc_lock_class); *** DEADLOCK *** May be due to missing lock nesting notation 4 locks held by init/307: #0: c1f29f18 (system_transition_mutex){+.+.}-{3:3}, at: __do_sys_reboot+0x90/0x23c #1: c20f7760 (&dev->mutex){....}-{3:3}, at: device_shutdown+0xf4/0x224 #2: c2e804d8 (&dev->mutex){....}-{3:3}, at: device_shutdown+0x104/0x224 #3: c3c0ac7c (&irq_desc_lock_class){-.-.}-{2:2}, at: __irq_get_desc_lock+0x58/0xa0 stack backtrace: CPU: 0 PID: 307 Comm: init Not tainted 5.17.0-rc3-00394-gc849047c2473 #1 Hardware name: Allwinner sun8i Family unwind_backtrace from show_stack+0x10/0x14 show_stack from dump_stack_lvl+0x68/0x90 dump_stack_lvl from __lock_acquire+0x1680/0x31a0 __lock_acquire from lock_acquire+0x148/0x3dc lock_acquire from _raw_spin_lock_irqsave+0x50/0x6c _raw_spin_lock_irqsave from __irq_get_desc_lock+0x58/0xa0 __irq_get_desc_lock from irq_set_irq_wake+0x2c/0x19c irq_set_irq_wake from irq_set_irq_wake+0x13c/0x19c [tail call from sunxi_pinctrl_irq_set_wake] irq_set_irq_wake from gpio_keys_suspend+0x80/0x1a4 gpio_keys_suspend from gpio_keys_shutdown+0x10/0x2c gpio_keys_shutdown from device_shutdown+0x180/0x224 device_shutdown from __do_sys_reboot+0x134/0x23c __do_sys_reboot from ret_fast_syscall+0x0/0x1c However, this can never deadlock because the upstream and downstream IRQs are never the same (nor do they even involve the same irqchip). Silence this erroneous lockdep splat by applying what appears to be the usual fix of moving the GPIO IRQs to separate lockdep classes. Fixes: a59c99d9eaf9 ("pinctrl: sunxi: Forward calls to irq_set_irq_wake") Reported-by: Guenter Roeck <[email protected]> Signed-off-by: Samuel Holland <[email protected]> Reviewed-by: Jernej Skrabec <[email protected]> Tested-by: Guenter Roeck <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-02-19pinctrl: sunxi: do not print error message for EPROBE_DEFERMans Rullgard1-5/+4
Avoid printing an error message if getting a regulator fails with EPROBE_DEFER. This can happen if, for example, a regulator supplying one of the main banks is controlled by a PL pin. Signed-off-by: Mans Rullgard <[email protected]> Acked-by: Chen-Yu Tsai <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-02-19Merge tag 'samsung-pinctrl-5.18-2' of ↵Linus Walleij10-406/+781
https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung into devel Samsung pinctrl drivers changes for v5.18 1. Fix OF reference leak in pinctrl driver probe error path. 2. Correct list of handlers for Exynos850 ALIVE and CMGP pin banks. 3. Accept devicetrees with GPIO pin bank definitions named with a "-gpio-bank" suffix. This is necessary for later Samsung pinctrl bindings dtschema. 4. Convert Samsung pinctrl bindings to dtschema. 5. Add support for Exynos850 and ExynosAutov9 wake-up interrupts. 6. Add support for Tesla FSD SoC.
2022-02-19pinctrl: qcom: qcm2290: Add GPIO wakeirq mapShawn Guo1-0/+12
It adds the map of wakeup capable GPIOs and the pins at MPM wake controller on QCM2290, so that these GPIOs can wake up the SoC from vlow/vmin low power mode. Signed-off-by: Shawn Guo <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-02-19pinctrl: qcom: print egpio mode in debugfsJonathan Marek1-0/+9
When egpio_enable bit is cleared, the gpio is driven by SSC/LPASS TLMM and the APSS TLMM settings are ignored. Reflect that in the debugfs dump. Signed-off-by: Jonathan Marek <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-02-19pinctrl: qcom: sm8450: Add egpio supportJonathan Marek1-45/+61
This mirrors egpio support added for sc7280. This change is necessary for gpios 165 to 209 to be driven by APSS. Signed-off-by: Jonathan Marek <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-02-19Merge tag 'renesas-pinctrl-for-v5.18-tag1' of ↵Linus Walleij10-125/+155
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: renesas: Updates for v5.18 - Add MOST (MediaLB I/F) pins on R-Car E3 and D3, - Add support for the new RZ/V2L SoC, - Miscellaneous fixes and improvements.
2022-02-11pinctl: doc: Fix spelling mistake "resisitors" -> "resistors"Colin Ian King1-1/+1
There is a spelling mistake in the documentation. Fix it. Signed-off-by: Colin Ian King <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Acked-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-02-11pinctrl: nuvoton: npcm7xx: Rename DS() macro to DSTR()Jonathan Neuschäfer1-79/+79
The name "DS" is defined in arch/x86/um/shared/sysdep/ptrace_64.h, which results in a compiler warning when build-testing on ARCH=um. Rename this driver's "DS" macro to DSTR so avoid this collision. Reported-by: kernel test robot <[email protected]> Fixes: 3b588e43ee5c7 ("pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver") Signed-off-by: Jonathan Neuschäfer <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-02-11pinctrl: nuvoton: npcm7xx: Use %zu printk format for ARRAY_SIZE()Jonathan Neuschäfer1-1/+1
When compile-testing on 64-bit architectures, GCC complains about the mismatch of types between the %d format specifier and value returned by ARRAY_LENGTH(). Use %zu, which is correct everywhere. Reported-by: kernel test robot <[email protected]> Fixes: 3b588e43ee5c7 ("pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver") Signed-off-by: Jonathan Neuschäfer <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-02-11pinctrl: starfive: fix semicolon.cocci warningskernel test robot1-1/+1
drivers/pinctrl/pinctrl-starfive.c:1029:2-3: Unneeded semicolon Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci Reported-by: kernel test robot <[email protected]> Signed-off-by: kernel test robot <[email protected]> Reported-by: Abaci Robot <[email protected]> Reported-by: Yang Li <[email protected]> Link: https://lore.kernel.org/r/20220206003735.GA94316@d6598ff186c2 Signed-off-by: Linus Walleij <[email protected]>
2022-02-11dt-bindings: pinctrl: mt8195: fix bias-pull-{up,down} checksChen-Yu Tsai1-14/+16
When the constraints and description for bias-pull-{up,down} were added, the constraints were not indented correctly, resulting in them being parsed as part of the description. This effectively nullified their purpose. Move the constraints out of the description block, make each description part of the same associative array as the enum its describing, and reindent them correctly so they take effect. Also add "type: boolean" to the list of valid values. This corresponds to having bias-pull-{up,down} without any arguments. Fixes: 91e7edceda96 ("dt-bindings: pinctrl: mt8195: change pull up/down description") Signed-off-by: Chen-Yu Tsai <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-02-11dt-bindings: pinctrl: pinctrl-microchip-sgpio: Fix exampleHoratiu Vultur1-1/+1
The blamed commit adds support for irq, but the reqisters for irq are outside of the memory size. They are at address 0x108. Therefore update the memory size to cover all the registers used by the device. Fixes: 01a9350bdd49fb ("dt-bindings: pinctrl: pinctrl-microchip-sgpio: Add irq support") Signed-off-by: Horatiu Vultur <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-02-11pinctrl: uniphier: Add USB device pinmux settingsKunihiko Hayashi2-4/+16
Add USB device pinmux settings for PXs2 and PXs3 SoCs. Only pins for ports 0 and 1 support USB device mode. Signed-off-by: Kunihiko Hayashi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-02-11pinctrl: uniphier: Divide pinmux group to support 1ch and 2ch I2SKunihiko Hayashi4-44/+152
Current pinmux group for audio in/out assumes 4ch I2S case but the UniPhier AIO hardware also supports 1ch and 2ch I2S. So divide current ain1 group into ain1, ain1_dat2 and ain1_dat4 groups. Divide other ain and aout in the same way. Signed-off-by: Ryuta NAKANISHI <[email protected]> Signed-off-by: Kunihiko Hayashi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-02-11pinctrl: uniphier: Add missing audio pinmux settings for PXs2 SoCKunihiko Hayashi1-2/+10
Add missing audio I/O pinmux settings for PXs2 SoC. This adds ain1 4ch pins, ain3 and aout1. Signed-off-by: Kunihiko Hayashi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-02-11pinctrl: qcom: spmi-mpp: Add PM8226 compatibleRayyan Ansari1-0/+1
The PM8226 provides 8 MPPs. Add a compatible to support them. Signed-off-by: Rayyan Ansari <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-02-11dt-bindings: pinctrl: qcom,pmic-mpp: Document PM8226 compatibleRayyan Ansari1-0/+1
Document the Device Tree binding for PM8226 MPPs. Signed-off-by: Rayyan Ansari <[email protected]> Acked-by: Rob Herring <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-02-11dt-bindings: pinctrl: qcom: msm8953: allow gpio-reserved-rangesLuca Weiss1-0/+2
Allow the gpio-reserved-ranges property to be used in dts. Signed-off-by: Luca Weiss <[email protected]> Acked-by: Konrad Dybcio <[email protected]> Acked-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-02-08pinctrl: renesas: rzg2l: Improve rzg2l_gpio_register()Biju Das1-2/+2
Update rzg2l_gpio_register() to use driver data for chip->names and check for gpio-range. This allows reusing the driver for SoC's with different port pin definitions(eg:- RZ/G2UL SoC has fewer ports compared to RZ/G2L and port pin definitions are different). Signed-off-by: Biju Das <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2022-02-08pinctrl: renesas: r8a77995: Restore pin group sort orderGeert Uytterhoeven1-43/+43
Move the msiof* pin groups where they belong. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/da1018c56134b910121b085b736fe7f664b96df1.1643199959.git.geert+renesas@glider.be
2022-02-08pinctrl: renesas: r8a7790: Restore pin function sort orderGeert Uytterhoeven1-1/+1
Move the du* pin function where it belongs. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/f4eb545cedcd1a72f0f80ef85daf03e2e423e90f.1643199959.git.geert+renesas@glider.be
2022-02-08pinctrl: renesas: r8a7779: Restore pin function sort orderGeert Uytterhoeven1-4/+4
Move the sdhi* pin functions where they belong. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/f69d05a760445c8d67bedcb39cf5959333c71a1f.1643199959.git.geert+renesas@glider.be
2022-02-08pinctrl: renesas: r8a779a0: Rename MOD_SEL2_* definitionsGeert Uytterhoeven1-21/+21
Rename the MOD_SEL2_* definitions, to match the bitfield order in IPxSRy_* definitions and in MOD_SEL* definitions in other drivers. No changes in generated code. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Kieran Bingham <[email protected]> Link: https://lore.kernel.org/r/4880e4cbc112ee26569bf29a21c070125461e58d.1642524603.git.geert+renesas@glider.be
2022-02-08pinctrl: renesas: Kconfig: Select PINCTRL_RZG2L if RZ/V2L SoC is enabledBiju Das1-2/+4
RZ/V2L uses the RZ/G2L GPIO and pinctrl driver. Enable the RZ/G2L pinctrl driver if RZ/V2L is enabled. Update the description for RZ/V2L pin control support. Signed-off-by: Biju Das <[email protected]> Signed-off-by: Lad Prabhakar <[email protected]> Link: https://lore.kernel.org/r/[email protected] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2022-02-03pinctrl: ocelot: Add support for ServalT SoCHoratiu Vultur1-0/+102
This patch adds support for ServalT pinctrl, using the ocelot driver as basis. Signed-off-by: Horatiu Vultur <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
2022-02-03dt-bindings: pinctrl: ocelot: Add ServalT SoC supportHoratiu Vultur1-2/+2
Add the documentation for the Microsemi ServalT pinmuxing and gpio controller. Signed-off-by: Horatiu Vultur <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
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