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2012-10-09drm/nouveau: remove unused _nouveau_parent_ctorMarcin Slusarz2-20/+0
Signed-off-by: Marcin Slusarz <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2012-10-09drm/nouveau/bios: fix shadowing of ACPI ROMs larger than 64KiBBen Skeggs1-11/+10
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nv98/crypt: fix fuc build with latest envyasBen Skeggs1-1/+1
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/devinit: fixup various issues with subdev ctor/init orderingBen Skeggs2-16/+38
Details of the problem, and solution, are in comments in the commit proper. Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nv41/vm: fix and enable use of "real" pciegartBen Skeggs2-7/+14
Hopefully fixed the tlb flush timeout issue. Was able to observe this condition occur occasionally, and it appears the binary driver doesn't wait on the old condition either.. Should give 39-bit DMA addressing on the relevant chipsets. Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nv44/vm: fix and enable use of "real" pciegartBen Skeggs4-41/+29
Something seems to be missing in regards to flushing specific ranges of the TLB. For the moment, flushing the entire thing seems to make it work alright. Should give 39-bit DMA addressing on the relevant chipsets. v2: allocate contig 16KiB for dummy pages, reported by mwk on irc Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nv04/dmaobj: fixup vm target handling in preparation for nv4x pcieBen Skeggs1-7/+10
We don't need to pull the page address out of the page tables on nv4x chips that have a real GART. Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau: store supported dma mask in vmmgrBen Skeggs7-7/+9
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nvc0/ibus: initial implementation of subdevBen Skeggs4-0/+134
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/therm: add support for fan-control modesMartin Peres6-5/+105
For now, only 2 control modes are available: - NONE: The fan is never touched (default) - MANUAL: The fan is set to the user-defined fan speed (pwm1) This patch introduces a distinction between ptherm internal fan management and external fan management. The latter is bound to respect the fan mode while the first can still select the speed it wants unless the NONE mode is selected. This is important for automatic fan management. Signed-off-by: Martin Peres <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/hwmon: rename pwm0* to pmw1* to follow hwmon's rulesMartin Peres1-18/+18
This was reported by tizbac on IRC. Signed-off-by: Martin Peres <[email protected]> Reviewed-by: Ben Skeggs <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/therm: calculate the pwm divisor on nv50+Martin Peres3-4/+37
v2: Martin Peres <[email protected]> - fixed unintentional use of floating point Signed-off-by: Martin Peres <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/fan: rewrite the fan tachometer driver to get more precision, fasterMartin Peres1-9/+16
The previous driver waited for 250ms to accumulate data. This version times a complete fan rotation and extrapolates to RPM. The fan rotational speed should now be read in less than 250ms (worst case) and usually in less 50ms. Signed-off-by: Martin Peres <[email protected]> Reviewed-by: Ben Skeggs <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/therm: move thermal-related functions to the therm subdevMartin Peres22-542/+1048
It looks scary because of the size, but I tried to keep the differences minimal. Further patches will fix the actual "driver" code and add new features. v2: change filenames, split to submodules v3: add a missing include v4: Ben Skeggs <[email protected]> - fixed set_defaults() to allow min_duty < 30 (thermal table will override this if it's actually necessary) - fixed set_defaults() to not provide pwm_freq so nv4x (which only has pwm_div) can actually work. the boards using pwm_freq will have a thermal table entry to provide us the value. - removed unused files Signed-off-by: Martin Peres <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/bios: parse the pwm divisor from the perf tableMartin Peres3-0/+90
v2: perf_table now is more in line with the other functions Signed-off-by: Martin Peres <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/therm: use the EXTDEV table to detect i2c monitoring devicesMartin Peres4-0/+174
This commit also adds a static list of all known devices and their possible i2c addresses. v2: use the common table parsing technique as suggested by darktama Signed-off-by: Martin Peres <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/therm: rework thermal table parsingMartin Peres6-205/+282
As an accident, it should also fix temperature reading on nv4x. v2: introduce nvbios_therm_entry as advised by darktama Signed-off-by: Martin Peres <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/gpio: expose the PWM/TOGGLE parameter found in the gpio vbios tableMartin Peres2-0/+10
Signed-off-by: Martin Peres <[email protected]> Reviewed-by: Ben Skeggs <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau: fix pm initialization orderDmitry Eremin-Solenikov1-1/+2
If nouveau_pm_perflvl_get() fails, pm->profiles list will be left uninitialized, which causes oops during nouveau_pm_fini(). Move INIT_LIST_HEAD before call to nouveau_pm_perflvl_get(). Signed-off-by: Dmitry Eremin-Solenikov <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/bios: check that fixed tvdac gpio data is valid before using itBen Skeggs1-7/+11
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau: log channel debug/error messages from client object rather than ↵Ben Skeggs1-5/+5
drm client This will make it more obvious which application caused particular messages. Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau: have drm debugging macros build on top of core macrosBen Skeggs1-13/+6
May kill the DRM version completely at some point, undecided.. Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/core: have client-id be a string, rather than an integerBen Skeggs4-10/+14
Can be somewhat more informative that way... Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nvc0/fifo: re-bash PBUS regs after vm-fault to BARs/PEEPHOLEBen Skeggs1-4/+18
Seems to be required to "re-arm" the engines after a vm fault. Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nvc0/gr: implement initial trap handlerBen Skeggs1-4/+188
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nvc0/gr: rebuild fuc with latest envyasBen Skeggs4-12/+167
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nvc0/ltcg: read LTS count at startupBen Skeggs1-1/+3
Not really sure how to confirm this 100%, but, the numbers match on all the traces I have for NVCx (2 LTS), NVD9 (1LTS) and NVEx (4LTS). Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nve0/gr: enable use of our fuc by defaultBen Skeggs1-1/+1
Graphics acceleration is still disabled by default due to lingering issues that need to be solved. Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nve0/gr: remove 0x404160 bashing from hub fucBen Skeggs2-282/+189
Triggers PIBUS interrupts due to register not existing anymore, and as a result HUB_SET_CHAN times out. After this commit, our fuc loads and can accelerate at least fbcon, X, glxgears and OA on NVE4. NVE7 not tested as of yet. Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nve0/gr: initial fuc implementation, based on fermi's codeBen Skeggs6-69/+3235
Currently identical except the available chipset register lists. This will *not* currently work and is disabled by default because of this. May get merged again later, remains to be seen what further changes will be required. Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nve0/ibus: handle PIBUS interrupts to prevent stormBen Skeggs6-0/+162
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/sw: trap and clear PMC_INTR_0_SOFTWAREBen Skeggs5-0/+12
Came in useful for debugging another issue earlier, so keep it around. Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau: quiet some static-related sparse noiseMarcin Slusarz25-47/+51
Signed-off-by: Marcin Slusarz <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau: constify instances of nouveau_bitfield and nouveau_enum structsMarcin Slusarz12-39/+39
Signed-off-by: Marcin Slusarz <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/fifo: use defines instead of hardcoded class idsBen Skeggs9-12/+20
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/dmaobj: reject unsupported parent types instead of half-succeedingBen Skeggs2-10/+16
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau: add defines for internal class namesBen Skeggs1-14/+35
Will probably flesh the documentation of the classes out a bit too at some later point. Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nv50/fifo: add support for dma channel classBen Skeggs3-7/+72
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nv84/fifo: add support for dma channel classBen Skeggs3-7/+81
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/fifo: version the dma channel class structBen Skeggs6-6/+6
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/fifo: separate object classes for dma channelsBen Skeggs6-5/+10
Future code will use the object class rather than chipset checks in order to identify available channel features. Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau: restore fifo chid information in engine error messagesBen Skeggs15-132/+213
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/core: have fifo store a unique context identifier at attach timeBen Skeggs11-2/+23
This value will match something that's easily available from the engine IRQ handlers, and used to lookup the relevant context. Since the changes in how this is done on each generation match when the major PFIFO changes happened, fifo is responsible for calculating the correct value to avoid duplicating the same code among many engine modules. Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/fifo: add method to lookup fifo chid related to a given objectBen Skeggs2-0/+17
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/core: protect engine context list with hardirq-safe spinlockBen Skeggs4-20/+60
IRQ handlers will need access to engine contexts. Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nv84/fifo: mask only the engine we're waiting on for channel unloadBen Skeggs1-6/+10
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nve0: use async copy engine for ttm buffer moves if availableBen Skeggs7-26/+72
Kepler PFIFO lost the ability to address multiple engines from a single channel, so we need a separate one for the copy engine. v2: Marcin Slusarz <[email protected]> - regression fix: restore hw accelerated buffer copies Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nve0/copy: add initial support for the async copy enginesBen Skeggs4-0/+164
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nve0/fifo: support engine selection when creating fifo channelsBen Skeggs7-13/+64
Signed-off-by: Ben Skeggs <[email protected]>
2012-10-03drm/nouveau/device: return proper error codes if ioremap failsBen Skeggs1-3/+3
Signed-off-by: Ben Skeggs <[email protected]>
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