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Keep a pointer to the corresponding s3c_irq_data struct as irq_chip_data.
This removes the need to fetch the intc struct from the irq_domains
host_data, thus making it independent of the underlying irq_domain
structure.
Also keep the real register offset of the interrupt in the s3c_irq_data
struct to make it independent of the hwirq structure in the irq_domain
Signed-off-by: Heiko Stuebner <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>
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For dt-enabled machines we want to use a big irq_domain over all controllers
and therefore need to access not only the main controllers but the
sub-controller as well.
Signed-off-by: Heiko Stuebner <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>
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Enables post-init setting of the desired typehandler for the interrupt.
Signed-off-by: Heiko Stuebner <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>
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The list in used was from the s3c2450, a close cousin of the s3c2416.
As it's not possible to distinguish between the s3c2416 and s3c2450
the additional interrupts of the s3c2450 will only be available thru
devicetree later.
Signed-off-by: Heiko Stuebner <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>
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Might be confusing for people to read the code without having the
datasheet nearby.
Signed-off-by: Heiko Stuebner <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>
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This move is necessary to make use of the irqchip infrastructure
for the following devicetree support for s3c24xx architectures.
Signed-off-by: Heiko Stuebner <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>
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Use the new standard API of_property_read_u32_index() instead of open-
coding it.
Signed-off-by: Stephen Warren <[email protected]>
Signed-off-by: Tony Prisk <[email protected]>
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With the move to a combined pinctrl/gpio driver, the arch-vt8500
gpio driver is no longer required.
Signed-off-by: Tony Prisk <[email protected]>
Acked-by: Linus Walleij <[email protected]>
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Remove the gpio related devicetree nodes as these are no longer required
with the move to a combined pinctrl/gpio driver.
Signed-off-by: Tony Prisk <[email protected]>
Acked-by: Linus Walleij <[email protected]>
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This patch adds pinctrl nodes to the VIA VT8500 and Wondermedia SoC dtsi
files to support the pinctrl driver.
Signed-off-by: Tony Prisk <[email protected]>
Acked-by: Linus Walleij <[email protected]>
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This patch adds support for the GPIO/pinmux controller found on the VIA
VT8500 and Wondermedia WM8xxx-series SoCs.
Each pin within the controller is capable of operating as a GPIO or as
an alternate function. The pins are numbered according to their control
bank/bit so that if new pins are added, the existing numbering is maintained.
All currently supported SoCs are included: VT8500, WM8505, WM8650, WM8750 and
WM8850.
Signed-off-by: Tony Prisk <[email protected]>
Reviewed-by: Stephen Warren <[email protected]>
Acked-by: Linus Walleij <[email protected]>
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With the inclusion of the pin control driver, more GPIO pins have been
identified on the arch-vt8500 SoCs requiring an increase in the available
GPIOs.
Signed-off-by: Tony Prisk <[email protected]>
Acked-by: Linus Walleij <[email protected]>
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Several functions in of/base.c have the same code duplicated for
finding and validating a property and value.
struct property *prop = of_find_property(np, propname, NULL);
if (!prop)
return -EINVAL;
if (!prop->value)
return -ENODATA;
if (<some length> > prop->length)
return -EOVERFLOW;
This patch adds of_find_property_value_of_size() which performs the
equivalent of the above code and removes the instances where it was
duplicated in several functions.
Reported-by: Rob Herring <[email protected]>
Signed-off-by: Tony Prisk <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Acked-by: Rob Herring <[email protected]>
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This patch adds an of_property_read_u32_index() function to allow
reading a single indexed u32 value from a property containing multiple
u32 values.
Signed-off-by: Tony Prisk <[email protected]>
Reviewed-by: Stephen Warren <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Acked-by: Rob Herring <[email protected]>
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Besides being used to interface with external memory devices,
the General-Purpose Memory Controller can be used to connect
Pseudo-SRAM devices such as ethernet controllers to OMAP2+
processors using the TI GPMC as a data bus.
This patch allows an ethernet chip to be defined as an GPMC
child device node.
Signed-off-by: Javier Martinez Canillas <[email protected]>
Signed-off-by: Jon Hunter <[email protected]>
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The gpmc_probe_nor_child() function is used in the GPMC driver to
configure the GPMC for a NOR child device node.
But this function is quite generic and all the NOR specific configuration
is made by the driver of the actual NOR flash memory used.
Other Pseudo-SRAM devices such as ethernet controllers need a similar
setup so by making this function generic it can be used for those too.
Signed-off-by: Javier Martinez Canillas <[email protected]>
Signed-off-by: Jon Hunter <[email protected]>
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gpmc_probe_nor_child() calls of_platform_device_create() to create a
platform device for the NOR child. If this function fails the value
of ret is returned to the caller but this value is zero since it was
assigned the return of a previous call to gpmc_cs_program_settings()
that had to succeed or otherwise gpmc_probe_nor_child() would have
returned before.
This means that if of_platform_device_create() fails, 0 will be returned
to the caller instead of an appropriate error code.
Signed-off-by: Javier Martinez Canillas <[email protected]>
Signed-off-by: Jon Hunter <[email protected]>
Tested-by: Ezequiel Garcia <[email protected]>
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When the GPMC driver is probed, we call gpmc_mem_init() to see which
chip-selects have already been configured and enabled by the boot-loader
and allocate space for them. If we fail to allocate space for one
chip-select, then we return failure from the probe and the GPMC driver
will not be available.
Rather than render the GPMC useless for all GPMC devices, if we fail to
allocate space for one chip-select print a warning and disable the
chip-select. This way other GPMC clients can still be used.
There is no downside to this approach, because all GPMC clients need to
request a chip-select before they can use the GPMC and on requesting a
chip-select, if memory has not already been reserved for the chip-select
then it will be.
Signed-off-by: Jon Hunter <[email protected]>
Tested-by: Ezequiel Garcia <[email protected]>
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With commit 21cc2bd (ARM: OMAP2+: Remove apollon board support) the
variable "boot_rom_space" is now not needed and the code surrounding
this variable can be cleaned up and simplified. Remove unnecessary
definitions and clean-up the comment as well.
Signed-off-by: Jon Hunter <[email protected]>
Tested-by: Ezequiel Garcia <[email protected]>
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Each GPMC chip-select can be configured to map 16MB, 32MB, 64MB or 128MB
of address space. The physical base address where a chip-select starts
is also configurable and must be aligned on a boundary that is equal to
or greater than the size of the address space mapped bt the chip-select.
When enabling a GPMC chip-select, ensure that the base address is aligned
to the appropriate boundary.
Reported-by: Mark Jackson <[email protected]>
Signed-off-by: Jon Hunter <[email protected]>
Tested-by: Ezequiel Garcia <[email protected]>
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When booting with device-tree, retrieve GPMC settings for ONENAND from
the device-tree blob. This will allow us to remove all static settings
stored in the gpmc-nand.c in the future once the migration to
device-tree is complete.
The user must now specify the ONENAND device width in the device-tree
binding so that the GPMC can be programmed correctly. Therefore, update
the device-tree binding documentation for ONENAND devices connected to
the GPMC to reflect this.
Please note that this does not include GPMC timings for ONENAND. The
timings are being calculated at runtime.
There is some legacy code that only enables read wait monitoring for
non-OMAP3 devices. There are no known OMAP3 device issues that prevent
this feature being enabled and so when booting with device-tree use the
wait-monitoring settings described in the device-tree blob.
Signed-off-by: Jon Hunter <[email protected]>
Tested-by: Ezequiel Garcia <[email protected]>
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When booting with device-tree, retrieve GPMC settings for NAND from
the device-tree blob. This will allow us to remove all static settings
stored in the gpmc-nand.c in the future once the migration to
device-tree is complete.
Signed-off-by: Jon Hunter <[email protected]>
Tested-by: Ezequiel Garcia <[email protected]>
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NOR flash is not currently supported when booting with device-tree
on OMAP2+ devices. Add support to detect and configure NOR devices
when booting with device-tree.
Add documentation for the TI GPMC NOR binding.
Signed-off-by: Jon Hunter <[email protected]>
Tested-by: Ezequiel Garcia <[email protected]>
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Some of the GPMC timings parameters are currently missing from the GPMC
device-tree binding. Add these parameters to the binding documentation
as well as code to read them. Also add either "-ps" or "-ns" suffix to
the GPMC timing properties to indicate whether the timing is in
picoseconds or nanoseconds.
The existing code in gpmc_read_timings_dt() is checking the value of
of_property_read_u32() and only is successful storing the value read
in the gpmc_timings structure. Checking the return value in this case
is not necessary and we can simply read the value, if present, and
store directly in the gpmc_timings structure. Therefore, simplify the
code by removing these checks.
The comment in the gpmc_read_timings_dt() function, "only for OMAP3430"
is also incorrect as it is applicable to all OMAP3+ devices. So correct
this too.
Signed-off-by: Jon Hunter <[email protected]>
Tested-by: Ezequiel Garcia <[email protected]>
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When I applied regarding samsung-time patches, the "select GENERIC_GPIO"
has been added wrong, so this patch fixes that.
And since the GENERIC_GPIO in arch/arm/ will be gone away, this adds
ARCH_REQUIRE_GPIOLIB for S3C24XX and S5PC100 instead.
Reported-by: Alexandre Courbot <[email protected]>
Cc: Romain Naour <[email protected]>
Signed-off-by: Kukjin Kim <[email protected]>
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Add necessary definitions to support ab8500-musb pinctrl default and
sleep states.
Signed-off-by: Patrice Chotard <[email protected]>
Signed-off-by: Fabio Baltieri <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
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DB8500_PIN_SLEEP was defined twice, drop one of the two.
Signed-off-by: Fabio Baltieri <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
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After the patch series for system suspending support, tegra_idle_lp2_last()
no longer uses its parameters cpu_on_time or cpu_off_time, so remove them.
Signed-off-by: Joseph Lo <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>
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Adding suspend to RAM support for Tegra platform. There are three suspend
mode for Tegra. The difference were below.
* LP2: CPU voltage off
* LP1: CPU voltage off, DRAM in self-refresh
* LP0: CPU + Core voltage off, DRAM in self-refresh
After this patch, the LP2 suspend mode will be supported.
Signed-off-by: Joseph Lo <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>
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The PMC mostly controls the entry and exit of the system from different
sleep modes. Different platform or system may have different configurations.
The power management configurations of PMC is represented as some properties.
The system needs to define the properties when the system supports deep sleep
mode (i.e. suspend).
Cc: Grant Likely <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: [email protected]
Signed-off-by: Joseph Lo <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>
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Add the wake up handling for legacy irq controller, and using
IRQCHIP_MASK_ON_SUSPEND for wake irq handling.
Based on the work by:
Varun Wadekar <[email protected]>
Signed-off-by: Joseph Lo <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>
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This patch add the gpio wakeup source handling for the Tegra platform. It
was be done by enabling the irq for the gpio in the gpio controller and
enabling the bank irq of the gpio in the Tegra legacy irq controller when
the system going to suspend.
Based on the work by:
Varun Wadekar <[email protected]>
Cc: Grant Likely <[email protected]>
Cc: Linus Walleij <[email protected]>
Signed-off-by: Joseph Lo <[email protected]>
Acked-by: Linus Walleij <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>
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The CPU power timer set up function was related to PMC register. Now moving
it to PMC driver. And it also help to clean up the PM related code later.
The timer was calculated based on the input clock of PMC. In this patch, we
also get the clock from DT.
Signed-off-by: Joseph Lo <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>
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Adding the bindings of the clock source of PMC in DT.
Signed-off-by: Joseph Lo <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>
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omap-for-v3.10/timer
Conflicts:
arch/arm/mach-omap2/timer.c
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Conflicts:
arch/arm/plat-omap/dmtimer.c
Resolve merge conflict in omap_device.c as per
Lothar Waßmann <[email protected]>.
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Reentrancy into the clock framework is necessary for clock operations
that result in nested calls to the clk api. A common example is a clock
that is prepared via an i2c transaction, such as a clock inside of a
discrete audio chip or a power management IC. The i2c subsystem itself
will use the clk api resulting in a deadlock:
clk_prepare(audio_clk)
i2c_transfer(..)
clk_prepare(i2c_controller_clk)
The ability to reenter the clock framework prevents this deadlock.
Other use cases exist such as allowing .set_rate callbacks to call
clk_set_parent to achieve the best rate, or to save power in certain
configurations. Yet another example is performing pinctrl operations
from a clk_ops callback. Calls into the pinctrl subsystem may call
clk_{un}prepare on an unrelated clock. Allowing for nested calls to
reenter the clock framework enables both of these use cases.
Reentrancy is implemented by two global pointers that track the owner
currently holding a global lock. One pointer tracks the owner during
sleepable, mutex-protected operations and the other one tracks the owner
during non-interruptible, spinlock-protected operations.
When the clk framework is entered we try to hold the global lock. If it
is held we compare the current task against the current owner; a match
implies a nested call and we reenter. If the values do not match then
we block on the lock until it is released.
Signed-off-by: Mike Turquette <[email protected]>
Cc: Rajagopal Venkat <[email protected]>
Cc: David Brown <[email protected]>
Tested-by: Laurent Pinchart <[email protected]>
Reviewed-by: Thomas Gleixner <[email protected]>
Reviewed-by: Ulf Hansson <[email protected]>
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Create locking helpers for the global mutex and global spinlock. The
definitions of these helpers will be expanded upon in the next patch
which introduces reentrancy into the locking scheme.
Signed-off-by: Mike Turquette <[email protected]>
Cc: Rajagopal Venkat <[email protected]>
Cc: David Brown <[email protected]>
Tested-by: Laurent Pinchart <[email protected]>
Reviewed-by: Thomas Gleixner <[email protected]>
Reviewed-by: Ulf Hansson <[email protected]>
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Provide RESET and Power regulators for the USB PHY,
the USB Host port mode and the PHY device.
Also provide pin multiplexer information for USB host
pins.
CC: Benoît Cousson <[email protected]>
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>
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Adds device nodes for HS USB Host module, TLL module,
OHCI and EHCI controllers.
CC: Benoît Cousson <[email protected]>
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>
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Adds device nodes for HS USB Host module, TLL module,
OHCI and EHCI controllers.
CC: Benoît Cousson <[email protected]>
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>
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Use usbhs_init_phys() to register the PHY's RESET regulator
and the NOP PHY device.
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>
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Use usbhs_init_phys() to register the PHY's RESET regulator
and the NOP PHY device.
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>
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Use usbhs_init_phys() to register the PHY's RESET regulator
and the NOP PHY device.
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>
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Use usbhs_init_phys() to register the PHY's RESET regulator
and the NOP PHY device.
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>
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Use usbhs_init_phys() to register the PHY's RESET regulator
and NOP PHY device. VAUX2 supplies the PHY's VCC.
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>
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Use usbhs_init_phys() to register the PHY's RESET regulator
and the NOP PHY device. VAUX2 supplies the PHY's VCC.
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>
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Use usbhs_init_phys() to register the PHY's RESET regulators
and the NOP PHY devices.
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>
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Remove deprecated USBHS platform data.
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>
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Use usbhs_init_phys() to register the PHY's RESET regulators
and the NOP PHY devices.
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>
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