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2014-01-10macvlan: forbid L2 fowarding offload for macvtapJason Wang1-1/+4
L2 fowarding offload will bypass the rx handler of real device. This will make the packet could not be forwarded to macvtap device. Another problem is the dev_hard_start_xmit() called for macvtap does not have any synchronization. Fix this by forbidding L2 forwarding for macvtap. Cc: John Fastabend <[email protected]> Cc: Neil Horman <[email protected]> Acked-by: Neil Horman <[email protected]> Signed-off-by: Jason Wang <[email protected]> Acked-by: John Fastabend <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2014-01-10Merge branch 'for-davem' of ↵David S. Miller4-14/+23
git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless John W. Linville says: ==================== For the mac80211 bits, Johannes says: "I have a fix from Javier for mac80211_hwsim when used with wmediumd userspace, and a fix from Felix for buffering in AP mode." For the NFC bits, Samuel says: "This pull request only contains one fix for a regression introduced with commit e29a9e2ae165620d. Without this fix, we can not establish a p2p link in target mode. Only initiator mode works." For the iwlwifi bits, Emmanuel says: "It only includes new device IDs so it's not vital. If you have a pull request to net.git anyway, I'd happy to have this in." ==================== Signed-off-by: David S. Miller <[email protected]>
2014-01-10bnx2x: fix DMA unmapping of TSO split BDsMichal Schmidt1-4/+9
bnx2x triggers warnings with CONFIG_DMA_API_DEBUG=y: WARNING: CPU: 0 PID: 2253 at lib/dma-debug.c:887 check_unmap+0xf8/0x920() bnx2x 0000:28:00.0: DMA-API: device driver frees DMA memory with different size [device address=0x00000000da2b389e] [map size=1490 bytes] [unmap size=66 bytes] The reason is that bnx2x splits a TSO BD into two BDs (headers + data) using one DMA mapping for both, but it uses only the length of the first BD when unmapping. This patch fixes the bug by unmapping the whole length of the two BDs. Signed-off-by: Michal Schmidt <[email protected]> Reviewed-by: Eric Dumazet <[email protected]> Acked-by: Dmitry Kravkov <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2014-01-10drm/i915: add braces around KHz/MHz macro parametersJani Nikula1-2/+2
It's an accident waiting to happen. Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Damien Lespiau <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-01-10drm/i915: Fix 915GM self-refresh enable/disableVille Syrjälä1-2/+2
INSTPM is a masked register so use the _MASKED_BIT_{ENABLE,DISABLE} macros when enabling/disabling self-refresh on 915GM. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-01-10drm/i915: 830M doesn't have an LVDS portVille Syrjälä1-1/+1
There's no LVDS port on 830M so don't go reading the LVDS control register. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-01-10drm/i915: No panel fitter on 830M or non-mobile gen2/3 platformsVille Syrjälä2-1/+4
PFIT_CONTROL doesn't exist on 830M, so avoid reading it in i9xx_get_pfit_config(). Also assume that only mobile gen2/3 chipsets have a panel fitter. This matches the documentation, but I didn't have real hardware to verify. Gen4 docmentation is a bit inconsistent, but experimenetation on my LPT machine suggests that the panel fitter is available on non-mobile gen4 platforms. At least on this machine panel fitter appears works just fine even on VGA output. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-01-10drm/i915/vlv: Add drpc debugfs support for valleyviewDeepak S2-1/+49
Many of the fields from Gen6 have gone away for vlv. Strip all those fields that are not relevent and try to update fields that we care about. This patch give information about current RP & RC status and individual Wells. v2: Move Render & Media Well status to separate lines (Ville) Signed-off-by: Deepak S <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-01-10drm/i915: vlv: W/a for hotplug/manual VGA detectionImre Deak1-4/+15
VGA detection requires the reference clock to be on, so make sure this is the case. This fixes VGA hotplug/manual detection where all pipes are off and so we would normally disable all clocks. v2: - Instead of disabling PSR clock gating, force the reference clock on through the DPLL_A register. (Kin Chan S <[email protected]>) v3: - Move enabling of the clock to intel_reset_dpio() and use the DPLL_B register instead, where we already have a similar tweak for the CRI clock. (Ville) Reported-by: Joonas Lahtinen <[email protected]> Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-01-10drm/i915: vlv: make CRI clock enabling explicit during resumeImre Deak1-4/+4
intel_init_dpio() isn't called during resume, so we won't set the CRI clock enable bit during that time. Move the enabling to intel_reset_dpio() instead. Note that the HW reset value for this bit is 1, so probably this patch won't make any difference. We should still make the setting explicit, since BIOS could change things under us. Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-01-10drm/i915: only apply GAMMA_MODE IPS WA on HSWPaulo Zanoni1-1/+1
The WA is mentioned in HSW's GAMMA_MODE register documentation, but not on on BDW's documentation, so let's assume it is not needed there. Signed-off-by: Paulo Zanoni <[email protected]> Reviewed-by: Damien Lespiau <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-01-10drm/i915: Introduce new intel_output_name()Damien Lespiau2-0/+23
That we can use for debugging purposes. v2: Use designated initializers for the 'names' array (Paulo Zanoni, Jani Nikula). Add a check in case the array has a hole (which can now remain unnoticed with designated initializers) (Jani Nikula) Reviewed-by: Paulo Zanoni <[email protected]> (for v1) Signed-off-by: Damien Lespiau <[email protected]> Reviewed-by: Jani Nikula <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-01-10drm/i915: don't set modes for 2 connectors on the same encoderPaulo Zanoni1-4/+8
In some cases we have more than 1 connector associated to an encoder (e.g., SDVO, Haswell DP/HDMI) and we can only set a mode for one of these connectors. If we only allowed modesets for connected connectors we would never need this patch, but since we do allow modeset for disconnected connectors we may see user space trying to set modes on the two connectors attached to the same encoder, so we need to forbid that. This problem can be reproduced by running the following intel-gpu-tools test case: ./kms_setmode --run-subtest clone-exclusive-crtc Thanks to Daniel Vetter for providing a version of this patch on pastebin. Credits-to: Daniel Vetter <[email protected]> Signed-off-by: Paulo Zanoni <[email protected]> Reviewed-by: Damien Lespiau <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-01-10drm/i915: i830M has watermarks like i855Daniel Vetter1-34/+19
So shuffle the checks around a bit. Also give all the structs and functions proper prefixes: i830_ for the dual-pipe mobile platforms and i845_ for the two single-pipe desktop platforms. Note that the max fifo value isn't actually correct for the i830M, but since we don't frob the fifo split we don't actually need it. This is different for some gen3 devices where we need the full fifo for self refresh mode. Cc: Thomas Richter <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-01-10drm/i915: Drop I915_ prefix from HAS_FBCDaniel Vetter6-9/+9
My OCD just couldn't let this slide. Spotted while reviewing Ville's patch to only flip planes when we have FBC. Cc: Ville Syrjälä <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-01-10Merge tag 'clk-fixes-for-linus' of ↵Linus Torvalds6-13/+19
git://git.linaro.org/people/mike.turquette/linux Pull clock fixes from Mike Turquette: "Late fixes for clock drivers. All of these fixes are for user-visible regressions, typically boot failures or other unsafe system configuration that causes badness" * tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux: clk: clk-divider: fix divisor > 255 bug clk: exynos: File scope reg_save array should depend on PM_SLEEP clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock ARM: dts: exynos5250: Fix MDMA0 clock number clk: samsung: exynos5250: Add MDMA0 clocks clk: samsung: exynos5250: Fix ACP gate register offset clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks clk: samsung: exynos4: Correct SRC_MFC register
2014-01-10Merge tag 'fixes-for-linus' of ↵Linus Torvalds3-5/+5
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Olof Johansson: "A few fixes for Renesas platforms to fixup DMA masks (this started causing errors once the DMA API added checks for valid masks in 3.13)" * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: shmobile: mackerel: Fix coherent DMA mask ARM: shmobile: kzm9g: Fix coherent DMA mask ARM: shmobile: armadillo: Fix coherent DMA mask
2014-01-10drm/i915: Don't swap planes on 830MVille Syrjälä2-3/+3
Looks like 830M doesn't quite like it when you try to move a plane from one pipe to another. It seems that the plane's old pipe has to be active even if the plane is already disabled, otherwise the relevant register just won't accept new values. The following commit: commit 1f1c2e2468f937cefd6bcb645c959c7b5d9821df Author: Ville Syrjälä <[email protected]> Date: Thu Nov 28 17:30:01 2013 +0200 drm/i915: Swap primary planes on gen2 for FBC caused a regression on 830M. It will attempt to swap the planes when the driver is loaded, but at that time only pipe A might be active, so plane A gets disabled, but plane B won't get enabled since pipe B is not active when we try to move the plane over to pipe A. There's no reason to swap planes on 830M since it doesn't support FBC. Change the logic a bit to limit the plane swapping to platforms which actually support FBC. This should avoid getting a black screen on 830M. Signed-off-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2014-01-10drm/i915: Don't grab crtc mutexes in intel_modeset_gem_init()Ville Syrjälä1-2/+2
When the pipe A force quirk is applied the code will attempt to grab a crtc mutex during intel_modeset_setup_hw_state(). If we're already holding all crtc mutexes this will obviously deadlock every time. So instead of using drm_modeset_lock_all() just grab the mode_config.mutex. This is enough to avoid the unlocked mutex warnings from certain lower level functions. The regression was introduced in: commit 027476642811f8559cbe00ef6cc54db230e48a20 Author: Ville Syrjälä <[email protected]> Date: Mon Dec 2 11:08:06 2013 +0200 drm/i915: Take modeset locks around intel_modeset_setup_hw_state() Signed-off-by: Ville Syrjälä <[email protected]> Cc: [email protected] [danvet: Add cc: stable since the offending commit has that, too.] Signed-off-by: Daniel Vetter <[email protected]>
2014-01-09ipv6: add link-local, sit and loopback address with INFINITY_LIFE_TIMEHannes Frederic Sowa1-2/+4
In the past the IFA_PERMANENT flag indicated, that the valid and preferred lifetime where ignored. Since change fad8da3e085ddf ("ipv6 addrconf: fix preferred lifetime state-changing behavior while valid_lft is infinity") we honour at least the preferred lifetime on those addresses. As such the valid lifetime gets recalculated and updated to 0. If loopback address is added manually this problem does not occur. Also if NetworkManager manages IPv6, those addresses will get added via inet6_rtm_newaddr and thus will have a correct lifetime, too. Reported-by: François-Xavier Le Bail <[email protected]> Reported-by: Damien Wyart <[email protected]> Fixes: fad8da3e085ddf ("ipv6 addrconf: fix preferred lifetime state-changing behavior while valid_lft is infinity") Cc: Yasushi Asano <[email protected]> Signed-off-by: Hannes Frederic Sowa <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2014-01-09bnx2x: prevent WARN during driver unloadYuval Mintz2-18/+38
Starting with commit 80c33dd "net: add might_sleep() call to napi_disable" bnx2x fails the might_sleep tests causing a stack trace to appear whenever the driver is unloaded, as local_bh_disable() is being called before napi_disable(). This changes the locking schematics related to CONFIG_NET_RX_BUSY_POLL, preventing the need for calling local_bh_disable() and thus eliminating the issue. Signed-off-by: Yuval Mintz <[email protected]> Signed-off-by: Dmitry Kravkov <[email protected]> Signed-off-by: Ariel Elior <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2014-01-10Merge branch 'pm-cpuidle'Rafael J. Wysocki1-6/+8
* pm-cpuidle: intel_idle: close avn_cstates array with correct marker Revert "intel_idle: mark states tables with __initdata tag"
2014-01-10intel_idle: close avn_cstates array with correct markerJiang Liu1-1/+3
Close avn_cstates array with correct marker to avoid overflow in function intel_idle_cpu_init(). [rjw: The problem was introduced when commit 22e580d07f65 was merged on top of eba682a5aeb6 (intel_idle: shrink states tables).] Fixes: 22e580d07f65 (intel_idle: Fixed C6 state on Avoton/Rangeley processors) Signed-off-by: Jiang Liu <[email protected]> Signed-off-by: Rafael J. Wysocki <[email protected]>
2014-01-09ftrace/x86: Load ftrace_ops in parameter not the variable holding itSteven Rostedt2-3/+3
Function tracing callbacks expect to have the ftrace_ops that registered it passed to them, not the address of the variable that holds the ftrace_ops that registered it. Use a mov instead of a lea to store the ftrace_ops into the parameter of the function tracing callback. Signed-off-by: Steven Rostedt <[email protected]> Reviewed-by: Masami Hiramatsu <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: H. Peter Anvin <[email protected]> Cc: <[email protected]> # v3.8+
2014-01-09drm/msm: add a330/apq8x74Rob Clark5-23/+144
Add support for adreno 330. Not too much different, just a few differences in initial configuration plus setting OCMEM base. Userspace support is already in upstream mesa. Note that the existing DT code is simply using the bindings from downstream android kernel, to simplify porting of this driver to existing devices. These do not constitute any committed/stable DT ABI. The addition of proper DT bindings will be a subsequent patch, at which point (as best as possible) I will try to support either upstream bindings or what is found in downstream android kernel, so that existing device DT files can be used. Signed-off-by: Rob Clark <[email protected]>
2014-01-09drm/msm: add mdp5/apq8x74Rob Clark12-2/+2167
Add support for the new MDP5 display controller block. The mapping between parts of the display controller and KMS is: plane -> PIPE{RGBn,VIGn} \ crtc -> LM (layer mixer) |-> MDP "device" encoder -> INTF / connector -> HDMI/DSI/eDP/etc --> other device(s) Unlike MDP4, it appears we can get by with a single encoder, rather than needing a different implementation for DTV, DSI, etc. (Ie. the register interface is same, just different bases.) Also unlike MDP4, all the IRQs for other blocks (HDMI, DSI, etc) are routed through MDP. And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from which blocks need to be allocated to the active pipes based on fetch stride. Signed-off-by: Rob Clark <[email protected]>
2014-01-09drm/msm: add hdmi support for apq8x74/mdp5Rob Clark8-107/+511
The HDMI block is basically the same between older SoC's with mdp4 display controller, and newer ones with mdp5. So mostly this consists of better abstracting out the different sets of regulators, clks, etc. In particular, for regulators and clks we can split it up by what is needed for hot plug detect to work, and what is needed to light up the display. Also, 8x74 has a new phy.. a very simple one, but split out into a different mmio space. And with mdp5, the irq is shared with mdp, so we don't directly register our own irq handler. Signed-off-by: Rob Clark <[email protected]>
2014-01-09drm/msm: move irq utils to mdp_kmsRob Clark10-169/+254
We'll want basically the same thing for mdp5, so refactor it out so it can be shared. Signed-off-by: Rob Clark <[email protected]>
2014-01-09drm/msm: split out msm_kms.hRob Clark6-30/+60
Signed-off-by: Rob Clark <[email protected]>
2014-01-09drm/msm: mdp4_format -> mdp_formatRob Clark7-31/+64
This can be shared between mdp4 and mdp5. Both use the same set of parameters to describe the format to the hw. Signed-off-by: Rob Clark <[email protected]>
2014-01-09drm/msm: resync generated headersRob Clark14-243/+1525
resync to latest envytools db, add mdp5 registers Signed-off-by: Rob Clark <[email protected]>
2014-01-09drm/msm: move mdp4 -> mdp/mdp4Rob Clark9-6/+6
There are some little bits and pieces that mdp4 and mdp5 can share, so move things around so that we can have both in a common parent directory. Signed-off-by: Rob Clark <[email protected]>
2014-01-09drm/msm: add support for msm8060ab/bstemRob Clark3-5/+19
This adds the necessary configuration for the APQ8060A SoC (dual-core krait + a320 gpu) as found on the bstem board. Signed-off-by: Rob Clark <[email protected]>
2014-01-09drm/msm: add support for non-IOMMU systemsRob Clark12-147/+410
Add a VRAM carveout that is used for systems which do not have an IOMMU. The VRAM carveout uses CMA. The arch code must setup a CMA pool for the device (preferrably in highmem.. a 256m-512m VRAM pool in lowmem is not cool). The user can configure the VRAM pool size using msm.vram module param. Technically, the abstraction of IOMMU behind msm_mmu is not strictly needed, but it simplifies the GEM code a bit, and will be useful later when I add support for a2xx devices with GPUMMU, so I decided to keep this part. It appears to be possible to configure the GPU to restrict access to addresses within the VRAM pool, but this is not done yet. So for now the GPU will refuse to load if there is no sort of mmu. Once address based limits are supported and tested to confirm that we aren't giving the GPU access to arbitrary memory, this restriction can be lifted Signed-off-by: Rob Clark <[email protected]>
2014-01-09drm/msm: fix bus scalingRob Clark4-15/+23
This got a bit broken with original patches when re-arranging things to move dependencies on mach-msm inside #ifndef OF. Signed-off-by: Rob Clark <[email protected]>
2014-01-09drm/msm: add missing MODULE_FIRMWARE()sRob Clark1-0/+5
Signed-off-by: Rob Clark <[email protected]>
2014-01-09drm/msm: COMPILE_TEST supportRob Clark3-4/+10
With a simple stub, we can get COMPILE_TEST support. Signed-off-by: Rob Clark <[email protected]>
2014-01-09Merge branch 'master' of ↵John W. Linville4-14/+23
git://git.kernel.org/pub/scm/linux/kernel/git/linville/wireless into for-davem
2014-01-09Revert "intel_idle: mark states tables with __initdata tag"Jiang Liu1-5/+5
This reverts commit 9d046ccb98085f1d437585f84748c783a04ba240. Commit 9d046ccb98085 marks all state tables with __initdata, but the state table may be accessed when doing CPU online, which then causing system crash as below: [ 204.188841] BUG: unable to handle kernel paging request at ffffffff8227cce8 [ 204.196844] IP: [<ffffffff814aa1c0>] intel_idle_cpu_init+0x40/0x130 [ 204.203996] PGD 1e11067 PUD 1e12063 PMD 455859063 PTE 800000000227c062 [ 204.211638] Oops: 0000 [#1] SMP DEBUG_PAGEALLOC [ 204.216975] Modules linked in: x86_pkg_temp_thermal intel_powerclamp coretemp kvm_intel kvm crct10dif_pclmul crc32_pclmul ghash_clmulni_intel aesni_intel aes_x86_64 lrw gf128mul glue_helper ablk_helper cryptd gpio_ich microcode joydev sb_edac edac_core ipmi_si lpc_ich ipmi_msghandler lp tpm_tis parport wmi mac_hid acpi_pad hid_generic ixgbe isci usbhid dca hid libsas ptp ahci libahci scsi_transport_sas megaraid_sas pps_core mdio [ 204.262815] CPU: 11 PID: 1489 Comm: bash Not tainted 3.13.0-rc7+ #48 [ 204.269993] Hardware name: Intel Corporation BRICKLAND/BRICKLAND, BIOS BRIVTIN1.86B.0047.L09.1312061514 12/06/2013 [ 204.281646] task: ffff8804303a24a0 ti: ffff880440fac000 task.ti: ffff880440fac000 [ 204.290311] RIP: 0010:[<ffffffff814aa1c0>] [<ffffffff814aa1c0>] intel_idle_cpu_init+0x40/0x130 [ 204.300184] RSP: 0018:ffff880440fadd28 EFLAGS: 00010286 [ 204.306192] RAX: ffffffff8227cca0 RBX: ffffe8fff1a03400 RCX: 0000000000000007 [ 204.314244] RDX: ffff88045f400000 RSI: 0000000000000009 RDI: 0000000000001120 [ 204.322296] RBP: ffff880440fadd38 R08: 0000000000000000 R09: 0000000000000001 [ 204.330411] R10: 0000000000000001 R11: 0000000000000000 R12: 000000000000001e [ 204.338482] R13: 00000000ffffffdb R14: 0000000000000001 R15: 0000000000000000 [ 204.346743] FS: 00007f64f7b0c740(0000) GS:ffff88045ce00000(0000) knlGS:0000000000000000 [ 204.355919] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 204.362449] CR2: ffffffff8227cce8 CR3: 0000000444ab0000 CR4: 00000000001407e0 [ 204.370520] Stack: [ 204.372853] 000000000000001e ffffffff81f10240 ffff880440fadd50 ffffffff814aa307 [ 204.381519] ffffffff81ea80e0 ffff880440fadda0 ffffffff8185a230 0000000000000000 [ 204.390196] 000000000000001e 0000000000000002 0000000000000002 0000000000000000 [ 204.398856] Call Trace: [ 204.401683] [<ffffffff814aa307>] cpu_hotplug_notify+0x57/0x70 [ 204.408638] [<ffffffff8185a230>] notifier_call_chain+0x100/0x150 [ 204.415553] [<ffffffff810a7dae>] __raw_notifier_call_chain+0xe/0x10 [ 204.422772] [<ffffffff81072163>] cpu_notify+0x23/0x50 [ 204.428616] [<ffffffff810723b2>] _cpu_up+0x132/0x1a0 [ 204.434361] [<ffffffff8107249d>] cpu_up+0x7d/0xa0 [ 204.439819] [<ffffffff81836c9c>] cpu_subsys_online+0x3c/0x90 [ 204.446345] [<ffffffff81554625>] device_online+0x45/0xa0 [ 204.452471] [<ffffffff815546ce>] online_store+0x4e/0x80 [ 204.458511] [<ffffffff815519a8>] dev_attr_store+0x18/0x30 [ 204.464744] [<ffffffff812a68f1>] sysfs_write_file+0x151/0x1c0 [ 204.471681] [<ffffffff81217ef1>] vfs_write+0xe1/0x160 [ 204.477524] [<ffffffff8121889c>] SyS_write+0x4c/0x90 [ 204.483270] [<ffffffff8185f2ed>] system_call_fastpath+0x1a/0x1f [ 204.490081] Code: 41 54 41 89 fc 8b 3d 48 25 85 01 53 48 8b 1d 30 25 85 01 48 03 1c c5 40 90 fb 81 48 8b 05 19 25 85 01 c7 43 0c 01 00 00 00 66 90 <48> 83 78 48 00 74 4f 41 83 c0 01 41 39 f0 7e 10 48 c7 c7 38 79 [ 204.515723] RIP [<ffffffff814aa1c0>] intel_idle_cpu_init+0x40/0x130 [ 204.522996] RSP <ffff880440fadd28> [ 204.526976] CR2: ffffffff8227cce8 [ 204.530766] ---[ end trace 336f56cc3d1cfc8c ]--- Fixes: 9d046ccb98085 (intel_idle: mark states tables with __initdata tag) Signed-off-by: Jiang Liu <[email protected]> Signed-off-by: Rafael J. Wysocki <[email protected]>
2014-01-09Merge branch 'parisc-3.13' of ↵Linus Torvalds3-46/+6
git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux Pull parisc fix from Helge Deller: "This patch fixes the kmap/kunmap implementation on parisc and finally makes AIO work on parisc" * 'parisc-3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux: parisc: Ensure full cache coherency for kmap/kunmap
2014-01-09Merge branch 'for-3.13-fixes' of ↵Linus Torvalds2-0/+7
git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata Pull libata fixes from Tejun Heo: "Late fixes for libata. Nothing too interesting. Adding missing PM callbacks to satat_sis and an additional PCI ID for ahci" * 'for-3.13-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata: sata_sis: missing PM support ahci: add PCI ID for Marvell 88SE9170 SATA controller
2014-01-08drm/radeon: implement pci config reset for CIK (v3)Alex Deucher2-0/+172
pci config reset is a low level reset that resets the entire chip from the bus interface. It can be more reliable if soft reset fails. v2: fix rebase v3: hide behind module parameter Signed-off-by: Alex Deucher <[email protected]>
2014-01-08drm/radeon: implement pci config reset for SI (v2)Alex Deucher2-0/+116
pci config reset is a low level reset that resets the entire chip from the bus interface. It can be more reliable if soft reset fails. v2: hide behind module parameter Signed-off-by: Alex Deucher <[email protected]>
2014-01-08drm/radeon: implement pci config reset for evergreen/cayman (v2)Alex Deucher3-2/+59
pci config reset is a low level reset that resets the entire chip from the bus interface. It can be more reliable if soft reset fails. v2: put behind module parameter Signed-off-by: Alex Deucher <[email protected]>
2014-01-08drm/radeon: implement pci config reset for r6xx/7xx (v3)Alex Deucher4-0/+112
pci config reset is a low level reset that resets the entire chip from the bus interface. It can be more reliable if soft reset fails. There's not much information still available on r6xx, so r6xx is based on guess-work. v2: put behind module parameter v3: add IGP check Signed-off-by: Alex Deucher <[email protected]>
2014-01-08drm/radeon: add pci config hard resetAlex Deucher2-0/+9
This is used to hard reset the asic. If a soft reset is not able to reset things, a hard reset can be used. Signed-off-by: Alex Deucher <[email protected]>
2014-01-08drm/radeon: add hard_reset module parameterAlex Deucher2-0/+5
Enabling this parameter enables pci config reset, aka hard reset, which is a bus level chip reset. In some cases this works more reliably than a soft reset. Disabled by default. Signed-off-by: Alex Deucher <[email protected]>
2014-01-08parisc: Ensure full cache coherency for kmap/kunmapJohn David Anglin3-46/+6
Helge Deller noted a few weeks ago problems with the AIO support on parisc. This change is the result of numerous iterations on how best to deal with this problem. The solution adopted here is to provide full cache coherency in a uniform manner on all parisc systems. This involves calling flush_dcache_page() on kmap operations and flush_kernel_dcache_page() on kunmap operations. As a result, the copy_user_page() and clear_user_page() functions can be removed and the overall code is simpler. The change ensures that both userspace and kernel aliases to a mapped page are invalidated and flushed. This is necessary for the correct operation of PA8800 and PA8900 based systems which do not support inequivalent aliases. With this change, I have observed no cache related issues on c8000 and rp3440. It is now possible for example to do kernel builds with "-j64" on four way systems. On systems using XFS file systems, the patch recently posted by Mikulas Patocka to "fix crash using XFS on loopback" is needed to avoid a hang caused by an uninitialized lock passed to flush_dcache_page() in the page struct. Signed-off-by: John David Anglin <[email protected]> Cc: [email protected] # v3.9+ Signed-off-by: Helge Deller <[email protected]>
2014-01-08Merge tag 'nfc-fixes-3.13-1' of ↵John W. Linville1-1/+1
git://git.kernel.org/pub/scm/linux/kernel/git/sameo/nfc-fixes Samuel Ortiz <[email protected]> says: "This is the first NFC fixes pull request for 3.13. It only contains one fix for a regression introduced with commit e29a9e2ae165620d. Without this fix, we can not establish a p2p link in target mode. Only initiator mode works." Signed-off-by: John W. Linville <[email protected]>
2014-01-08drm/i915: fix wrong PLL debug messages.Paulo Zanoni1-8/+3
LPT does have PCH refclk, but it's different form the IBX/CPT/PPT one and doesn't use the same structs. It is wrong to have a message saying that "LPT does not has PCH refclk" (sic). While at it, signal that we only want this function on IBX/CPT/PPT by renaming it and adding a WARN. On HSW we also print "0 shared PLLs initialized", but we *do* have shared PLLs on HSW (LCPLL, WRPLL, SPLL) and we *do* initialize them. We just don't use "struct intel_shared_dpll". So remove the debug message. In the future we may want to rename all that "intel shared pll" code to "ibx shared pll", but I'll leave this to another patch. Signed-off-by: Paulo Zanoni <[email protected]> Reviewed-by: Damien Lespiau <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
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