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2020-12-20Merge branches 'clk-amlogic', 'clk-rockchip', 'clk-of', 'clk-freescale' and ↵Stephen Boyd30-49/+1332
'clk-unused' into clk-next - Replace clk-provider.h with of_clk.h when possible * clk-amlogic: clk: meson: g12a: add MIPI DSI Host Pixel Clock dt-bindings: clk: g12a-clkc: add DSI Pixel clock bindings clk: meson: enable building as modules clk: meson: Kconfig: fix dependency for G12A clk: meson: axg: add MIPI DSI Host clock clk: meson: axg: add Video Clocks dt-bindings: clk: axg-clkc: add MIPI DSI Host clock binding dt-bindings: clk: axg-clkc: add Video Clocks * clk-rockchip: clk: rockchip: fix i2s gate bits on rk3066 and rk3188 clk: rockchip: add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocks clk: rockchip: Remove redundant null check before clk_prepare_enable clk: rockchip: Add appropriate arch dependencies * clk-of: xtensa: Replace <linux/clk-provider.h> by <linux/of_clk.h> sh: boards: Replace <linux/clk-provider.h> by <linux/of_clk.h> * clk-freescale: clk: fsl-flexspi: new driver dt-bindings: clock: document the fsl-flexspi-clk device clk: divider: add devm_clk_hw_register_divider_table() clk: qoriq: provide constants for the type clk: fsl-sai: use devm_clk_hw_register_composite_pdata() clk: composite: add devm_clk_hw_register_composite_pdata() clk: fsl-sai: fix memory leak clk: qoriq: Add platform dependencies * clk-unused: clk: scpi: mark scpi_clk_match as maybe unused clk: pwm: drop of_match_ptr from of_device_id table
2020-12-20Merge branches 'clk-doc', 'clk-qcom', 'clk-simplify', 'clk-hw', ↵Stephen Boyd41-388/+5122
'clk-renesas' and 'clk-samsung' into clk-next - Camera clks on Qualcomm SC7180 SoCs - GCC and RPMh clks on Qualcomm SDX55 SoCs - RPMh clks on Qualcomm SM8350 SoCs - LPASS clks on Qualcomm SM8250 SoCs - Add devm variant of clk_notifier_register() - Add clk_hw_get_clk() to generate a struct clk from a struct clk_hw * clk-doc: clk: fix a kernel-doc markup * clk-qcom: (27 commits) clk: qcom: rpmh: add support for SM8350 rpmh clocks dt-bindings: clock: Add RPMHCC bindings for SM8350 clk: qcom: lpasscc: Introduce pm autosuspend for SC7180 clk: qcom: gcc-sc7180: Add 50 MHz clock rate for SDC2 clk: qcom: gcc-sc7180: Use floor ops for sdcc clks clk: qcom: Add GDSC support for SDX55 GCC dt-bindings: clock: Add GDSC in SDX55 GCC clk: qcom: Add support for SDX55 RPMh clocks dt-bindings: clock: Introduce RPMHCC bindings for SDX55 clk: qcom: Add SDX55 GCC support dt-bindings: clock: Add SDX55 GCC clock bindings clk: qcom: Kconfig: Fix spelling mistake "dyanmic" -> "dynamic" clk: qcom: rpmh: Add CE clock on sdm845. dt-bindings: clock: Add entry for crypto engine RPMH clock resource clk: qcom: dispcc-sm8250: handle MMCX power domain clk: qcom: camcc-sc7180: Use runtime PM ops instead of clk ones clk: qcom: lpass-sc7180: Clean up on error in lpass_sc7180_init() clk: qcom: Add support to LPASS AON_CC Glitch Free Mux clocks clk: qcom: Add support to LPASS AUDIO_CC Glitch Free Mux clocks dt-bindings: clock: Add support for LPASS Always ON Controller ... * clk-simplify: clk: remove unneeded dead-store initialization * clk-hw: clk: meson: g12: use devm variant to register notifiers clk: add devm variant of clk_notifier_register clk: meson: g12: drop use of __clk_lookup() clk: add api to get clk consumer from clk_hw clk: avoid devm_clk_release name clash * clk-renesas: dt-bindings: clock: renesas: rcar-usb2-clock-sel: Convert bindings to json-schema clk: renesas: sh73a0: Stop using __raw_*() I/O accessors clk: renesas: r8a774c0: Add RPC clocks clk: renesas: r8a779a0: Fix R and OSC clocks clk: renesas: cpg-mssr: fix kerneldoc of cpg_mssr_priv clk: renesas: rcar-usb2-clock-sel: Replace devm_reset_control_array_get() clk: renesas: r8a774b1: Add RPC clocks clk: renesas: r8a774a1: Add RPC clocks clk: renesas: r8a779a0: Add VIN clocks clk: renesas: r8a779a0: Add CSI4[0-3] clocks MAINTAINERS: Update git repo for Renesas clock drivers clk: renesas: r8a779a0: Make rcar_r8a779a0_cpg_clk_register() static clk: renesas: rcar-gen3: Remove stp_ck handling for SDHI * clk-samsung: clk: samsung: Prevent potential endless loop in the PLL ops clk: samsung: Allow compile testing of Exynos, S3C64xx and S5Pv210
2020-12-10Merge tag 'renesas-clk-for-v5.11-tag3' of ↵Stephen Boyd12-102/+235
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Update git repo branch for Renesas clock drivers - Add camera (CSI) and video-in (VIN) clocks on R-Car V3U - Add RPC (QSPI/HyperFLASH) clocks on RZ/G2M, RZ/G2N, and RZ/G2E - Stop using __raw_*() I/O accessors - One more conversion of DT bindings to json-schema - Minor fixes and improvements * tag 'renesas-clk-for-v5.11-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: dt-bindings: clock: renesas: rcar-usb2-clock-sel: Convert bindings to json-schema clk: renesas: sh73a0: Stop using __raw_*() I/O accessors clk: renesas: r8a774c0: Add RPC clocks clk: renesas: r8a779a0: Fix R and OSC clocks clk: renesas: cpg-mssr: fix kerneldoc of cpg_mssr_priv clk: renesas: rcar-usb2-clock-sel: Replace devm_reset_control_array_get() clk: renesas: r8a774b1: Add RPC clocks clk: renesas: r8a774a1: Add RPC clocks clk: renesas: r8a779a0: Add VIN clocks clk: renesas: r8a779a0: Add CSI4[0-3] clocks MAINTAINERS: Update git repo for Renesas clock drivers clk: renesas: r8a779a0: Make rcar_r8a779a0_cpg_clk_register() static clk: renesas: rcar-gen3: Remove stp_ck handling for SDHI
2020-12-10clk: qcom: rpmh: add support for SM8350 rpmh clocksVinod Koul2-12/+54
This adds the RPMH clocks present in SM8350 SoC Reviewed-by: Bjorn Andersson <[email protected]> Signed-off-by: Vinod Koul <[email protected]> Link: https://lore.kernel.org/r/[email protected] [[email protected]: Move sdx55 to the right place] Signed-off-by: Stephen Boyd <[email protected]>
2020-12-10dt-bindings: clock: Add RPMHCC bindings for SM8350Vinod Koul1-0/+1
Add bindings and update documentation for clock rpmh driver on SM8350. Reviewed-by: Bjorn Andersson <[email protected]> Signed-off-by: Vinod Koul <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2020-12-10clk: qcom: lpasscc: Introduce pm autosuspend for SC7180Taniya Das1-1/+9
The LPASSCC driver's suspend/resume is invoked multiple number of times and thus allow the device to autosuspend for 500ms. Signed-off-by: Taniya Das <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-12-10clk: qcom: gcc-sc7180: Add 50 MHz clock rate for SDC2Douglas Anderson1-0/+1
50 MHz is an incredibly common clock rate for SD cards to run at. It's "high speed" mode in SD (not very fast these days, but it used to be) or: #define HIGH_SPEED_MAX_DTR 50000000 If we don't support this then older "high speed" cards can only run at 25 MHz or at half their normal speed. There doesn't seem to be any reason to skip this clock rate, so add it. Fixes: 17269568f726 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180") Signed-off-by: Douglas Anderson <[email protected]> Link: https://lore.kernel.org/r/20201210102234.2.I26dcc0cee374f5571d9929c9985f463773167e68@changeid Reviewed-by: Bjorn Andersson <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2020-12-10clk: qcom: gcc-sc7180: Use floor ops for sdcc clksDouglas Anderson1-2/+2
I would repeat the same commit message that was in commit 5e4b7e82d497 ("clk: qcom: gcc-sdm845: Use floor ops for sdcc clks") but it seems silly to do so when you could just go read that commit. NOTE: this is actually extra terrible because we're missing the 50 MHz rate in the table (see the next patch AKA ("clk: qcom: gcc-sc7180: Add 50 MHz clock rate for SDC2")). That means then when you run an older SD card it'll try to clock it at 100 MHz when it's only specced to run at 50 MHz max. As you can probably guess that doesn't work super well. Signed-off-by: Douglas Anderson <[email protected]> Fixes: 17269568f726 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180") Link: https://lore.kernel.org/r/20201210102234.1.I096779f219625148900fc984dd0084ed1ba87c7f@changeid Signed-off-by: Stephen Boyd <[email protected]>
2020-12-10clk: scpi: mark scpi_clk_match as maybe unusedKrzysztof Kozlowski1-1/+1
The scpi_clk_match (struct of_device_id) is referenced only with CONFIG_OF builds thus mark it as __maybe_unused: drivers/clk/clk-scpi.c:132:34: warning: ‘scpi_clk_match’ defined but not used [-Wunused-const-variable=] Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Sudeep Holla <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2020-12-10clk: pwm: drop of_match_ptr from of_device_id tableKrzysztof Kozlowski1-1/+1
The driver can match only via the DT table so the table should be always used and the of_match_ptr does not have any sense (this also allows ACPI matching via PRP0001, even though it might be not relevant here). This fixes compile warning (!CONFIG_OF && !CONFIG_MODULES): drivers/clk/clk-pwm.c:139:34: warning: ‘clk_pwm_dt_ids’ defined but not used [-Wunused-const-variable=] Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-12-10dt-bindings: clock: renesas: rcar-usb2-clock-sel: Convert bindings to ↵Yoshihiro Shimoda2-68/+100
json-schema Convert Renesas R-Car USB 2.0 clock selector bindings documentation to json-schema. Signed-off-by: Yoshihiro Shimoda <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/1604543524-31482-1-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven <[email protected]>
2020-12-10clk: renesas: sh73a0: Stop using __raw_*() I/O accessorsGeert Uytterhoeven1-1/+1
There is no reason to keep on using the __raw_{read,write}l() I/O accessors in Renesas ARM driver code. Switch to using the plain {read,write}l() I/O accessors, to have a chance that this works on big-endian. Suggested-by: Arnd Bergmann <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-12-10clk: renesas: r8a774c0: Add RPC clocksLad Prabhakar3-0/+42
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it, as well as the RPC-IF module clock, in the RZ/G2E (R8A774C0) CPG/MSSR driver. Add new clk type CLK_TYPE_GEN3_E3_RPCSRC to register rpcsrc as a fixed clock on R-Car Gen3 E3 (and also RZ/G2E which is identical to E3 SoC), parent and the divider is set based on the register value CPG_RPCCKCR[4:3] which has been set prior to booting the kernel. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Biju Das <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2020-12-10clk: renesas: r8a779a0: Fix R and OSC clocksGeert Uytterhoeven1-3/+10
The R-Car V3U clock driver defines the R and OSC clocks using R-Car Gen3 clock types. However, The R-Car V3U clock driver does not use the R-Car Gen3 clock driver core, hence registering the R and OSC clocks fails: renesas-cpg-mssr e6150000.clock-controller: Failed to register core clock osc: -22 renesas-cpg-mssr e6150000.clock-controller: Failed to register core clock r: -22 Fix this by introducing clock definition macros specific to R-Car V3U. Note that rcar_r8a779a0_cpg_clk_register() already handled the related clock types. Drop the now unneeded include of rcar-gen3-cpg.h. Fixes: 17bcc8035d2d19fc ("clk: renesas: cpg-mssr: Add support for R-Car V3U") Signed-off-by: Geert Uytterhoeven <[email protected]> Tested-by: Yoshihiro Shimoda <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-12-10clk: renesas: cpg-mssr: fix kerneldoc of cpg_mssr_privKrzysztof Kozlowski1-1/+2
The struct cpg_mssr_priv missed proper formatting: drivers/clk/renesas/renesas-cpg-mssr.c:142: warning: cannot understand function prototype: 'struct cpg_mssr_priv ' Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2020-12-10clk: renesas: rcar-usb2-clock-sel: Replace devm_reset_control_array_get()Yejune Deng1-1/+1
devm_reset_control_array_get_shared() looks more readable Signed-off-by: Yejune Deng <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2020-12-10clk: renesas: r8a774b1: Add RPC clocksBiju Das1-0/+8
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it, as well as the RPC-IF module clock, in the RZ/G2N (R8A774B1) CPG/MSSR driver. Inspired by commit 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks"). Signed-off-by: Biju Das <[email protected]> Signed-off-by: Lad Prabhakar <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2020-12-10clk: renesas: r8a774a1: Add RPC clocksBiju Das1-0/+8
Describe the RPCSRC internal clock and the RPC[D2] clocks derived from it, as well as the RPC-IF module clock, in the RZ/G2M (R8A774A1) CPG/MSSR driver. Inspired by commit 94e3935b5756 ("clk: renesas: r8a77980: Add RPC clocks"). Signed-off-by: Biju Das <[email protected]> Signed-off-by: Lad Prabhakar <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2020-12-10clk: renesas: r8a779a0: Add VIN clocksJacopo Mondi1-0/+32
Add definitions of the VIN instance clocks for R-Car V3U. Signed-off-by: Jacopo Mondi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2020-12-10clk: renesas: r8a779a0: Add CSI4[0-3] clocksJacopo Mondi1-0/+4
Add definitions of the CSI-2 receiver clocks for R-Car V3U. Signed-off-by: Jacopo Mondi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2020-12-10MAINTAINERS: Update git repo for Renesas clock driversGeert Uytterhoeven1-1/+1
Align the clock branch name with other renesas-* branches pulled by subsystem maintainers. Signed-off-by: Geert Uytterhoeven <[email protected]> Acked-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-12-10clk: renesas: r8a779a0: Make rcar_r8a779a0_cpg_clk_register() staticGeert Uytterhoeven1-1/+1
When compiling with clang: drivers/clk/renesas/r8a779a0-cpg-mssr.c:156:21: warning: no previous prototype for function 'rcar_r8a779a0_cpg_clk_register' [-Wmissing-prototypes] struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev, ^ drivers/clk/renesas/r8a779a0-cpg-mssr.c:156:1: note: declare 'static' if the function is not intended to be used outside of this translation unit struct clk * __init rcar_r8a779a0_cpg_clk_register(struct device *dev, ^ static Similarly, with sparse: drivers/clk/renesas/r8a779a0-cpg-mssr.c:156:12: warning: symbol 'rcar_r8a779a0_cpg_clk_register' was not declared. Should it be static? There are no users of rcar_r8a779a0_cpg_clk_register() outside this file, so it should be static. Fixes: 17bcc8035d2d19fc ("clk: renesas: cpg-mssr: Add support for R-Car V3U") Reported-by: kernel test robot <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-12-07clk: qcom: Add GDSC support for SDX55 GCCManivannan Sadhasivam2-0/+34
Add GDSC support to control the power supply of power domains in SDX55 GCC. Signed-off-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-12-07dt-bindings: clock: Add GDSC in SDX55 GCCManivannan Sadhasivam1-0/+5
Add GDSC instances in SDX55 GCC block. Signed-off-by: Manivannan Sadhasivam <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2020-12-07clk: qcom: Add support for SDX55 RPMh clocksManivannan Sadhasivam1-0/+20
Add support for following clocks maintained by RPMh in SDX55 SoCs. * BI TCXO * RF_CLK1 * RF_CLK1_AO * RF_CLK2 * RF_CLK2_AO * QPIC (Qualcomm Technologies, Inc. Parallel Interface Controller) Signed-off-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Vinod Koul <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-12-07dt-bindings: clock: Introduce RPMHCC bindings for SDX55Vinod Koul2-0/+2
Add compatible for SDX55 RPMHCC and DT include. Signed-off-by: Vinod Koul <[email protected]> Signed-off-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Acked-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-12-07clk: qcom: Add SDX55 GCC supportNaveen Yadav3-0/+1634
Add Global Clock Controller (GCC) support for SDX55 SoCs from Qualcomm. Signed-off-by: Naveen Yadav <[email protected]> [mani: converted to parent_data, commented critical clocks, cleanups] Signed-off-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Vinod Koul <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-12-07dt-bindings: clock: Add SDX55 GCC clock bindingsVinod Koul2-0/+189
Add device tree bindings for global clock controller on SDX55 SoCs. Signed-off-by: Vinod Koul <[email protected]> Signed-off-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-12-07clk: fsl-flexspi: new driverMichael Walle3-0/+115
Add support for the FlexSPI clock on Freescale Layerscape SoCs. The clock is a simple divider based one and is located inside the device configuration space (DCFG). This will allow switching the SCK frequencies for the FlexSPI interface on the LS1028A and the LX2160A. Signed-off-by: Michael Walle <[email protected]> Link: https://lore.kernel.org/r/[email protected] [[email protected]: Drop modalias, add module table] Signed-off-by: Stephen Boyd <[email protected]>
2020-12-07dt-bindings: clock: document the fsl-flexspi-clk deviceMichael Walle1-0/+55
Signed-off-by: Michael Walle <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] [[email protected]: DT bindings aren't drivers] Signed-off-by: Stephen Boyd <[email protected]>
2020-12-07clk: divider: add devm_clk_hw_register_divider_table()Michael Walle2-0/+61
This will simplify drivers which would only unregister the clk in their remove() op. Signed-off-by: Michael Walle <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-12-07clk: qoriq: provide constants for the typeMichael Walle2-6/+22
To avoid future mistakes in the device tree for the clockgen module, add constants for the clockgen subtype as well as a macro for the PLL divider. Signed-off-by: Michael Walle <[email protected]> Acked-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-12-07clk: fsl-sai: use devm_clk_hw_register_composite_pdata()Michael Walle1-19/+7
Simplify the driver by using that helper and drop the remove() function. Signed-off-by: Michael Walle <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-12-07clk: composite: add devm_clk_hw_register_composite_pdata()Michael Walle2-0/+57
This will simplify drivers which would only unregister the clk in their remove() op. Signed-off-by: Michael Walle <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-12-07clk: fsl-sai: fix memory leakMichael Walle1-0/+12
If the device is removed we don't unregister the composite clock. Fix that. Fixes: 9cd10205227c ("clk: fsl-sai: new driver") Signed-off-by: Michael Walle <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-12-07clk: qoriq: Add platform dependenciesGeert Uytterhoeven1-1/+2
The Freescale QorIQ clock controller is only present on Freescale E500MC and Layerscape SoCs. Add platform dependencies to the CLK_QORIQ config symbol, to avoid asking the user about it when configuring a kernel without E500MC or Layerscape support. Signed-off-by: Geert Uytterhoeven <[email protected]> Acked-by: Arnd Bergmann <[email protected]> Acked-by: Li Yang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-12-07xtensa: Replace <linux/clk-provider.h> by <linux/of_clk.h>Geert Uytterhoeven1-1/+1
The Xtensa time code is not a clock provider, and just needs to call of_clk_init(). Hence it can include <linux/of_clk.h> instead of <linux/clk-provider.h>. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Acked-by: Max Filippov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-12-07sh: boards: Replace <linux/clk-provider.h> by <linux/of_clk.h>Geert Uytterhoeven1-1/+1
The SuperH/J2 DT platform code is not a clock provider, and just needs to call of_clk_init(). Hence it can include <linux/of_clk.h> instead of <linux/clk-provider.h>. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-12-07Merge tag 'v5.11-rockchip-clk-1' of ↵Stephen Boyd3-20/+30
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip Pull Rockchip clk driver updates from Heiko Stuebner: Added arch-dependencies for the newly added per-soc config symbols, an unneeded redundancy removed and making i2s actually work on the rk3066. * tag 'v5.11-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: fix i2s gate bits on rk3066 and rk3188 clk: rockchip: add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocks clk: rockchip: Remove redundant null check before clk_prepare_enable clk: rockchip: Add appropriate arch dependencies
2020-12-07Merge tag 'clk-meson-v5.11-1' of https://github.com/BayLibre/clk-meson into ↵Stephen Boyd16-67/+1157
clk-amlogic Pull Amlogic clk driver updates from Jerome Brunet: - Add MIPI DSI clocks for axg and g12 - Make it possible to build controllers as modules - Fix Video PLL clock dependency * tag 'clk-meson-v5.11-1' of https://github.com/BayLibre/clk-meson: clk: meson: g12a: add MIPI DSI Host Pixel Clock dt-bindings: clk: g12a-clkc: add DSI Pixel clock bindings clk: meson: enable building as modules clk: meson: Kconfig: fix dependency for G12A clk: meson: axg: add MIPI DSI Host clock clk: meson: axg: add Video Clocks dt-bindings: clk: axg-clkc: add MIPI DSI Host clock binding dt-bindings: clk: axg-clkc: add Video Clocks clk: meson: g12: use devm variant to register notifiers clk: add devm variant of clk_notifier_register clk: meson: g12: drop use of __clk_lookup() clk: add api to get clk consumer from clk_hw clk: avoid devm_clk_release name clash
2020-12-04Merge tag 'clk-v5.11-samsung' of ↵Stephen Boyd4-91/+149
https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-samsung Pull Samsung clk driver updates from Sylwester Nawrocki: - Correction of Kconfig dependencies for better compile test coverage - Refactoring of the PLL clocks driver * tag 'clk-v5.11-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk: clk: samsung: Prevent potential endless loop in the PLL ops clk: samsung: Allow compile testing of Exynos, S3C64xx and S5Pv210
2020-11-29clk: rockchip: fix i2s gate bits on rk3066 and rk3188Johan Jonker1-3/+4
The Rockchip PX2/RK3066 uses these bits in CRU_CLKGATE7_CON: hclk_i2s_8ch_gate_en bit 4 (dtsi: i2s0) hclk_i2s0_2ch_gate_en bit 2 (dtsi: i2s1) hclk_i2s1_2ch_gate_en bit 3 (dtsi: i2s2) The Rockchip PX3/RK3188 uses this bit in CRU_CLKGATE7_CON: hclk_i2s_2ch_gate_en bit 2 (dtsi: i2s0) The bits got somehow mixed up in the clk-rk3188.c file. The labels in the dtsi files are not suppose to change. The sclk and hclk names should match for "trace_event=clk_disable,clk_enable", so remove GATE HCLK_I2S0 from the common clock tree and fix the bits in the rk3066 and rk3188 clock tree. Signed-off-by: Johan Jonker <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2020-11-29clk: rockchip: add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocksJohan Jonker1-14/+14
Add CLK_SET_RATE_PARENT to sclk for rk3066a i2s and uart clocks, so that the parent COMPOSITE_FRACMUX and COMPOSITE_NOMUX also update. Signed-off-by: Johan Jonker <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2020-11-29clk: rockchip: Remove redundant null check before clk_prepare_enableXu Wang1-2/+1
Because clk_prepare_enable() already checked NULL clock parameter, so the additional check is unnecessary, just remove it. Signed-off-by: Xu Wang <[email protected]> Acked-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Heiko Stuebner <[email protected]>
2020-11-27clk: qcom: Kconfig: Fix spelling mistake "dyanmic" -> "dynamic"Colin Ian King1-1/+1
There is a spelling mistake in the Kconfig help text. Fix it. Signed-off-by: Colin Ian King <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-11-26clk: meson: g12a: add MIPI DSI Host Pixel ClockNeil Armstrong2-1/+76
This adds the MIPI DSI Host Pixel Clock, unlike AXG, the pixel clock can be different from the VPU ENCL output clock to feed the DSI Host controller with a different clock rate. Signed-off-by: Neil Armstrong <[email protected]> Signed-off-by: Jerome Brunet <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-11-26Merge branch 'v5.11/headers' into v5.11/driversJerome Brunet1-0/+2
2020-11-26dt-bindings: clk: g12a-clkc: add DSI Pixel clock bindingsNeil Armstrong1-0/+2
This adds the MIPI DSI Host Pixel Clock bindings. Signed-off-by: Neil Armstrong <[email protected]> Signed-off-by: Jerome Brunet <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-11-24clk: qcom: rpmh: Add CE clock on sdm845.Thara Gopinath1-0/+2
Qualcomm CE clock resource that is managed by BCM is required by crypto driver to access the core clock. Reviewed-by: Bjorn Andersson <[email protected]> Signed-off-by: Thara Gopinath <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-11-24dt-bindings: clock: Add entry for crypto engine RPMH clock resourceThara Gopinath1-0/+1
Add clock id forc CE clock resource which is required to bring up the crypto engine on sdm845. Reviewed-by: Bjorn Andersson <[email protected]> Signed-off-by: Thara Gopinath <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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