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2014-09-16ARM: imx: add gpt_3m clk for i.mx6qdlAnson Huang2-1/+10
Add gpt_3m clock for i.mx6qdl, as gpt can source clock from OSC, some i.MX6 series SOCs has fixed divider of 8 for gpt clock, so here add a fix clk of gpt_3m. i.MX6Q TO1.0 has no gpt_3m option, so force it to be from ipg_per. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: imx: fix register offset of pll7_usb_host gate clockShawn Guo3-3/+3
There is a copy&paste error on register offset of pll7_usb_host gate clock introduced by i.MX6 PLL bypass support patches. The error breaks the ENET function, because it overwrites the pll6_enet gate bit. Correct the offset for all i.MX6 clock drivers. Thanks to Fugang Duan <[email protected]> for spotting the error. Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: clk-imx6sl: refine clock tree for SSIShengjiu Wang2-4/+14
Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits. Signed-off-by: Shengjiu Wang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: imx: remove ENABLE and BYPASS bits from clk-pllv3 driverShawn Guo1-37/+0
Since ENABLE and BYPASS bits of PLLs are now implemented as separate gate and mux clocks by clock drivers, the code handling these two bits can be removed from clk-pllv3 driver. Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: imx6sx: add BYPASS support for PLL clocksShawn Guo2-10/+78
This is the same change for imx6sx clock driver as "ARM: imx6q: add BYPASS support for PLL clocks" for imx6q. The difference is that only anaclk1 is available on imx6sx. Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: imx6sl: add BYPASS support for PLL clocksShawn Guo2-9/+87
This is the same change for imx6sl clock driver as "ARM: imx6q: add BYPASS support for PLL clocks" for imx6q. The difference is that only anaclk1 is available on imx6sl. Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: imx6q: add BYPASS support for PLL clocksShawn Guo2-11/+83
The imx6q clock driver currently hard-codes all PLL clocks to source from OSC24M without BYPASS support. The patch adds the missing lvds_in clock which is mutually exclusive with lvds_gate, and implements BYPASS and BYPASS_CLK_SRC selection for PLL clocks as per Figure 10-3. Primary Clock Generation in IMX6DQRM, i.e. both BYPASS_CLK_SRC and BYPASS bits are implemented as mux clocks, and ENABLE bit of PLL clocks is implemented as a gate clock after BYPASS mux. Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: imx: add an exclusive gate clock typeShawn Guo3-1/+99
There are a couple of gate clocks are mutually exclusive on i.MX6, i.e. LVDSCLK1_IBEN and LVDSCLK1_OBEN. They cannot be enabled simultaneously. This patches adds an exclusive gate clock type specifically for such case. The clock driver will need to call imx_clk_gate_exclusive() to register a gate clock with parameter exclusive_mask indicating the mask of gate bits which are mutually exclusive to this gate clock. Right now, it only handles the exclusive gate clocks which are defined in a single hardware register, which is the case we're running into today. But it can be extended to handle exclusive gate clocks defined in different registers later if needed. Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: clk-imx6q: refine clock tree for SSIShengjiu Wang1-3/+9
Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits. Signed-off-by: Shengjiu Wang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: clk-imx6q: refine clock tree for ASRCShengjiu Wang2-2/+7
ASRC has "asrc", "asrc_ipg", "asrc_mem" clocks, and they share the same gate bits. Signed-off-by: Shengjiu Wang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: clk-imx6sl: correct the pxp and epdc axi clock selectionsFancy Fang1-3/+4
The parent clocks of IMX6SL_CLK_PXP_AXI_SEL and IMX6SL_CLK_EPDC_AXI_SEL clocks are not the same. So split the epdc_pxp_sels into two different clock selections 'pxp_axi_sels' and 'epdc_axi_sels'. Signed-off-by: Fancy Fang <[email protected]> Signed-off-by: Robby Cai <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: clk-imx6q: refine clock tree for ESAIShengjiu Wang2-6/+8
There are three clock for ESAI, esai_extal, esai_ipg, esai_mem. Rename 'esai' to 'esai_extal', 'esai_ahb' to 'esai_mem', and add 'esai_ipg'. Make the clock for ESAI more clear and align them with imx6sx. Signed-off-by: Shengjiu Wang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: clk-imx6sl: Select appropriate parents for LCDIF clocksFabio Estevam1-0/+7
PLL5 is well suited for being the parent of IMX6SL_CLK_LCDIF_PIX_SEL and PLL2_PFD for IMX6SL_CLK_LCDIF_AXI_SEL. Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: clk-imx6sl: Remove csi_lcdif_sels[]Fabio Estevam1-3/+4
Currently csi_lcdif_sels[] is a shared array for the providing the possible clock parents for csi and lcdif blocks. This is not correct, as csi and lcdif do not share the same clock parents. Introduce csi_sels[] for the csi and lcdif_axi_sels[] for the lcdif clocks in order to describe the parents correctly. Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: imx: clk-vf610: Add USBPHY clocksStefan Agner2-3/+14
This commit adds PLL7 which is required for USBPHY1. It also adds the USB PHY and USB Controller clocks and the gates to enable them. Acked-by: Jingchang Lu <[email protected]> Signed-off-by: Stefan Agner <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: imx: add cpufreq support for i.mx6sxAnson Huang1-0/+3
Add cpufreq support for i.MX6SX, using common i.MX6Q cpufreq driver. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: imx: clk-vf610: introduce clks_init_onStefan Agner1-0/+9
At the end of the boot process, the clock framework might disable required main PLL's. So far, this was no issue since drivers requested clocks, which are descended of the main PLL's (e.g. pll1_pfd1, which provides the system clock). To archive the full 500MHz system clock, DDR clock need to be a descendant of PLL2 rather than PLL1 (DDRC_CLK_SEL set to 0). The bootloader sets up the clocks accordingly before making use of DDR at all. However, in Linux, there is no driver using PLL2, which lead to PLL2 being disabled by the clock framework. With this patch, we make sure that the main system clock and the DDR clock are initially enabled and are kept enabled. Signed-off-by: Stefan Agner <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: i.MX1: Add devicetree supportAlexander Shiyan3-0/+35
This patch adds basic devicetree support for i.MX1 based SoCs. Signed-off-by: Alexander Shiyan <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-16ARM: i.MX6: add more chip revision supportJason Liu2-0/+15
Add more revision support for the new i.MX6DQ tape-out (TO1.5). This TO1.5 is the Rev 1.3 as documented in i.MX6DQ data sheet, because TO1.3 and TO1.4 are never revealed. Signed-off-by: Jason Liu <[email protected]> Signed-off-by: Shawn Guo <[email protected]> Acked-by: Sascha Hauer <[email protected]>
2014-09-11Merge tag 'renesas-dt-timers2-for-v3.18' of ↵Arnd Bergmann8-19/+24
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc Pull "Second Round of Renesas ARM Based SoC DT Timers Updates for v3.18" from Simon Horman: * kzm9g-reference: Enable CMT1 in device tree * Use SoC-specific timer compat strings Signed-off-by: Arnd Bergmann <[email protected]> * tag 'renesas-dt-timers2-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: kzm9g-reference: Enable CMT1 in device tree ARM: shmobile: sh73a0: Add CMT1 device to DT ARM: shmobile: r8a7740: Use SoC-specific 48-bit CMT compat string ARM: shmobile: r8a7779: Use SoC-specific TMU compat string ARM: shmobile: r8a7791: Use SoC-specific 48-bit CMT compat string ARM: shmobile: r7s72100: Use SoC-specific MTU2 compat string ARM: shmobile: r8a7790: Use SoC-specific 48-bit CMT compat string
2014-09-11ARM: shmobile: r8a7794: Remove unnecessary #ifdef CONFIG_USE_OFSimon Horman1-3/+0
The r8a7794 support is always compiled using ARCH_MULTIPLATFORM which selects USE_OF. So #ifdef CONFIG_USE_OF is unnecessary. Reported-by: Arnd Bergmann <[email protected]> Signed-off-by: Simon Horman <[email protected]>
2014-09-10ARM: imx: Remove mach-mxt_td60 board fileFabio Estevam3-286/+0
All the current support of mach-mxt_td60 board can be converted to devicetree. Remove the board file. Cc: Alan Carvalho de Assis <[email protected]> Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2014-09-09ARM: OMAP5+: Reuse OMAP4 PM code for OMAP5 and DRA7Nishanth Menon1-4/+8
OMAP4, OMAP5 and DRA7 share a lot of common logic and data structures. These have been enabled in the previous patches, however, this also means that OMAP5 or DRA7 only builds also need to build OMAP4 logic. Update to reuse OMAP4 logic. This fixes the 'undefined reference to 'omap4_pm_init_early'' in OMAP5 or DRA7 only builds. Fixes: 6af16a1dac5465c ("ARM: DRA7: Add hook in SoC initcalls to enable pm initialization") Fixes: 628ed4717000789 ("ARM: OMAP5: Add hook in SoC initcalls to enable pm initialization") Reported-by: Tony Lindgren <[email protected]> Signed-off-by: Nishanth Menon <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
2014-09-10clk: shmobile: Add r8a7740, sh73a0 SoCs to MSTP bindingsUlrich Hecht1-0/+2
Signed-off-by: Ulrich Hecht <[email protected]> Acked-by: Mike Turquette <[email protected]> Signed-off-by: Simon Horman <[email protected]>
2014-09-09Merge tag 'renesas-soc3-for-v3.18' of ↵Arnd Bergmann4-4/+45
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc Pull "Third Round of Renesas ARM Based SoC Soc Updates for v3.18" from Simon Horman: * Initial r8a7794 SoC support * Support Cortex-A7 in shmobile_init_delay() Signed-off-by: Arnd Bergmann <[email protected]> * tag 'renesas-soc3-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: Initial r8a7794 SoC support ARM: shmobile: support Cortex-A7 in shmobile_init_delay()
2014-09-09Merge tag 'renesas-r8a7740-multiplatform-for-v3.18' of ↵Arnd Bergmann10-524/+300
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc Pull "Renesas ARM Based SoC r8a7740 Multiplatform Updates for v3.18" from Simon Horman: * Enable multiplatform support for r8a7740 SoC and remove its DT-reference C board DTS files. Signed-off-by: Arnd Bergmann <[email protected]> * tag 'renesas-r8a7740-multiplatform-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: armadillo800eva reference: Remove DTS ARM: shmobile: armadillo800eva reference: Remove C board code ARM: shmobile: r8a7740: Add restart callback ARM: shmobile: armadillo800eva: Build DTS for multiplatform ARM: shmobile: armadillo800eva: Sync DTS ARM: shmobile: r8a7740: Multiplatform support
2014-09-09ARM: shmobile: kzm9g-reference: Enable CMT1 in device treeUlrich Hecht2-10/+5
Signed-off-by: Ulrich Hecht <[email protected]> Acked-by: Magnus Damm <[email protected]> Signed-off-by: Simon Horman <[email protected]>
2014-09-09ARM: shmobile: sh73a0: Add CMT1 device to DTUlrich Hecht1-0/+10
Signed-off-by: Ulrich Hecht <[email protected]> Acked-by: Magnus Damm <[email protected]> Signed-off-by: Simon Horman <[email protected]>
2014-09-09ARM: shmobile: r8a7740: Use SoC-specific 48-bit CMT compat stringSimon Horman1-1/+1
In general Renesas hardware is not documented to the extent where the relationship between IP blocks on different SoCs can be assumed although they may appear to operate the same way. Furthermore the documentation typically does not specify a version for individual IP blocks. For these reasons a convention of using the SoC name in place of a version and providing SoC-specific compat strings has been adopted. Although not universally liked this convention is used in the bindings for a number of drivers for Renesas hardware. The purpose of this patch is to make use of the SoC-specific CMT compat string for the r8a7740 48-bit CMT clock source. Signed-off-by: Simon Horman <[email protected]>
2014-09-09ARM: shmobile: r8a7779: Use SoC-specific TMU compat stringSimon Horman1-3/+3
In general Renesas hardware is not documented to the extent where the relationship between IP blocks on different SoCs can be assumed although they may appear to operate the same way. Furthermore the documentation typically does not specify a version for individual IP blocks. For these reasons a convention of using the SoC name in place of a version and providing SoC-specific compat strings has been adopted. Although not universally liked this convention is used in the bindings for a number of drivers for Renesas hardware. The purpose of this patch is to make use of the SoC-specific CMT compat string for the r8a7779 TMU clock source. Signed-off-by: Simon Horman <[email protected]>
2014-09-09ARM: shmobile: r8a7791: Use SoC-specific 48-bit CMT compat stringSimon Horman1-2/+2
In general Renesas hardware is not documented to the extent where the relationship between IP blocks on different SoCs can be assumed although they may appear to operate the same way. Furthermore the documentation typically does not specify a version for individual IP blocks. For these reasons a convention of using the SoC name in place of a version and providing SoC-specific compat strings has been adopted. Although not universally liked this convention is used in the bindings for a number of drivers for Renesas hardware. The purpose of this patch is to make use of the SoC-specific CMT compat string for the r8a7791 48-bit CMT clock source. Signed-off-by: Simon Horman <[email protected]>
2014-09-09ARM: shmobile: r7s72100: Use SoC-specific MTU2 compat stringSimon Horman1-1/+1
In general Renesas hardware is not documented to the extent where the relationship between IP blocks on different SoCs can be assumed although they may appear to operate the same way. Furthermore the documentation typically does not specify a version for individual IP blocks. For these reasons a convention of using the SoC name in place of a version and providing SoC-specific compat strings has been adopted. Although not universally liked this convention is used in the bindings for a number of drivers for Renesas hardware. The purpose of this patch is to make use of the SoC-specific CMT compat string for the r7s72100 MTU2 clock source. Signed-off-by: Simon Horman <[email protected]>
2014-09-09ARM: shmobile: r8a7790: Use SoC-specific 48-bit CMT compat stringSimon Horman1-2/+2
In general Renesas hardware is not documented to the extent where the relationship between IP blocks on different SoCs can be assumed although they may appear to operate the same way. Furthermore the documentation typically does not specify a version for individual IP blocks. For these reasons a convention of using the SoC name in place of a version and providing SoC-specific compat strings has been adopted. Although not universally liked this convention is used in the bindings for a number of drivers for Renesas hardware. The purpose of this patch is to make use of the SoC-specific CMT compat string for the r8a7790 48-bit CMT clock source. Signed-off-by: Simon Horman <[email protected]>
2014-09-09Merge tag 'renesas-r8a7740-ccf-and-timers-for-v3.18' into dt-timers-for-v3.18Simon Horman6-19/+317
Renesas ARM Based SoC R8a7740 CCF and Timers Updates for v3.18 When booting using the r8a7740/armadillo800eva using dt-reference: * Use CCF to initialise clocks via DT * Initialise timers via DT
2014-09-08ARM: dts: OMAP3+: Add PRM interruptNishanth Menon4-0/+4
Provide OMAP3, 4 and OMAP5 with interrupt number for PRM And for DRA7, provide crossbar number for prm interrupt. Signed-off-by: Nishanth Menon <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
2014-09-08ARM: omap: Remove stray ARCH_HAS_OPP referencesMark Brown1-5/+0
OPP is now a normal kernel library selected by its users rather than a feature that architectures need to enable so ARCH_HAS_OPP serves no function any more - remove the selects. Signed-off-by: Mark Brown <[email protected]> Acked-by: Nishanth Menon <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
2014-09-08ARM: DRA7: Add hook in SoC initcalls to enable pm initializationRajendra Nayak2-1/+4
With consolidated code, now we can add the required hooks for DRA7 to enable power management. Signed-off-by: Rajendra Nayak <[email protected]> [[email protected]: minor modifications] Signed-off-by: Nishanth Menon <[email protected]> Reviewed-by: Kevin Hilman <[email protected]> Tested-by: Kevin Hilman <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
2014-09-08Merge branch 'pull/v3.18/for-omap-soc' of ↵Tony Lindgren13-64/+275
https://github.com/nmenon/linux-2.6-playground into omap-for-v3.18/soc
2014-09-08Merge branch 'pull/v3.18/powerdomain-fixes' of ↵Tony Lindgren6-16/+106
https://github.com/nmenon/linux-2.6-playground into omap-for-v3.18/fixes-not-urgent
2014-09-08ARM: OMAP5: Add hook in SoC initcalls to enable pm initializationSantosh Shilimkar2-1/+4
With consolidated code, now we can add the required hooks for OMAP5 to enable power management. Signed-off-by: Santosh Shilimkar <[email protected]> [[email protected]: minor rebase updates] Signed-off-by: Nishanth Menon <[email protected]> Reviewed-by: Kevin Hilman <[email protected]> Tested-by: Kevin Hilman <[email protected]>
2014-09-08ARM: OMAP5 / DRA7: Enable CPU RET on suspendRajendra Nayak4-3/+17
On OMAP5 / DRA7, prevent a CPU powerdomain OFF and resulting MPU OSWR and instead attempt a CPU RET and side effect, MPU RET in suspend. NOTE: the hardware was originally designed to be capable of achieving deep power states such as OFF and OSWR, however due to various issues and risks, deepest valid state was determined to be CSWR - hence we use the errata framework to handle this case. Signed-off-by: Rajendra Nayak <[email protected]> [[email protected]: updates] Signed-off-by: Nishanth Menon <[email protected]> Reviewed-by: Kevin Hilman <[email protected]> Tested-by: Kevin Hilman <[email protected]>
2014-09-08ARM: OMAP5 / DRA7: PM: Provide a dummy startup function for CPU hotplugSantosh Shilimkar1-6/+8
Dont assume that all OMAP4+ code will be able to use OMAP4 hotplug logic. On OMAP5, DRA7, we do not need this in place yet, also, currently the CPU startup pointer is located in omap4_cpu_pm_info instead of cpu_pm_ops. So, isolate the function to hotplug_restart pointer in cpu_pm_ops where it should have belonged, initalize them as per valid startup pointers for OMAP4430/60 as in current logic, however provide dummy_cpu_resume to be the startup location as well. Signed-off-by: Santosh Shilimkar <[email protected]> [[email protected]: split this out of original code and isolate it] Signed-off-by: Nishanth Menon <[email protected]> Reviewed-by: Kevin Hilman <[email protected]> Tested-by: Kevin Hilman <[email protected]>
2014-09-08ARM: OMAP5 / DRA7: PM: Avoid all SAR savesRajendra Nayak1-21/+34
Get rid of all assumptions about always having a sar base on *all* OMAP4+ platforms. We dont need one on DRA7 and it is not necessary at this point for OMAP5 either. Signed-off-by: Rajendra Nayak <[email protected]> [[email protected]: Split and optimize] Signed-off-by: Nishanth Menon <[email protected]> Reviewed-by: Kevin Hilman <[email protected]> Tested-by: Kevin Hilman <[email protected]>
2014-09-08ARM: OMAP5 / DRA7: PM: Enable Mercury retention mode on CPUx powerdomainsSantosh Shilimkar1-0/+16
In addition to the standard power-management technique, the OMAP5 / DRA7 MPU subsystem also employs an SR3-APG (mercury) power management technology to reduce leakage. It allows for full logic and memories retention on MPU_C0 and MPU_C1 and is controlled by the PRCM_MPU. Only "Fast-mode" is supported on the OMAP5 and DRA7 family of processors. Signed-off-by: Santosh Shilimkar <[email protected]> [[email protected]: minor consolidation] Signed-off-by: Nishanth Menon <[email protected]> Reviewed-by: Kevin Hilman <[email protected]> Tested-by: Kevin Hilman <[email protected]>
2014-09-08ARM: OMAP5 / DRA7: PM / wakeupgen: Enables ES2 PM mode by defaultSantosh Shilimkar3-0/+19
Enables MPUSS ES2 power management mode using ES2_PM_MODE in AMBA_IF_MODE register. 0x0: OMAP5 ES1 behavior, CPU cores would enter and exit OFF mode together. Broken! Fortunately, we do not support this anymore. 0x1: OMAP5 ES2, DRA7 behavior, CPU cores are allowed to enter/exit OFF mode independently. This is one time settings thanks to always ON domain. Signed-off-by: Santosh Shilimkar <[email protected]> [[email protected]: minor conflict resolutions, consolidation for DRA7] Signed-off-by: Nishanth Menon <[email protected]> Reviewed-by: Kevin Hilman <[email protected]> Tested-by: Kevin Hilman <[email protected]>
2014-09-08ARM: OMAP5 / DRA7: PM: Set MPUSS-EMIF clock-domain static dependencySantosh Shilimkar1-3/+33
With EMIF clock-domain put under hardware supervised control, memory corruption and untraceable crashes are observed on OMAP5. Further investigation revealed that there is a weakness in the PRCM on this specific dynamic depedency. The recommendation is to set MPUSS static dependency towards EMIF clock-domain to avoid issues. This recommendation holds good for DRA7 family of devices as well. Signed-off-by: Santosh Shilimkar <[email protected]> [[email protected]: DRA7] Signed-off-by: Rajendra Nayak <[email protected]> [[email protected]: conflict resolution, dra7] Signed-off-by: Nishanth Menon <[email protected]> Reviewed-by: Kevin Hilman <[email protected]> Tested-by: Kevin Hilman <[email protected]>
2014-09-08ARM: OMAP5 / DRA7: PM: Update CPU context register offsetSantosh Shilimkar1-4/+9
On OMAP5, RM_CPUi_CPUi_CONTEXT offset has changed. Update the code so that same code works for OMAP4+ devices. DRA7 and OMAP5 have the same context offset as well. Signed-off-by: Santosh Shilimkar <[email protected]> [[email protected]: for DRA7] Signed-off-by: Rajendra Nayak <[email protected]> [[email protected]: rebase, split/merge etc..] Signed-off-by: Nishanth Menon <[email protected]> Reviewed-by: Kevin Hilman <[email protected]> Tested-by: Kevin Hilman <[email protected]>
2014-09-08ARM: AM437x: use pdata quirks for pinctrl informationKeerthy1-0/+3
Provide pdata-quirks for Am437x processor family. Signed-off-by: Keerthy <[email protected]>
2014-09-08ARM: DRA7: use pdata quirks for pinctrl informationNishanth Menon1-0/+3
Provide pdata-quirks for DRA7 processor family. Signed-off-by: Nishanth Menon <[email protected]>
2014-09-08ARM: OMAP5: use pdata quirks for pinctrl informationNishanth Menon1-0/+4
Provide pdata-quirks for OMAP5 processor family. Signed-off-by: Nishanth Menon <[email protected]>
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