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2014-05-27pinctrl/at91: Fix lockup when IRQ on PIOC and PIOD occursAlexander Stein1-0/+13
With commit 80cc3732 (pinctrl/at91: convert driver to use gpiolib irqchip) gpiochip_set_chained_irqchip is called for PIOC, PIOD and PIOE. The associated GPIO chip for the IRQ chip is overwritten each time, because they share the same hard IRQ line. Thus if an IRQ occurs on PIOC or PIOD, gpio_irq_handler will only check on PIOE (the assigned GPIO chip) where no event occured. Thus the IRQ will not be cleared, retriggering the ISR. Fix that (like done before) by only set the PIOC GPIO chip to the IRQ chip and walk the list in the irq handler. Signed-off-by: Alexander Stein <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-05-23pinctrl: msm: switch to using generic GPIO irqchip helpersLinus Walleij2-72/+28
This switches the Qualcomm MSM pin control driver over to using the generic GPIO irqchip helpers. Cc: Stephen Boyd <[email protected]> Cc: Josh Cartwright <[email protected]> Acked-by: Bjorn Andersson <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-05-23pinctrl: sunxi: Fix multiple registration issueMaxime Ripard1-12/+17
When the support for the PRCM muxer on the A31 has been added, the global static pinctl_desc definition has been left as is. Unfortunately, this structure is used to register the pinctrl device, and prior to this registration, we set the name and pins field. Since this structure is shared across instances, that means that the latest registered pinctrl device wins in setting the name, pins and pins numbers, which is not really a good thing. Signed-off-by: Maxime Ripard <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-05-23pinctrl: sunxi: Fix recursive dependencyMaxime Ripard2-13/+16
Fix the following configuration error: drivers/pinctrl/sunxi/Kconfig:3:error: recursive dependency detected! drivers/pinctrl/sunxi/Kconfig:3: symbol PINCTRL_SUNXI is selected by PINCTRL_SUN4I_A10 drivers/pinctrl/sunxi/Kconfig:9: symbol PINCTRL_SUN4I_A10 default value contains PINCTRL_SUNXI Add a new intermedia PINCTRL_SUNXI_COMMON, that superseeds the PINCTRL_SUNXI one. We still need to keep PINCTRL_SUNXI at the moment in order to preserve bisectability. Indeed, during that merge window, we also introduced the MACH_SUN* symbols. Since it's going through different trees, we can't rely on the fact that the options will be there, while ARCH_SUNXI still select PINCTRL_SUNXI. Signed-off-by: Maxime Ripard <[email protected]> Suggested-by: Arnd Bergmann <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-05-23pinctrl: berlin: add the BG2CD pinctrl driverAntoine Tenart3-0/+222
Add the pin-controller driver for the Berlin BG2Q SoC, with definition of its groups and functions. Pin control registers are part of chip/ system control registers, which will be represented by a single node. Until a proper driver for the chip/system control is available, register the corresponding regmap in pinctrl driver probe. Signed-off-by: Antoine Tenart <[email protected]> Acked-by: Sebastian Hesselbarth <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-05-23pinctrl: berlin: add the BG2 pinctrl driverAntoine Tenart3-0/+279
Add the pin-controller driver for the Berlin BG2 SoC, with definition of its groups and functions. Pin control registers are part of chip/ system control registers, which will be represented by a single node. Until a proper driver for the chip/system control is available, register the corresponding regmap in pinctrl driver probe. Signed-off-by: Antoine Tenart <[email protected]> Acked-by: Sebastian Hesselbarth <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-05-23pinctrl: berlin: add the BG2Q pinctrl driverAntoine Tenart3-0/+441
Add the pin-controller driver for the Berlin BG2Q SoC, with definition of its groups and functions. Pin control registers are part of chip/ system control registers, which will be represented by a single node. Until a proper driver for the chip/system control is available, register the corresponding regmap in pinctrl driver probe. Signed-off-by: Antoine Tenart <[email protected]> Acked-by: Sebastian Hesselbarth <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-05-23pinctrl: berlin: add the core pinctrl driver for Marvell Berlin SoCsAntoine Tenart6-0/+420
The Marvell Berlin boards have a group based pinmuxing mechanism. This adds the core driver support. We actually do not need any information about the pins here and only have the definition of the groups. Let's take the example of the uart0 pinmuxing on the BG2Q. Balls BK4 and BH6 are muxed to respectively UART0 RX and TX if the group GSM12 is set to mode 0: Group Modes Offset Base Offset LSB Bit Width GSM12 3 sm_base 0x40 0x10 0x2 Ball Group Mode 0 Mode 1 Mode 2 BK4 GSM12 UART0_RX IrDA0_RX GPIO9 BH6 GSM12 UART0_TX IrDA0_TX GPIO10 So in order to configure BK4 -> UART0_TX and BH6 -> UART0_RX, we need to set (sm_base + 0x40 + 0x10) &= ff3fffff. As pin control registers are part of either chip control or system control registers, that deal with a bunch of other functions we rely on a regmap instead of exclusively remapping any resources. Signed-off-by: Antoine Tenart <[email protected]> Acked-by: Sebastian Hesselbarth <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-05-23pinctrl: baytrail: Add pull type, strength and open drain to debugfs outputMika Westerberg1-4/+51
In case of resolving power management or similar issues it might be useful to have these properties included in the debugfs output. Signed-off-by: Mika Westerberg <[email protected]> Acked-by: Mathias Nyman <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-05-23pinctrl: baytrail: Register GPIO chip after chip->to_irq is setJin Yao1-6/+6
If chip->to_irq is NULL ACPI GPIO helpers don't register GPIO event handlers thus preventing any ACPI GPIO triggered events. Solve this by calling gpiochip_add() after we have set up drivers chip->to_irq hook. Signed-off-by: Jin Yao <[email protected]> Signed-off-by: Mika Westerberg <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-05-23pinctrl: baytrail: Add back Baytrail-T ACPI IDJin Yao2-0/+2
Now that the x86 dynamic IRQ allocation problem has been resolved with commmit 62a08ae2a576 (genirq: x86: Ensure that dynamic irq allocation does not conflict), we can add back Baytrail-T ACPI ID to the pinctrl driver. This makes the driver to work on Asus T100 where it is needed for several things like ACPI GPIO events and SD card detection. References: https://bugzilla.kernel.org/show_bug.cgi?id=68291 Acked-by: Rafael J. Wysocki <[email protected]> Signed-off-by: Jin Yao <[email protected]> Signed-off-by: Mika Westerberg <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-05-23pinctrl: sh-pfc: r8a73a4: Allow Multiplatform BuildMagnus Damm1-0/+3
Add #ifdefs to allow r8a73a4 Multiplatform build. Needed to enable r8a73a4 Multiplatform support. Signed-off-by: Magnus Damm <[email protected]> Signed-off-by: Laurent Pinchart <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-05-23pinctrl: sh-pfc: sh73a0: Allow Multiplatform BuildMagnus Damm1-0/+2
Add #ifdefs to allow sh73a0 Multiplatform build. Needed to enable sh73a0 Multiplatform support. Signed-off-by: Magnus Damm <[email protected]> Signed-off-by: Laurent Pinchart <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-05-23pinctrl: sh-pfc: r8a7740: Allow Multiplatform BuildMagnus Damm1-0/+2
Add #ifdefs to allow r8a7740 Multiplatform build. Needed to enable r8a7740 Multiplatform support. Signed-off-by: Magnus Damm <[email protected]> Signed-off-by: Laurent Pinchart <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-05-23pinctrl: sh-pfc: Don't set the pinmux_irq irq field for multiplatformLaurent Pinchart1-0/+5
In the multiplatform kernel case the IRQs associated with the PFC GPIOs are specified through DT. The pinmux_irq irq field is thus ignored by the code, and doesn't need to be set. This will allow removing the mach/irq.h include from pfc-*.c files that was required for the irq_pin() macro used to initialize the irq field. Signed-off-by: Laurent Pinchart <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-05-23pinctrl: sunxi: Enable the pinctrl Kconfig options by defaultMaxime Ripard1-6/+6
Enable the freshly introduced Kconfig options whenever their matching architecture is enabled. Since the Kconfig symbols for these machines are going through a different tree, keep PINCTRL_SUNXI around for the moment to avoid breaking the defconfig. It should be removed eventually. Signed-off-by: Maxime Ripard <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-05-09dt-bindings: adapt rockchip-pinctrl doc to changed bindingsHeiko Stübner1-8/+20
Introduce the syscons for grf and pmu and deprecate the previous register areas. Signed-off-by: Heiko Stuebner <[email protected]> Tested-by: Max Schwarz <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-05-09pinctrl: rockchip: base regmap supplied by a sysconHeiko Stübner1-19/+28
This allows the basic registers of the general register files to be supplied by a syscon instead of being mapped locally. The GRF registers contain a lot more than pinctrl functions like dma, usb-phy and general soc control and status registers, intermixed with the iomux, pull and drive-strength registers. Signed-off-by: Heiko Stuebner <[email protected]> Tested-by: Max Schwarz <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-05-09pinctrl: rockchip: only map bank0-pull-region when pmu regmap missingHeiko Stübner1-11/+19
When the pmu registers are supplied through a syscon regmap we do not need to map the registers ourself. Signed-off-by: Heiko Stuebner <[email protected]> Tested-by: Max Schwarz <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-05-09pinctrl: rockchip: let pmu registers be supplied by a sysconHeiko Stübner1-2/+15
Currently the pmu registers containing pin pull settings on the rk3188 are mapped locally when bank0 is instantiated. Add an alternative that can resolve the pmu from a syscon phandle. Signed-off-by: Heiko Stuebner <[email protected]> Tested-by: Max Schwarz <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-05-09pinctrl: rockchip: rockchip_pinctrl in rockchip_get_bank_dataHeiko Stübner1-8/+9
Convert rockchip_get_bank_data to use the struct rockchip_pinctrl because later on we need to check a value from it when registering the gpio banks. Signed-off-by: Heiko Stuebner <[email protected]> Tested-by: Max Schwarz <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-05-09pinctrl: rockchip: use regmaps instead of raw mappingsHeiko Stübner2-36/+81
This allows us to use syscons in the future. Signed-off-by: Heiko Stuebner <[email protected]> Tested-by: Max Schwarz <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-05-09pinctrl: rockchip: do not require 2nd register areaHeiko Stübner2-3/+14
Deprecate secondary register area for rk3188 pulls. Instead use big enough initial mapping of grf registers to catch all. The now deprecated register is still supported though. Signed-off-by: Heiko Stuebner <[email protected]> Tested-by: Max Schwarz <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-05-09Merge tag 'sunxi-pinctrl-for-3.16' of https://github.com/mripard/linux into ↵Linus Walleij14-4611/+4524
devel Pinctrl cleanup and reworks for 3.16 This serie of patch: - Moves the Allwinner pinctrl driver to a folder of its own - removes the sunxi-pinctrl-pins header, and split the driver into a core one, with all the logic, and smaller drivers, one for each SoC, that declare the pins, and will provide to the core the set of pins. - And does a few cleanups here and there.
2014-05-04pinctrl: sunxi: Move the reset handling functions out of the coreMaxime Ripard2-16/+23
The way that reset is handled right now is that it is made optional for every pinctrl driver, while actually, it isn't used at all for the main pin controllers so far, and while it's mandatory for the A31's secondary pin controller. Move the reset functions out of the core and in the driver, where they can be made mandatory. Signed-off-by: Maxime Ripard <[email protected]>
2014-05-04pinctrl: sunxi: Introduce per-driver Kconfig optionsMaxime Ripard2-6/+30
Add one Kconfig option for each driver. This will allow to better control which driver is enabled, instead of having either all or nothing. Signed-off-by: Maxime Ripard <[email protected]>
2014-05-04pinctrl: sunxi: Move Allwinner A20 pinctrl driver to a driver of its ownMaxime Ripard3-37/+33
Move the pin description to a driver specific to be. This is the final step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. We can finally remove that header, and remove all the driver part of the pinctrl-sunxi core. Signed-off-by: Maxime Ripard <[email protected]>
2014-05-04pinctrl: sunxi: Move Allwinner A31 special pins driver to a driver of its ownMaxime Ripard4-75/+123
Move the pin description to a driver specific to be. This is one more step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. Signed-off-by: Maxime Ripard <[email protected]>
2014-05-04pinctrl: sunxi: Move Allwinner A31 pinctrl driver to a driver of its ownMaxime Ripard4-821/+866
Move the pin description to a driver specific to be. This is one more step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. Signed-off-by: Maxime Ripard <[email protected]>
2014-05-04pinctrl: sunxi: Move Allwinner A13 pinctrl driver to a driver of its ownMaxime Ripard4-367/+412
Move the pin description to a driver specific to be. This is one more step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. Signed-off-by: Maxime Ripard <[email protected]>
2014-05-04pinctrl: sunxi: Move Allwinner A10s pinctrl driver to a driver of its ownMaxime Ripard4-646/+691
Move the pin description to a driver specific to be. This is one more step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. Signed-off-by: Maxime Ripard <[email protected]>
2014-05-04pinctrl: sunxi: Move Allwinner A10 pinctrl driver to a driver of its ownMaxime Ripard4-995/+1043
Move the pin description to a driver specific to be. This is one more step toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all the Allwinner SoCs in a single header, that would have in turn result in having these structures in the final binary as many times as the header was included. Signed-off-by: Maxime Ripard <[email protected]>
2014-05-04pinctrl: sunxi: Libraryse the driverMaxime Ripard2-7/+17
This will allow to have multiple drivers using the same core code, and eventually, retire pinctrl-sunxi-pins.h Signed-off-by: Maxime Ripard <[email protected]>
2014-05-03pinctrl: sunxi: Switch to devm_ioremap_resourceMaxime Ripard1-3/+5
The previous code was calling of_iomap, which doesn't do any resource management, and doesn't call request_mem_region either. Use devm_ioremap_resource that do both. Signed-off-by: Maxime Ripard <[email protected]>
2014-05-03pinctrl: sunxi: Replace hardcoded pin defines by a macroMaxime Ripard2-1089/+729
We previously had an evergrowing (and exhaustive) list of the pins that could be used on any Allwinner SoCs. These defines were then used by each pinctrl driver to declare the list of functions for this pin. Since it's pretty much all boilerplate, we can remove it just by a single macro. Signed-off-by: Maxime Ripard <[email protected]>
2014-05-03pinctrl: sunxi: Move the Allwinner pinctrl driver to its own directoryMaxime Ripard7-7/+12
This will allow to create numerous files without crippling the main pinctrl directory. Signed-off-by: Maxime Ripard <[email protected]>
2014-05-03pinctrl: sunxi: Drop unused structure membersMaxime Ripard1-2/+0
The ranges and nranges were never used. Remove them. Signed-off-by: Maxime Ripard <[email protected]>
2014-05-03pinctrl: sunxi: Add const qualifier to the pin descriptorMaxime Ripard2-2/+2
The pins description structure were declared as const, but the of_device_id data magic was losing it silently. Make sure we have it on both sides. And now that we're using const, we can also remove the useless cast in probe. Signed-off-by: Maxime Ripard <[email protected]>
2014-05-02pinctrl: qcom: Correct name for pin 0Andy Gross1-1/+1
Fix copy/paste error in pinctrl_pin_desc for pin 0. Signed-off-by: Andy Gross <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-04-24pinctrl: mvebu: new driver for Orion platformsThomas Petazzoni4-0/+357
This commit extends the pinctrl mvebu logic with a new driver to cover Orion5x SoC. It supports the definitions for the 5181l, 5182 and 5281 variants of Orion5x, which are the three ones supported by the old style MPP code in arch/arm/mach-orion5x/. Signed-off-by: Thomas Petazzoni <[email protected]> Acked-by: Sebastian Hesselbarth <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-04-23pinctrl: rockchip: implement PIN_CONFIG_OUTPUT handlingHeiko Stübner1-0/+40
In some cases it is nice to be able to simply control a gpio output via the PIN_CONFIG_OUTPUT option without having a driver control it. Thus add support for it to the rockchip pinctrl driver. Signed-off-by: Heiko Stuebner <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-04-23pinctrl: rockchip: return a complete config in pinconf_getHeiko Stübner1-2/+5
Till now pinconf_get only set the argument value into the config parameter effectively removing the actual config param value. As other pinctrl drivers do, it might be nicer to keep the config param intact. Therefore construct a real pinconfig value from param and arg in pinconf_get Signed-off-by: Heiko Stuebner <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-04-23pinctrl: sirf: switch driver to use gpiolib irqchip helpersLinus Walleij2-63/+27
This switches the SiRF pinctrl driver over to using the gpiolib irqchip helpers simplifying some of the code. Signed-off-by: Barry Song <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-04-23pinctrl: sirf: wrap all gpio banks into one gpio_chipBarry Song1-126/+91
all gpio banks are in one chip, that makes software clean in mapping irq and gpio. Signed-off-by: Barry Song <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-04-23pinctrl: sirf: rename inlined accessorLinus Walleij1-7/+7
The sirfsoc_irqchip_to_bank() is obviously misnamed, as it is not converting an irqchip to a bank but converts a gpiochip to a bank so rename it sirfsoc_gpiochip_to_bank(). Acked-by: Barry Song <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-04-23dt: Document Qualcomm IPQ8064 pinctrl bindingAndy Gross1-0/+95
Define a new binding for the Qualcomm TLMMv2 based pin controller inside the IPQ8064. Signed-off-by: Andy Gross <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-04-23pinctrl: qcom: Add definitions for IPQ8064Andy Gross3-0/+662
This adds pinctrl definitions for the GPIO pins of the TLMM v2 block in the Qualcomm IPQ8064 platform. Signed-off-by: Andy Gross <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-04-23pinctrl: sunxi: list all pinctrl compatible stringsBoris BREZILLON1-2/+7
List all sunxi pinctrl compatible strings in order to be able to grep for those values. Signed-off-by: Boris BREZILLON <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-04-23pinctrl: exynos: Add driver data for Exynos3250Tomasz Figa3-0/+70
This patch adds driver data (bank list and EINT layout) for Exynos3250 to pinctrl-exynos driver. Exynos3250 includes 158 multi-functional input/output ports. There are 23 general port groups. Changes from v1: - Add signed-off of sender - Post only separated patch for pinctrl from following patchset(v1) : https://lkml.org/lkml/2014/4/10/286 Cc: Thomas Abraham <[email protected]> Cc: Linus Walleij <[email protected]> Cc: Kukjin Kim <[email protected]> Signed-off-by: Tomasz Figa <[email protected]> Signed-off-by: Chanwoo Choi <[email protected]> Acked-by: Kyungmin Park <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2014-04-22pinctrl/at91: Fix mask creation in at91_gpio_dbg_showAlexander Stein1-2/+1
pin_to_mask expects a bank pin number. So do not add the chip base. Without that patch cat /sys/kernel/debug/gpio looks like that: GPIOs 0-31, platform/fffff200.gpio, fffff200.gpio: [spi32766.0] GPIOfffff200.gpio5: [gpio] set [ads7846_pendown] GPIOfffff200.gpio15: [gpio] set [ohci_vbus] GPIOfffff200.gpio21: [gpio] set [ohci_vbus] GPIOfffff200.gpio24: [gpio] set [button1] GPIOfffff200.gpio28: [gpio] clear [button2] GPIOfffff200.gpio29: [gpio] clear GPIOs 32-63, platform/fffff400.gpio, fffff400.gpio: [sda] GPIOfffff400.gpio4: [periph A] [scl] GPIOfffff400.gpio5: [periph A] [spi32766.3] GPIOfffff400.gpio11: [periph A] [error] GPIOfffff400.gpio22: [periph A] [run] GPIOfffff400.gpio23: [periph A] GPIOs 64-95, platform/fffff600.gpio, fffff600.gpio: [reset_pin] GPIOfffff600.gpio29: [periph A] GPIOs 96-127, platform/fffff800.gpio, fffff800.gpio: [led1] GPIOfffff800.gpio5: [periph A] [led2] GPIOfffff800.gpio6: [periph A] [led3] GPIOfffff800.gpio7: [periph A] [led4] GPIOfffff800.gpio8: [periph A] GPIOs 128-159, platform/fffffa00.gpio, fffffa00.gpio: [button3] GPIOfffffa00.gpio10: [periph A] [button4] GPIOfffffa00.gpio12: [periph A] Note that every bank despite bank 0 only shows "periph A" which are obviously used as GPIOs. Signed-off-by: Alexander Stein <[email protected]> Acked-by: Alexandre Belloni <[email protected]> Acked-by: Nicolas Ferre <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
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