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2017-06-09mux: adg792a: always require I2C supportArnd Bergmann1-1/+1
COMPILE_TEST makes no sense when I2C is disabled, as the driver cannot compile in that configuration: drivers/mux/mux-adg792a.c: In function 'adg792a_write_cmd': drivers/mux/mux-adg792a.c:34:9: error: implicit declaration of function 'i2c_smbus_write_byte_data'; did you mean 'i2c_set_clientdata'? [-Werror=implicit-function-declaration] drivers/mux/mux-adg792a.o: In function `adg792a_driver_init': mux-adg792a.c:(.init.text+0x14): undefined reference to `i2c_register_driver' drivers/mux/mux-adg792a.o: In function `adg792a_probe': mux-adg792a.c:(.text.adg792a_probe+0x94): undefined reference to `i2c_smbus_write_byte_data' drivers/mux/mux-adg792a.o: In function `adg792a_set': mux-adg792a.c:(.text.adg792a_set+0x80): undefined reference to `i2c_smbus_write_byte_data' Fixes: afda08c4caa9 ("mux: adg792a: add mux controller driver for ADG792A/G") Signed-off-by: Arnd Bergmann <[email protected]> Reviewed-by: Peter Rosin <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09nvmem: rockchip-efuse: add support for rk322x-efuseFinley Xiao2-0/+5
This adds the necessary data for handling eFuse on the rk322x. Signed-off-by: Finley Xiao <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Srinivas Kandagatla <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09nvmem: core: add locking to nvmem_find_cellHeiner Kallweit1-1/+7
Adding entries to nvmem_cells and deleting entries from it is protected by nvmem_cells_mutex. Therefore this mutex should also protect iterating over the list. Signed-off-by: Heiner Kallweit <[email protected]> Signed-off-by: Srinivas Kandagatla <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09nvmem: core: Call put_device() in nvmem_unregister()Andrey Smirnov1-0/+1
Call put_device() in nvmem_unregister() to make sure nvmem_release gets called freeing up allocated resources. Cc: [email protected] Cc: Srinivas Kandagatla <[email protected]> Cc: Maxime Ripard <[email protected]> Signed-off-by: Andrey Smirnov <[email protected]> Signed-off-by: Srinivas Kandagatla <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09nvmem: core: fix leaks on registration errorsJohan Hovold1-5/+8
Make sure to deregister and release the nvmem device and underlying memory on registration errors. Note that the private data must be freed using put_device() once the struct device has been initialised. Also note that there's a related reference leak in the deregistration function as reported by Mika Westerberg which is being fixed separately. Fixes: b6c217ab9be6 ("nvmem: Add backwards compatibility support for older EEPROM drivers.") Fixes: eace75cfdcf7 ("nvmem: Add a simple NVMEM framework for nvmem providers") Cc: stable <[email protected]> # 4.3 Cc: Andrew Lunn <[email protected]> Cc: Srinivas Kandagatla <[email protected]> Cc: Mika Westerberg <[email protected]> Signed-off-by: Johan Hovold <[email protected]> Acked-by: Andrey Smirnov <[email protected]> Signed-off-by: Srinivas Kandagatla <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09nvmem: correct Broadcom OTP controller driver writesOza Pawandeep1-2/+2
- use data write offset to write otp data instead of read offset - use OTP program command 0x8 to write otp with ECC rather than just command 0xA without ECC Fixes: 9d59c6e8ae27 ("nvmem: Add the Broadcom OTP controller driver") Signed-off-by: Oza Pawandeep <[email protected]> Signed-off-by: Scott Branden <[email protected]> Signed-off-by: Srinivas Kandagatla <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09w1: Add subsystem kernel public interfaceAndrew F. Davis36-260/+208
Like other subsystems we should be able to define slave devices outside of the w1 directory. To do this we move public facing interface definitions to include/linux/w1.h and rename the internal definition file to w1_internal.h. As w1_family.h and w1_int.h contained almost entirely public driver interface definitions we simply removed these files and moved the remaining definitions into w1_internal.h. With this we can now start to move slave devices out of w1/slaves and into the subsystem based on the function they implement, again like other drivers. Signed-off-by: Andrew F. Davis <[email protected]> Reviewed-by: Sebastian Reichel <[email protected]> Acked-by: Evgeniy Polyakov <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09drivers/fsi: Add module license to core driverChristopher Bostic1-0/+1
Add missing MODULE_LICENSE("GPL") to the core FSI driver. Signed-off-by: Christopher Bostic <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09drivers/fsi: Use asynchronous slave modeJeremy Kerr3-1/+24
For slaves that are behind a software-clocked master, we want FSI CFAMs to run asynchronously to the FSI clock, so set up our slaves to be in async mode. Signed-off-by: Jeremy Kerr <[email protected]> Signed-off-by: Christopher Bostic <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09drivers/fsi: Add hub master supportChristopher Bostic3-0/+336
Add an engine driver to expose a "hub" FSI master - which has a set of control registers in the engine address space, and uses a chunk of the slave address space for actual FSI communication. Additional changes from Jeremy Kerr <[email protected]>. Signed-off-by: Christopher Bostic <[email protected]> Signed-off-by: Jeremy Kerr <[email protected]> Signed-off-by: Joel Stanley <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09drivers/fsi: Add SCOM FSI client device driverChristopher Bostic3-0/+269
Create a simple SCOM engine device driver that reads and writes its control registers via an FSI bus. Includes changes from Edward A. James <[email protected]>. Signed-off-by: Christopher Bostic <[email protected]> Signed-off-by: Joel Stanley <[email protected]> Signed-off-by: Edward A. James <[email protected]> Signed-off-by: Jeremy Kerr <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09drivers/fsi/gpio: Add tracepoints for GPIO masterJeremy Kerr2-0/+77
Trace low level input/output GPIO operations. Signed-off-by: Jeremy Kerr <[email protected]> Signed-off-by: Christopher Bostic <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09drivers/fsi: Add GPIO based FSI masterChristopher Bostic3-0/+607
Implement a FSI master using GPIO. Will generate FSI protocol for read and write commands to particular addresses. Sends master command and waits for and decodes a slave response. Includes changes from Edward A. James <[email protected]> and Jeremy Kerr <[email protected]>. Signed-off-by: Edward A. James <[email protected]> Signed-off-by: Jeremy Kerr <[email protected]> Signed-off-by: Christopher Bostic <[email protected]> Signed-off-by: Joel Stanley <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09drivers/fsi: Document FSI master sysfs files in ABIChristopher Bostic1-0/+38
Add info for sysfs scan file in Documentaiton ABI/testing Signed-off-by: Christopher Bostic <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09drivers/fsi: Add error handling for slaveJeremy Kerr1-7/+114
This change implements error handling in the FSI core, by cleaining up and retrying failed operations, using the SISC, TERM and BREAK facilities. Signed-off-by: Jeremy Kerr <[email protected]> Signed-off-by: Christopher Bostic <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09drivers/fsi: Add tracepoints for low-level operationsJeremy Kerr2-6/+148
Trace low level read and write FSI bus operations. Signed-off-by: Jeremy Kerr <[email protected]> Signed-off-by: Joel Stanley <[email protected]> Signed-off-by: Christopher Bostic <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09drivers/fsi: expose direct-access slave APIJeremy Kerr2-6/+36
Allow drivers to access the slave address ranges. Signed-off-by: Jeremy Kerr <[email protected]> Signed-off-by: Joel Stanley <[email protected]> Signed-off-by: Christopher Bostic <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09drivers/fsi: Add sysfs files for FSI master & slave accessesJeremy Kerr1-0/+116
This change adds a 'raw' file for reads & writes, and a 'term' file for the TERM command, and a 'break' file for issuing a BREAK. Signed-off-by: Jeremy Kerr <[email protected]> Signed-off-by: Joel Stanley <[email protected]> Signed-off-by: Christopher Bostic <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09drivers/fsi: Add client driver register utilitiesChristopher Bostic2-0/+29
Add driver_register and driver_unregister wrappers for FSI. Signed-off-by: Christopher Bostic <[email protected]> Signed-off-by: Joel Stanley <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09drivers/fsi: Add documentation for GPIO bindingsChristopher Bostic1-0/+24
Add fsi master gpio device tree binding documentation. Includes changes from Jeremy Kerr <[email protected]>. Signed-off-by: Christopher Bostic <[email protected]> Signed-off-by: Jeremy Kerr <[email protected]> Signed-off-by: Joel Stanley <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09drivers/fsi: Add master unscanChristopher Bostic1-0/+44
Allow a master to undo a previous scan. Should a master scan a bus twice it will need to ensure it doesn't double register any previously detected device. Signed-off-by: Christopher Bostic <[email protected]> Signed-off-by: Joel Stanley <[email protected]> ---- v7 - Unscan when unregistering master - Remove leading '__'s from function names - Return fail state for sysfs rescan file Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09drivers/fsi: Add device read/write/peek APIJeremy Kerr2-2/+55
This change introduces the fsi device API: simple read, write and peek accessors for the devices' address spaces. Includes contributions from Christopher Bostic <[email protected]> and Edward A. James <[email protected]>. Signed-off-by: Edward A. James <[email protected]> Signed-off-by: Jeremy Kerr <[email protected]> Signed-off-by: Christopher Bostic <[email protected]> Signed-off-by: Joel Stanley <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09drivers/fsi: scan slaves & register devicesJeremy Kerr2-1/+131
Now that we have fsi_slave devices, scan each for endpoints, and register them on the fsi bus. Includes contributions from Christopher Bostic <[email protected]>. Signed-off-by: Jeremy Kerr <[email protected]> Signed-off-by: Christopher Bostic <[email protected]> Signed-off-by: Joel Stanley <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09drivers/fsi: Set slave SMODE to init communicationChristopher Bostic1-0/+75
Set CFAM to appropriate ID so that the controlling master can manage link memory ranges. Add slave engine register definitions. Includes changes from Jeremy Kerr <[email protected]>. Signed-off-by: Jeremy Kerr <[email protected]> Signed-off-by: Christopher Bostic <[email protected]> Signed-off-by: Joel Stanley <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09drivers/fsi: Implement slave initialisationJeremy Kerr2-2/+66
Implement fsi_slave_init: if we can read a chip ID, create fsi_slave devices and register with the driver core. Includes changes from Christopher Bostic <[email protected]>. Signed-off-by: Jeremy Kerr <[email protected]> Signed-off-by: Christopher Bostic <[email protected]> Signed-off-by: Joel Stanley <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09drivers/fsi: Set up links for slave communicationChristopher Bostic1-2/+35
Enable each link and send a break command, and try to detect a slave by reading from the SMODE register. Signed-off-by: Christopher Bostic <[email protected]> Signed-off-by: Joel Stanley <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09drivers/fsi: Add slave & master read/write APIsJeremy Kerr1-0/+92
Introduce functions to perform reads/writes on the slave address space; these simply pass the request on the slave's master with the correct link and slave ID. We implement these on top of similar helpers for the master. Signed-off-by: Jeremy Kerr <[email protected]> Signed-off-by: Joel Stanley <[email protected]> Signed-off-by: Chris Bostic <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09lib: Add crc4 moduleJeremy Kerr4-0/+63
Add a little helper for crc4 calculations. This works 4-bits-at-a-time, using a simple table approach. We will need this in the FSI core code, as well as any master implementations that need to calculate CRCs in software. Signed-off-by: Jeremy Kerr <[email protected]> Signed-off-by: Chris Bostic <[email protected]> Signed-off-by: Joel Stanley <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09drivers/fsi: Add empty master scanJeremy Kerr1-2/+23
When a new fsi master is added, we will need to scan its links, and slaves attached to those links. This change introduces a little shell to iterate the links, which we will populate with the actual slave scan in a later change. Signed-off-by: Jeremy Kerr <[email protected]> Signed-off-by: Chris Bostic <[email protected]> Signed-off-by: Joel Stanley <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09drivers/fsi: Add slave definitionJeremy Kerr1-0/+10
Add the initial fsi slave device, which is private to the core code. This will be a child of the master, and parent to endpoint devices. Signed-off-by: Jeremy Kerr <[email protected]> Signed-off-by: Chris Bostic <[email protected]> Signed-off-by: Joel Stanley <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09drivers/fsi: Add fsi master definitionJeremy Kerr2-0/+76
Add a `struct fsi_master` to represent a FSI master controller. FSI master drivers register one of these structs to provide device-specific of the standard operations: read/write/term/break and link control. Includes changes from Edward A. James <[email protected]> & Jeremy Kerr <[email protected]>. Signed-off-by: Jeremy Kerr <[email protected]> Signed-off-by: Chris Bostic <[email protected]> Signed-off-by: Joel Stanley <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09config: android-base: disable CONFIG_NFSD and CONFIG_NFS_FSRoberto Pereira1-0/+2
Disable Network file system support. Reviewed-at: https://android-review.googlesource.com/#/c/409559/ Signed-off-by: Roberto Pereira <[email protected]> [AmitP: cherry-picked this change from Android common kernel and updated commit message] Signed-off-by: Amit Pundir <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09config: android-base: add CGROUP_BPFChenbo Feng1-0/+1
Add CONFIG_CGROUP_BPF as a default configuration in android base config since it is used to replace XT_QTAGUID in future. Reviewed-at: https://android-review.googlesource.com/#/c/400374/ Signed-off-by: Chenbo Feng <[email protected]> [AmitP: cherry-picked this change from Android common kernel] Signed-off-by: Amit Pundir <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09config: android-base: add CONFIG_MODULES optionGreg Kroah-Hartman1-1/+3
This adds CONFIG_MODULES, CONFIG_MODULE_UNLOAD, and CONFIG_MODVERSIONS which are required by the O release. Reviewed-at: https://android-review.googlesource.com/#/c/364554/ Signed-off-by: Greg Kroah-Hartman <[email protected]> [AmitP: cherry-picked this change from Android common kernel] Signed-off-by: Amit Pundir <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09config: android-base: add CONFIG_IKCONFIG optionGreg Kroah-Hartman1-0/+2
This adds CONFIG_IKCONFIG and CONFIG_IKCONFIG_PROC options, which are a requirement for the O release. Reviewed-at: https://android-review.googlesource.com/#/c/364553/ Signed-off-by: Greg Kroah-Hartman <[email protected]> [AmitP: cherry-picked this change from Android common kernel] Signed-off-by: Amit Pundir <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09config: android-recommended: enable CONFIG_CPU_SW_DOMAIN_PANSami Tolvanen1-1/+2
Enable CPU domain PAN to ensure that normal kernel accesses are unable to access userspace addresses. Reviewed-at: https://android-review.googlesource.com/#/c/334035/ Signed-off-by: Sami Tolvanen <[email protected]> [AmitP: cherry-picked this change from Android common kernel, updated the commit message and re-placed the CONFIG_STRICT_KERNEL_RWX config in sorted order] Signed-off-by: Amit Pundir <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09config: android-base: disable CONFIG_USELIB and CONFIG_FHANDLEMax Shi1-0/+2
Turn off the two kernel configs to disable related system ABI. Reviewed-at: https://android-review.googlesource.com/#/c/264976/ Signed-off-by: Max Shi <[email protected]> [AmitP: cherry-picked this change from Android common kernel] Signed-off-by: Amit Pundir <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09config: android-recommended: enable CONFIG_ARM64_SW_TTBR0_PANSami Tolvanen1-0/+1
Enable PAN emulation using TTBR0_EL1 switching. Reviewed-at: https://android-review.googlesource.com/#/c/325997/ Signed-off-by: Sami Tolvanen <[email protected]> [AmitP: cherry-picked this change from Android common kernel and updated the commit message] Signed-off-by: Amit Pundir <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09config: android-recommended: enable fstack-protector-strongJeff Vander Stoep1-0/+1
If compiler has stack protector support, set CONFIG_CC_STACKPROTECTOR_STRONG. Reviewed-at: https://android-review.googlesource.com/#/c/238388/ Signed-off-by: Jeff Vander Stoep <[email protected]> [AmitP: cherry-picked this change from Android common kernel] Signed-off-by: Amit Pundir <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09arm64: dts: qcom: msm8916: Add debug unitLeo Yan1-0/+32
Add debug unit on Qualcomm msm8916 based platforms, including the DragonBoard 410c board. Signed-off-by: Leo Yan <[email protected]> Reviewed-by: Mathieu Poirier <[email protected]> Acked-by: Andy Gross <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09arm64: dts: hi6220: register debug moduleLeo Yan1-0/+64
Bind debug module driver for Hi6220. Signed-off-by: Leo Yan <[email protected]> Reviewed-by: Mathieu Poirier <[email protected]> Acked-by: Wei Xu <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09coresight: add support for CPU debug moduleLeo Yan3-0/+715
Coresight includes debug module and usually the module connects with CPU debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has description for related info in "Part H: External Debug". Chapter H7 "The Sample-based Profiling Extension" introduces several sampling registers, e.g. we can check program counter value with combined CPU exception level, secure state, etc. So this is helpful for analysis CPU lockup scenarios, e.g. if one CPU has run into infinite loop with IRQ disabled. In this case the CPU cannot switch context and handle any interrupt (including IPIs), as the result it cannot handle SMP call for stack dump. This patch is to enable coresight debug module, so firstly this driver is to bind apb clock for debug module and this is to ensure the debug module can be accessed from program or external debugger. And the driver uses sample-based registers for debug purpose, e.g. when system triggers panic, the driver will dump program counter and combined context registers (EDCIDSR, EDVIDSR); by parsing context registers so can quickly get to know CPU secure state, exception level, etc. Some of the debug module registers are located in CPU power domain, so this requires the CPU power domain stays on when access related debug registers, but the power management for CPU power domain is quite dependent on SoC integration for power management. For the platforms which with sane power controller implementations, this driver follows the method to set EDPRCR to try to pull the CPU out of low power state and then set 'no power down request' bit so the CPU has no chance to lose power. If the SoC has not followed up this design well for power management controller, the user should use the command line parameter or sysfs to constrain all or partial idle states to ensure the CPU power domain is enabled and access coresight CPU debug component safely. Signed-off-by: Leo Yan <[email protected]> Reviewed-by: Suzuki K Poulose <[email protected]> Signed-off-by: Mathieu Poirier <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09coresight: refactor with function of_coresight_get_cpuLeo Yan2-15/+31
This is refactor to add function of_coresight_get_cpu(), so it's used to retrieve CPU id for coresight component. Finally can use it as a common function for multiple places. Suggested-by: Mathieu Poirier <[email protected]> Signed-off-by: Leo Yan <[email protected]> Signed-off-by: Mathieu Poirier <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09coresight: of_get_coresight_platform_data: Add missing of_node_putSuzuki K Poulose1-7/+10
The of_get_coresight_platform_data iterates over the possible CPU nodes to find a given cpu phandle. However it does not drop the reference to the node pointer returned by the of_get_coresight_platform_data. This patch also introduces another minor fix is to use of_cpu_device_node_get() to replace of_get_cpu_node(). Cc: Mathieu Poirier <[email protected]> Signed-off-by: Suzuki K Poulose <[email protected]> [Leo: minor tweaks for of_get_coresight_platform_data] Signed-off-by: Leo Yan <[email protected]> Signed-off-by: Mathieu Poirier <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09MAINTAINERS: update file entries for Coresight subsystemLeo Yan1-0/+2
Update document file entries for Coresight debug module. Signed-off-by: Leo Yan <[email protected]> Signed-off-by: Mathieu Poirier <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09doc: Add coresight_cpu_debug.enable to kernel-parameters.txtLeo Yan1-0/+7
Add coresight_cpu_debug.enable to kernel-parameters.txt, this flag is used to enable/disable the CPU sampling based debugging. Signed-off-by: Leo Yan <[email protected]> Signed-off-by: Mathieu Poirier <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09doc: Add documentation for Coresight CPU debugLeo Yan1-0/+175
Add detailed documentation for Coresight CPU debug driver, which contains the info for driver implementation, Mike Leach excellent summary for "clock and power domain". At the end some examples on how to enable the debugging functionality are provided. Suggested-by: Mike Leach <[email protected]> Signed-off-by: Leo Yan <[email protected]> Signed-off-by: Mathieu Poirier <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09coresight: bindings for CPU debug moduleLeo Yan1-0/+49
According to ARMv8 architecture reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate debug module and it can support self-hosted debug and external debug. Especially for supporting self-hosted debug, this means the program can access the debug module from mmio region; and usually the mmio region is integrated with coresight. So add document for binding debug component, includes binding to APB clock; and also need specify the CPU node which the debug module is dedicated to specific CPU. Suggested-by: Mike Leach <[email protected]> Signed-off-by: Leo Yan <[email protected]> Reviewed-by: Suzuki K Poulose <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Mathieu Poirier <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09coresight: tmc: Configure DMA mask appropriatelyRobin Murphy1-0/+7
Before making any DMA API calls, the ETR driver should really be setting its masks to ensure that DMA is possible. Especially since it can address more than the 32-bit default mask set by the AMBA bus code. Signed-off-by: Robin Murphy <[email protected]> Tested-by: Suzuki K Poulose <[email protected]> Signed-off-by: Mathieu Poirier <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2017-06-09coresight: etb10: Fix a typo in a comment lineMarkus Elfring1-1/+1
Delete a character in this description for a condition check. Signed-off-by: Markus Elfring <[email protected]> Signed-off-by: Mathieu Poirier <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
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