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2021-06-07drm/amdkfd: pages_addr offset must be 0 for system rangePhilip Yang1-1/+1
prange->offset is for VRAM range mm_nodes, if multiple ranges share same mm_nodes, migrate range back to VRAM will reuse the VRAM at offset of the same mm_nodes. For system memory pages_addr array, the offset is always 0, otherwise, update GPU mapping will use incorrect system memory page, and cause system memory corruption. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-07drm/amdgpu: Modify register access in sdma_v5_2 to use _SOC15 macrosRohit Khaire1-35/+35
In SRIOV environment, KMD should access SDMA registers through RLCG if GC indirect access flag enabled. Using _SOC15 read/write macros ensures that they go through RLC when the flag is enabled. Signed-off-by: Rohit Khaire <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu/dc: fix DCN3.1 FP handlingAlex Deucher1-1/+17
Missing proper DC_FP_START/DC_FP_END. Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu/dc: fix DCN3.1 Makefile for PPC64Alex Deucher1-1/+8
Port the necessary changes from previous DCN versions. Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: Add DC support and display block for Yellow CarpNicholas Kazlauskas2-1/+7
To enable output on real display instead of virtual. Acked-by: Huang Rui <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/display: Add DC DCN3.1 support to KconfigNicholas Kazlauskas1-0/+7
To enable compiling and using DCN3.1 ASICs with physical output. Acked-by: Huang Rui <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/display: Add DCN3.1 Yellow Carp support to DMNicholas Kazlauskas1-0/+44
To detect DCN3.1 ASICs and to enable the appropriate number of CRTCs, pick the right validation paths for display formats and to use the right DC interfaces. Acked-by: Huang Rui <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/display: Add DCN3.1 blocks to the DC MakefileNicholas Kazlauskas2-0/+38
Preparation for compiling DCN3.1 support. Acked-by: Huang Rui <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/display: Add DCN3.1 ResourceNicholas Kazlauskas4-0/+2245
Container for hardware resources and blocks for DCN3.1, also adds new DC debug flags used with DCN3.1. Acked-by: Huang Rui <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/display: Add z10 restore checks for DC interfacesNicholas Kazlauskas4-0/+30
DMCUB has a deferred z10 restore process that needs signalling from driver to occur. This needs to be done on any interface that programs the hardware state or sequences where we expect to have the same hardware state as before. Acked-by: Huang Rui <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/display: Add DCN3.1 HWSEQNicholas Kazlauskas8-2/+888
Add DCN3.1 specific hardware sequence programming - extending off of our existing DCN3/DCN2 support. Extend stream hardware sequencing to include new DCCG programming. Acked-by: Huang Rui <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/display: Add DCN3.1 BIOS parser supportNicholas Kazlauskas2-0/+118
Updated interfaces for multiple eDP backlight caps. Added support for interpreting the new BIOS command tables on DCN3.1. Acked-by: Huang Rui <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/display: Add DCN3.1 HDCP supportNicholas Kazlauskas6-4/+214
New DTM interface is V3 and we need to extend our existing support to enable HDCP on DCN3.1. Version the helpers and fallback to the older versions on failure in the new interfaces. Acked-by: Huang Rui <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/display: Add DCN3.1 PANELNicholas Kazlauskas2-0/+197
The PANEL block handles embedded panel power and backlight programming. This programming and sequencing is now owned by DMCUB and driver will call into the interface for backlight status and programming. Acked-by: Huang Rui <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/display: Add DCN3.1 DMCUBNicholas Kazlauskas8-0/+780
DMCU-B (Display Micro-Controller Unit B) is a display microcontroller used for shared display functionality with BIOS and for advanced power saving display features. Extends the command header to include new DCN3.1 functionality. Adds new interfaces to DC dmub interface as well for z-state support. Acked-by: Huang Rui <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/display: Add DCN3.1 GPIO supportNicholas Kazlauskas2-0/+6
Extends off of DCN3. Acked-by: Huang Rui <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/display: Add DCN3.1 IRQ managerNicholas Kazlauskas3-0/+480
Add IRQ services for DCN3.1 to handle hardware generated interrupts. Acked-by: Huang Rui <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/display: Add DCN3.1 DML calculation supportNicholas Kazlauskas11-0/+9523
DML (Display mode library) is used for calculating watermarks, bandwidth and for validating display configurations. Acked-by: Huang Rui <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/display: Add DCN3.1 DCHHUBNicholas Kazlauskas12-0/+1561
Adds DCN3.1 DCHHUB programming and modifies DCN20/DCN30 shared hardware sequencer helpers to use these hooks. HW Blocks: +--------++------+ +----------+ |DCHUBBUB|| HUBP | <-- | MMHUBBUB | +--------++------+ +----------+ | ^ v | +--------+ +--------+ | DPP | <---------> | DWB | +--------+ +--------+ | ^ v | +--------+ | | MPC | | +--------+ | | | v | +-------+ | | OPP | | +-------+ | | | v | +--------+ / | OPTC | -------------- +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ No changes to MMHUBBUB or DWB programming, added to diagram for clarity. Acked-by: Huang Rui <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/display: Add DCN3.1 OPTCNicholas Kazlauskas5-0/+563
Add support for programming the DCN3.1 OPTC (Output Timing Controller) HW Blocks: +--------+ | MPC | +--------+ | v +-------+ | OPP | +-------+ | v +--------+ | OPTC | +--------+ | v +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ There are no changes to OPP or MPC for DCN3.1, so the diagram will include them in this patch. Acked-by: Huang Rui <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/display: Add DCN3.1 DIONicholas Kazlauskas6-0/+710
Add support for the DIO (Display IO) block of DCN3.1 which controls legacy HDMI/DP stream/link encoding. HW Blocks: +--------+ +--------+ | DIO | | DCCG | +--------+ +--------+ Includes some updates to core logic for link encoder assignment and future support for new high bandwidth output. v2: squash in unused variable fix (Alex) Acked-by: Huang Rui <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/display: Add DCN3.1 DCCGNicholas Kazlauskas4-0/+536
Add programming of the DCCG (Display Controller Clock Generator) block: HW Blocks: +--------+ | DCCG | +--------+ Acked-by: Huang Rui <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/display: Add DCN3.1 clock manager supportNicholas Kazlauskas11-0/+1454
Adds support for clock requests for the various parts of the DCN3.1 IP and the interfaces and definitions for sending messages to SMU/PMFW. Includes new support for z9/10, detecting SMU timeout and p-state support enablement. Acked-by: Huang Rui <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/display: Add DCN3.1 yellow carp asic family IDsNicholas Kazlauskas2-0/+16
[Why & How] To determine whether the chip is yellow carp or not and which revision it is. Acked-by: Huang Rui <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: Update atomfirmware for DCN3.1 phy tuning and eDP capsNicholas Kazlauskas1-1/+55
[Why & How] We'll need these in driver for phy tuning in DCN3.1. Multiple eDP support also requires understanding which LCD the backlight curve in atombios is for. Acked-by: Huang Rui <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: add video_codecs query support for yellow carpJames Zhu1-0/+1
Add video_codecs query support for yellow carp. Acked-by: Huang Rui <[email protected]> Signed-off-by: James Zhu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/pm: disable manually setting MCLK power level on yellow carpXiaomeng Hou1-12/+10
PMFW provides specific messages for setting fclk freq range thus adjust the power level. There's misusing of these messages when setting dpm mclk. Since actually mclk could adjust automatically complying with fclk, remove standalone support for mclk dpm level setting. Acked-by: Huang Rui <[email protected]> Signed-off-by: Xiaomeng Hou <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: add mode2 reset support for yellow carpAaron Liu2-0/+27
This patch adds mode2 reset support for yellow carp. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/pm: add set_performance_level function for yellow carpXiaomeng Hou1-0/+84
This patch enables editing sysfs file power_dpm_force_performance_level for yellow carp. User could thus adjust the dpm forced level. v2: enable fine grain control of GFXCLK only when in manual performance level mode. In other mode, the min/max range of GFXCLK will be reset to corresponding values. Ex: To enable min 300MHz / max 600MHz gfx clocks 1) echo manual > /sys/bus/pci/devices/.../power_dpm_force_performance_level 2) echo s 0 300 > /sys/bus/pci/devices/.../pp_od_clk_voltage 3) echo s 1 600 > /sys/bus/pci/devices/.../pp_od_clk_voltage 4) echo c > /sys/bus/pci/devices/.../pp_od_clk_voltage Signed-off-by: Xiaomeng Hou <[email protected]> Acked-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: correct the cu and rb info for yellow carpXiaomeng Hou1-2/+4
Skip disabled sa to correct the cu_info and active_rbs for yellow carp. Signed-off-by: Xiaomeng Hou <[email protected]> Suggested-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: add gpu harvest support for yellow carp (v2)Xiaomeng Hou3-0/+48
Register callback in gfxhub functions to program the bypass groups in gc_utcl2 corresponding to harvested SA. v2: update comments (Alex) Signed-off-by: Xiaomeng Hou <[email protected]> Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/pm: add the interface to dump smu metrics table for yellow carpXiaomeng Hou1-1/+55
This patch is to add the interface to dump smu metrics table for yellow carp. Signed-off-by: Xiaomeng Hou <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/pm: add callbacks to read/write sysfs file pp_power_profile_modeXiaomeng Hou1-0/+86
Implement the sysfs API for getting/setting pp_power_profile_mode for yellow carp. Signed-off-by: Xiaomeng Hou <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/pm: add callback get_dpm_ultimate_freq for yellow carpXiaomeng Hou1-0/+111
Add callback function to get the hard frequency range of a clock domain for yellow carp. Signed-off-by: Xiaomeng Hou <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/pm: add callback to get bootup values for yellow carpXiaomeng Hou3-0/+139
Add get_vbios_bootup_values function to get the bootup values for yellow carp. Signed-off-by: Xiaomeng Hou <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: Load TA firmware for yellow carpNicholas Kazlauskas1-0/+4
Add TA firmware to module firmware list for yellow carp and call psp_init_ta_microcode to parse the TA firmware for HDCP support. Cc: Aaron Liu <[email protected]> Acked-by: Huang Rui <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/pm: add PrepareMp1ForUnload support for yellow carpAaron Liu1-0/+4
Driver needs to notify the PMFW when the RLC is disabled. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/pm: add callback force_clk_levels for yellow carpXiaomeng Hou1-0/+114
Implement the sysfs API to set a range of allowed DPM levels for specific clock domain. v2: return error directly if the specified clock type not supported Acked-by: Huang Rui <[email protected]> Signed-off-by: Xiaomeng Hou <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/pm: initialize feature_enabled/feature_support bitmap for yellow carpXiaomeng Hou1-0/+25
Initialize the feature_enabled and feature_supported bitmap for yellow carp. Acked-by: Huang Rui <[email protected]> Signed-off-by: Xiaomeng Hou <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/pm: implement is_dpm_running() callback for yellow carpXiaomeng Hou1-9/+21
Implement function to check if DPM is running for yellow carp. Acked-by: Huang Rui <[email protected]> Signed-off-by: Xiaomeng Hou <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/pm: add feature map for yellow carpXiaomeng Hou1-0/+42
Add feature map for yellow carp. Acked-by: Huang Rui <[email protected]> Signed-off-by: Xiaomeng Hou <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/pm: add support to get dpm clock value for yellow carpXiaomeng Hou1-1/+127
Implement the sysfs API for getting values of pp dpm clocks(pp_dpm_socclk/mclk/fclk/vclk/dclk) for yellow carp. Signed-off-by: Xiaomeng Hou <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/pm: add the fine grain tuning function for yellow carpXiaomeng Hou1-0/+116
Use the pp_od_clk_voltage sysfs file to configure the min and max value of gfx clock frequency or to restore the default values. Command guide: echo "s level value" > pp_od_clk_voltage "s" - set the sclk frequency "level" - 0 or 1, "0" represents the min value, "1" represents the max value "value" - the target value of sclk frequency, it should be limited in the safe range echo "r" > pp_od_clk_voltage "r" - reset the sclk frequency, restore the default value echo "c" > pp_od_clk_voltage "c" - commit the min and max value of sclk frequency to the system only after the commit command, the setting target values by "s" command will take effect Example: 1) check the default sclk frequency $ cat pp_od_clk_voltage OD_SCLK: 0: 200Mhz 1: 600Mhz OD_RANGE: SCLK: 200MHz 600MHz 2) use "s" -- set command to configure the min or max sclk frequency $ echo "s 0 300" > pp_od_clk_voltage $ echo "s 1 500" > pp_od_clk_voltage $ echo "c" > pp_od_clk_voltage $ cat pp_od_clk_voltage OD_SCLK: 0: 300Mhz 1: 500Mhz OD_RANGE: SCLK: 200MHz 600MHz 3) use "r" -- reset command to restore the min and max sclk frequency $ echo "r" > pp_od_clk_voltage $ echo "c" > pp_od_clk_voltage $ cat pp_od_clk_voltage OD_SCLK: 0: 200Mhz 1: 600Mhz OD_RANGE: SCLK: 200MHz 600MHz v2: modify the description of reset command usage - need to do "commit" after set the restore command Signed-off-by: Xiaomeng Hou <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/pm: add set_watermarks_table function for yellow carpXiaomeng Hou1-0/+61
Add callback function set_watermarks_table for yellow carp. Acked-by: Huang Rui <[email protected]> Signed-off-by: Xiaomeng Hou <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/pm: add read_sensor function for yellow carpXiaomeng Hou1-0/+140
Add callback function read_sensor for yellow carp. Acked-by: Huang Rui <[email protected]> Signed-off-by: Xiaomeng Hou <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: add timestamp counter query support for yellow carpAaron Liu1-0/+1
Allows software to query HW counters to timestamp submissions. This patch can address KFDPerfCountersTest. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Reviewed-by: chen gong <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: add RLC_PG_DELAY_3 for yellow carpAaron Liu1-5/+16
RLC_PG_DELAY_3 is to make RLC in safe mode to prevent any misalignment or conflict in middle of any power feature entry/exit sequence when CGPG feature is enabled. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu/pm: support smu_post_init for yellow carpAaron Liu1-3/+3
Add smu_post_init support for yellow carp. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: enable VCN PG and CG for yellow carpAaron Liu1-2/+6
Enable VCN 3.0 PG and CG for Yellow Carp by setting up flags. Acked-by: Huang Rui <[email protected]> Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: enable vcn dpg mode on yellow carpJames Zhu1-1/+2
Enable vcn dpg mode on yellow carp. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Reviewed-by: Aaron Liu <[email protected]> Acked-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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