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2013-04-18drm/i915: add intel_using_power_wellPaulo Zanoni3-2/+19
It returns true if we've requested to turn the power well on and it's really on. It also returns true for all the previous gens. For now there's just one caller, but I'm going to add more. Signed-off-by: Paulo Zanoni <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/i915: don't check inconsistent modeset state when force-restoringDaniel Vetter1-6/+24
It will be only consistent once we've restored all the crtcs. Since a bunch of other callers also want to just restore a single crtc, add a boolean to disable checking only where it doesn't make sense. Note that intel_modeset_setup_hw_state already has a call to intel_modeset_check_state at the end, so we don't reduce the amount of checking. v2: Try harder not to create a big patch (Chris). v3: Even smaller (still Chris). Also fix a trailing space. References: https://lkml.org/lkml/2013/3/16/60 Cc: Tomas Melin <[email protected]> Cc: Richard Cochran <[email protected]> Cc: Chris Wilson <[email protected]> Cc: [email protected] Reviewed-by: Chris Wilson <[email protected]> Tested-by: Tomas Melin <[email protected]> Tested-by: Richard Cochran <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/i915: IVB/HSW have 32 fence registerVille Syrjälä3-5/+7
Increase the number of fence registers to 32 on IVB/HSW. VLV however only has 16 fence registers according to the docs. Increasing the number of fences was attempted before [1], but there was some uncertainty about the maximum CPU fence number for FBC. Since then BSpec has been updated to state that there are in fact 32 fence registers, and the CPU fence number field in the SNB_DPFC_CTL_SA register is 5 bits, and the CPU fence number field in the ILK_DPFC_CONTROL register must be zero. So now it all makes sense. [1] http://lists.freedesktop.org/archives/intel-gfx/2011-October/012865.html v2: Include some background information based on the previous attempt Signed-off-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/i915: Return stored value from max freq sysfs entryMika Kuoppala1-1/+1
commit 4f9b2fe0441d4bdf5666a306156b5d6755de2584 Author: Ben Widawsky <[email protected]> Date: Fri Apr 5 14:29:22 2013 -0700 drm/i915: Better overclock support changed the sysfs read semantics for 'gt_max_freq_mhz'. By always returning overclock max instead of stored value. Fix this by returning the stored value. Separate sysfs entry should be considered for overclocking max freq. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=63415 Cc: Ben Widawsky <[email protected]> Signed-off-by: Mika Kuoppala <[email protected]> Reviewed-by: Ben Widawsky <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/i915: Remove stale codeBen Widawsky1-3/+0
Looks like a some remnant from a rebase. Signed-off-by: Ben Widawsky <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/i915: Increase max fence pitch limit to 256KB on IVB+Ville Syrjälä2-3/+7
BSpec contains several scattered notes which state that the maximum fence stride was increased to 256KB on IVB. Testing on real hardware agrees. Signed-off-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/i915: Reject fence stride=0 on gen4+Ville Syrjälä1-3/+3
Our checks for an invalid fence stride forgot to guard against zero stride on gen4+. Fix it. v2: Avoid duplicated code (danvet) Signed-off-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/i915: Configure GAM_ECOCHK appropriatly for Gen7Ville Syrjälä2-2/+14
IVB and HSW use different encodings for the PPGTT cacheability bits in the GAM_ECOCHK register. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Imre Deak <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/i915: Set GAC_ECO_BITS register on Gen7+Ville Syrjälä1-0/+5
According to BSpec GAC_ECO_BITS register exists on Gen7 platforms as well. Configure it accordingly. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Imre Deak <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/i915: Add ECOBITS_SNB_BITVille Syrjälä2-1/+3
GAC_ECO_BITS has a bit similar to GAM_ECOCHK's ECOCHK_SNB_BIT. Add the define, and enable it on SNB. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Imre Deak <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/i915: Don't default to overclock maxBen Widawsky1-2/+1
Requested-by: Daniel Vetter <[email protected]> Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/i915: Better overclock supportBen Widawsky4-6/+16
Most importantly this will allow users to set overclock frequencies in sysfs. Previously the max was limited by the RP0 max as opposed to the overclock max. This is useful if one wants to either limit the max overclock frequency, or set the minimum frequency to be in the overclock range. It also fixes an issue where if one sets the max frequency to be below the overclock max, they wouldn't be able to set back the proper overclock max. In addition I've added a couple of other bits: Show the overclock freq. as max in sysfs Print the overclock max in debugfs. Print a warning if the user sets the min frequency to be in the overclock range. In this patch I've decided to store the hw_max when we read it from the pcode at init. The reason I do this is the pcode reads can fail, and are slow. v2: Report when user requested overclocked max (Daniel) Remove when user sets min to overclock range (Daniel) Reported-by: freezer from #intel-gfx on irc Signed-off-by: Ben Widawsky <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> [danvet: Fixup the s/100MHz/50MHz/ confusion in an unrelated comment that Mika spotted.] Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/i915: use lower aux clock divider on non-ULT HSWJani Nikula1-2/+6
Workaround to avoid intermittent aux channel failures, per spec change. v2: Don't mess with cpu dp aux divider (Paulo Zanoni) Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Paulo Zanoni <[email protected]> [danvet: Kill spurious tab spotted by Paulo.] Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/i915: Allow PPGTT enable to failBen Widawsky4-6/+15
I'm really not happy that we have to support this, but this will be the simplest way to handle cases where PPGTT init can fail, which I promise will be coming in the future. v2: Resolve conflicts due to patch series reordering. Signed-off-by: Ben Widawsky <[email protected]> (v1) Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/i915: NULL aliasing_ppgtt on cleanupBen Widawsky1-0/+1
This will allow us to carry on if we've cleaned up the PPGTT. The usage for this is coming up - it simplifies handling a failed PPGTT init. Signed-off-by: Ben Widawsky <[email protected]> [danvet: Spill the secrets about failing ppgtt init.] Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/i915: Abstract PPGTT enablingBen Widawsky4-61/+61
Since we've already set up a nice vtable to abstract other PPGTT functions, also abstract the actual register programming to enable things. This function will probably need to change a bit as we implement real processes. v2: Resolve conflicts due to patch series reordering. Signed-off-by: Ben Widawsky <[email protected]> (v1) Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/i915: Rework PPGTT init codeBen Widawsky1-1/+5
This rework will help if future platforms choose to be a bit different. Should have no functional impact. v2: Don't move around the vtable setup (Daniel) v3: Squash in the disable-by-default patch. Signed-off-by: Ben Widawsky <[email protected]> (v1) Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/i915: Conditionally carve out GGTT PDEBen Widawsky1-3/+6
It only works that way on GEN6 and GEN7. Let's not assume GENn will be the same. Signed-off-by: Ben Widawsky <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/i915/ppgtt: Set scratch page "globally"Ben Widawsky1-2/+1
The PPGTT scratch page is used for all gens, and doing it in the global part of our PPGTT setup makes the code a bit nicer. This was in a patch submitted earlier as part of the PPGTT cleanups. Grumpy maintainer must have missed it, and I didn't yell when appropriate. Apologies for everyone :-) v2: Update commit message Signed-off-by: Ben Widawsky <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/i915: random checkpatch fixesBen Widawsky1-3/+2
There used to be other fixes in this patch but they've slowly disappeared as other parts have been fixed. Signed-off-by: Ben Widawsky <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/i915: Map registers before GTT initBen Widawsky1-24/+23
This will allow us to read/write registers in GTT init. Signed-off-by: Ben Widawsky <[email protected]> [danvet: Fix up error handling. We really should look into devres for this stuff ...] Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/i915: Call out GEN6 PTE specificityBen Widawsky1-16/+15
We can assume that the PTE layout, and size changes for future generations. To avoid confusion with the existing GEN6 PTE typedef, give it a GEN6_ prefix. v2: Fixup checkpatch warning and bikeshed commit message slightly. v3: Rebase on top of Imre's for_each_sg_pages rework. v4: Fixup conflicts in patch series reordering. Signed-off-by: Ben Widawsky <[email protected]> (v1) Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/i915: generalize pte vs. register BAR allocationBen Widawsky1-2/+4
All gen6+ parts so far have 1 BAR which holds both the register space and the GTT PTEs. Up until now, that was a 4MB BAR with half allocated to each. I have a strong hunch (wink, nod, wink) that future gens will also keep a similar 50-50 split though the sizes may change. To help this along change the code to obey the rule of half the total size instead of a hard-coded 2MB. Signed-off-by: Ben Widawsky <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/i915: Use MLC (l3$) for context objectsChris Wilson1-0/+7
Enabling context support increases SwapBuffers latency by about 20% (measured on an i7-3720qm). We can offset that loss slightly by enabling faster caching for the contexts. As they are not backed by any particular cache (such as the sampler or render caches) our only option is to select the generic mid-level cache. This reduces the latency of the swap by about 5%. Oddly this effect can be observed running smokin-guns on IVB at 1280x1024: Using BLT copies for swaps: 151.67 fps Using Render copies for swaps (unpatched): 141.70 fps With contexts disabled: 150.23 fps With contexts in L3$: 150.77 fps Signed-off-by: Chris Wilson <[email protected]> Cc: Ben Widawsky <[email protected]> Cc: Kenneth Graunke <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/i915: update FDI mPHY setup codeDaniel Vetter1-7/+0
Bspec has been been updated and dropped these two changes for non-sdv LPT PCHs. Cc: Paulo Zanoni <[email protected]> Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/i915: Workaround incoherence between fences and LLC across multiple CPUsChris Wilson1-5/+23
In order to fully serialize access to the fenced region and the update to the fence register we need to take extreme measures on SNB+, and manually flush writes to memory prior to writing the fence register in conjunction with the memory barriers placed around the register write. Fixes i-g-t/gem_fence_thrash v2: Bring a bigger gun v3: Switch the bigger gun for heavier bullets (Arjan van de Ven) v4: Remove changes for working generations. v5: Reduce to a per-cpu wbinvd() call prior to updating the fences. v6: Rewrite comments to ellide forgotten history. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=62191 Signed-off-by: Chris Wilson <[email protected]> Cc: Jon Bloomfield <[email protected]> Tested-by: Jon Bloomfield <[email protected]> (v2) Cc: [email protected] Reviewed-by: Jesse Barnes <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/i915: tune down Y tiling scanout warningDaniel Vetter1-2/+4
Userspace can easily hit this and does since Ville added a new evil igt testcase in: commit 069e35e0fc3785faa562adcfd2dd7bbed4cb1dea Author: Ville Syrjälä <[email protected]> Date: Mon Mar 4 15:34:06 2013 +0200 kms_flip: Add flip-vs-bad-tiling test v2: Fix the spelling in the added comment (Chris). Cc: Ville Syrjälä <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=63246 Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/i915: set CB tuning also for the reduce clockDaniel Vetter1-2/+7
Since the ratio is different, we also need to pass in the parameters for the reduced clock. Might or might not reduce flicker for the auto-downclocking on lvds/eDP. Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/i915: fix FP CB tuning limits for lvdsDaniel Vetter1-1/+1
Only on IBX should we set the limiting factor to 25 unconditionally for dual-channel mode, on CPT/PPT 25 only applies when the lvds refclock is 100MHz. Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/i915: fix lost FP_CB_TUNE setting for pch pllsDaniel Vetter1-3/+3
commit de13a2e3f88a4da8e85063b6de37096795079e41 Author: Paulo Zanoni <[email protected]> Date: Thu Sep 20 18:36:05 2012 -0300 drm/i915: extract compute_dpll from ironlake_crtc_mode_set missed the subtle adjustment of the FP1 register. Fix this up by passing a pointer around instead of the value. Cc: Paulo Zanoni <[email protected]> Cc: Rodrigo Vivi <[email protected]> Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/i915: Fix SDVO connector and encoder get_hw_state functionsEgbert Eich1-6/+3
The connector associated with the encoder is considered active when the output associtated with this connector is active on the encoder. The encoder itself is considered active when either there is an active output on it or the respective SDVO channel is active. Having active outputs when the SDVO channel is inactive seems to be inconsistent: such states can be found when intel_modeset_setup_hw_state() collects the hardware state set by the BIOS. This inconsistency will be fixed in intel_sanitize_crtc() (when intel_crtc_update_dpms() is called), this however only happens when the encoder is associated with a crtc. This patch also reverts: commit bd6946e87a98fea11907b2a47368e13044458a35 Author: Daniel Vetter <[email protected]> Date: Tue Apr 2 21:30:34 2013 +0200 drm/i915: Fix sdvo connector get_hw_state function Signed-off-by: Egbert Eich <[email protected]> Suggested-by: Daniel Vetter <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=63031 Cc: [email protected] Signed-off-by: Daniel Vetter <[email protected]>
2013-04-18drm/qxl: fix build with debugfs turned off.Dave Airlie1-0/+4
Reported-by: Randy Dunlap Signed-off-by: Dave Airlie <[email protected]>
2013-04-17Merge branch 'gma500-next' of git://github.com/patjak/drm-gma500 into drm-nextDave Airlie19-162/+154
Patrik writes: I haven't had much review or testing on other platforms than Poulsbo but at least the following Cedarview bug has been squashed and no regressions reported: https://bugs.freedesktop.org/show_bug.cgi?id=58527 * 'gma500-next' of git://github.com/patjak/drm-gma500: drm/gma500: Add debugging info to psb_gtt_restore() drm/gma500: Check connector status before restoring sdvo gma500:fix build failure for 3.9-rc5 drm/gma500: Fix hibernation problems on sdvo encoders drm/gma500: Add hooks for hibernation drm/gma500: Activate the gtt rebuild on suspend/resume drm/gma500: Add support for rebuilding the gtt drm/gma500: Change fb name so pm-utils doesn't apply quirks gma500: Make VGA and HDMI connector hotpluggable drm/gma500: Clean up various defines drm/gma500: Remove unnecessary function exposure drm/gma500: Type clock limits directly into array and remove defines drm/gma500: Calculate clock in one function instead of three identical drm/gma500: Remove unused i8xx clock limits gma500: medfield: Fix possible NULL pointer dereference drivers: gpu: drm: gma500: Replaced calls kzalloc & memcpy with kmemdup gma500: remove unused drm_psb_no_fb
2013-04-17Merge branch 'drm-next-3.10' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie32-332/+2737
into drm-next Alex writes: This is the initial 3.10 pull request for radeon. The big changes here are UVD support and proper tiling support for SI. The rest is bug fixes. I hope to have another pull request later in the week with some new things we've been working on internally. * 'drm-next-3.10' of git://people.freedesktop.org/~agd5f/linux: (28 commits) drm/radeon: Always flush the VM drm/radeon: re-enable PTE/PDE packet for set_page on cayman/TN drm/radeon: cleanup properly if mmio mapping fails drm/radeon/evergreen+: don't enable HPD interrupts on eDP/LVDS drm/radeon: add si tile mode array query v3 drm/radeon: add ring working query drm/radeon: handle broken disabled rb mask gracefully drm/radeon: add pcie set/get lanes callbacks for newer asics drm/radeon: update r600 set/get pcie lane config drm/radeon/kms: replace *REG32_PCIE_P with *REG32_PCIE_PORT drm/radeon: remove unused blit remnants from si.c drm/radeon: add UVD tiling addr config v2 drm/radeon: init UVD clocks to sane defaults drm/radeon: add set_uvd_clocks callback for r7xx v3 drm/radeon: add set_uvd_clocks callback for SI drm/radeon: add set_uvd_clocks callback for evergreen drm/radeon: add set_uvd_clocks callback for ON/LN/TN (v4) drm/radeon: add radeon_atom_get_clock_dividers helper drm/radeon: add pm callback for setting uvd clocks drm/radeon: UVD bringup v8 ...
2013-04-16drm/radeon: Always flush the VMJerome Glisse1-1/+2
This is slightly cleaned up version of Jerome's patch. There seems to be an issue tracking the last flush of the VM which results in hangs in certain cases when VM is used. For now just flush the VM for every IB. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=62959 https://bugs.freedesktop.org/show_bug.cgi?id=62997 Signed-off-by: Jerome Glisse <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2013-04-16drm/radeon: re-enable PTE/PDE packet for set_page on cayman/TNAlex Deucher2-18/+52
PTE/PDE doesn't support a single update (count = 1). We had previously disabled it since it we were hitting that case which let to hangs. The PTE/PDE packet is much more efficient for VM updates where it can be used. Signed-off-by: Alex Deucher <[email protected]>
2013-04-17Revert "of/exynos_g2d: Add Bindings for exynos G2D driver"Sachin Kamat1-22/+0
This reverts commit 09495dda6a62c74b13412a63528093910ef80edd. The description is incomplete and the location of this file is incorrect. Based on discussion with the Samsung media and DRM subsystem maintainers, the documentaion of Samsung G2D bindings has been placed at: Documentation/devicetree/bindings/gpu/samsung-g2d.txt Signed-off-by: Sachin Kamat <[email protected]> Signed-off-by: Inki Dae <[email protected]>
2013-04-17drm/exynos: drm_connector: Fix error check conditionSachin Kamat1-1/+1
drm_add_edid_modes() returns 0 upon failure to find any modes. Hence check for 0 and not less than 0. Signed-off-by: Sachin Kamat <[email protected]> Signed-off-by: Inki Dae <[email protected]>
2013-04-17drm/exynos: drm_rotator: Fix incorrect usage of IS_ERR_OR_NULLSachin Kamat1-1/+1
Use IS_ERR instead of IS_ERR_OR_NULL on clk_get results. Signed-off-by: Sachin Kamat <[email protected]> Signed-off-by: Inki Dae <[email protected]>
2013-04-17drm/exynos: mixer: Fix incorrect usage of IS_ERR_OR_NULLSachin Kamat1-5/+5
Use IS_ERR instead of IS_ERR_OR_NULL on clk_get results. Signed-off-by: Sachin Kamat <[email protected]> Signed-off-by: Inki Dae <[email protected]>
2013-04-17drm/exynos: hdmi: Fix incorrect usage of IS_ERR_OR_NULLSachin Kamat1-5/+5
Use IS_ERR instead of IS_ERR_OR_NULL on clk_get results. Signed-off-by: Sachin Kamat <[email protected]> Signed-off-by: Inki Dae <[email protected]>
2013-04-17drm/exynos: change the method for getting the interruptVikas Sajjan1-1/+1
Replaces the "platform_get_resource() for IORESOURCE_IRQ" with platform_get_resource_byname(). Both in exynos4 and exynos5, FIMD IP has 3 interrupts in the order: "fifo", "vsync", and "lcd_sys". But The FIMD driver expects the "vsync" interrupt to be mentioned as the 1st parameter in the FIMD DT node. So to meet this expectation of the driver, the FIMD DT node was forced to be made by keeping "vsync" as the 1st paramter. For example in exynos4, the FIMD DT node has interrupt numbers mentioned as <11, 1> <11, 0> <11, 2> keeping "vsync" as the 1st paramter. This patch fixes the above mentioned "hack" of re-ordering of the FIMD interrupt numbers by getting interrupt resource of FIMD by using platform_get_resource_byname(). Signed-off-by: Vikas Sajjan <[email protected]> Signed-off-by: Inki Dae <[email protected]>
2013-04-17drm/exynos: enable OF_VIDEOMODE and FB_MODE_HELPERS for exynos drm fimdVikas Sajjan1-1/+3
patch adds "select OF_VIDEOMODE" and "select FB_MODE_HELPERS" when EXYNOS_DRM_FIMD config is selected. Also adds the "OF" dependency. Signed-off-by: Vikas Sajjan <[email protected]> Signed-off-by: Inki Dae <[email protected]>
2013-04-17drm/exynos: Add display-timing node parsing using video helper functionVikas Sajjan1-4/+20
Add support for parsing the display-timing node using video helper function. The DT node parsing is done only if 'dev.of_node' exists and the NON-DT logic is still maintained under the 'else' part. Signed-off-by: Leela Krishna Amudala <[email protected]> Signed-off-by: Vikas Sajjan <[email protected]> Acked-by: Joonyoung Shim <[email protected]> Signed-off-by: Inki Dae <[email protected]>
2013-04-17drm/exynos: hdmi: move mode_fixup to drm common hdmiRahul Sharma3-54/+36
Currently, mode_fixup code doesn't consider the limitations of mixer as it is implemented inside the hdmi driver. Following fix, moves the mode_fixup to common drm hdmi driver. To check the mode support, it calls both, mixer and hdmi check_timing callbacks for a given resolution mode. This patch is dependent on https://patchwork.kernel.org/patch/2176021/. Signed-off-by: Rahul Sharma <[email protected]> Signed-off-by: Inki Dae <[email protected]>
2013-04-17drm/exynos: hdmi: using drm_display_mode timings for exynos4Rahul Sharma2-417/+246
Exynos5 is already using drm_display_mode for timings parameters. Exynos4 is also modifed to use the same. List of supported resolutions and corresponding timings are removed which helps is enabling some extra resolutions. It also cleans some of the duplicate code. Exynos4 and Exynos5 Mixers, work fine for the same range of resolutions. Hence same condition (to find the supported mode) is applied to both. More exynos4 phy configs can be added later to extend the mode supprot. Signed-off-by: Rahul Sharma <[email protected]> Signed-off-by: Inki Dae <[email protected]>
2013-04-16drm/qxl: fix smatch warningsDave Airlie3-4/+5
drivers/gpu/drm/qxl/qxl_display.c:99 qxl_alloc_client_monitors_config() error: dereferencing freed memory 'qdev->client_monitors_config' drivers/gpu/drm/qxl/qxl_object.c:66 qxl_ttm_placement_from_domain() warn: bitwise AND condition is false here drivers/gpu/drm/qxl/qxl_ioctl.c:353 qxl_clientcap_ioctl() warn: buffer overflow 'qdev->rom->client_capabilities' 58 <= 58 Reported-by: Dan Carpenter <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2013-04-16drm/qxl: make lots of things static.Dave Airlie9-77/+31
/usr/lib/gcc/x86_64-linux-gnu/4.7/include/stddef.h:414:9: sparse: preprocessor token offsetof redefined include/linux/stddef.h:17:9: this was the original definition >> drivers/gpu/drm/qxl/qxl_drv.c:49:5: sparse: symbol 'qxl_modeset' was not declared. Should it be static? Reported-by: kbuild test robot. Signed-off-by: Dave Airlie <[email protected]>
2013-04-16Merge tag 'omapdss-for-3.10' of git://gitorious.org/linux-omap-dss2/linux ↵Dave Airlie53-1739/+1972
into drm-next Omapdss patches for 3.10 merge window The biggest changes are: * DSI video mode: automatic clock and timing calculation * Lots of platform data related panel driver cleanups, to prepare for DT * tag 'omapdss-for-3.10' of git://gitorious.org/linux-omap-dss2/linux: (69 commits) drm/omap: add statics to a few structs drm/omap: Fix and improve crtc and overlay manager correlation drm/omap: Take a fb reference in omap_plane_update() drm/omap: Make fixed resolution panels work drm/omap: fix modeset_init if a panel doesn't satisfy omapdrm requirements OMAPDSS: DPI: widen the pck search when using dss fck OMAPDSS: fix dss_fck clock rate rounding omapdss: use devm_clk_get() OMAPDSS: nec-nl8048 panel: Use dev_pm_ops OMAPDSS: DISPC: Revert to older DISPC Smart Standby mechanism for OMAP5 OMAPDSS: DISPC: Configure doublestride for NV12 when using 2D Tiler buffers omapdss: Features: Fix some parameter ranges omapdss: DISPC: add max pixel clock limits for LCD and TV managers OMAPDSS: DSI: Use devm_clk_get() drivers: video: omap2: dss: Use PTR_RET function OMAPDSS: VENC: remove platform_enable/disable calls OMAPDSS: n8x0 panel: remove use of platform_enable/disable OMAPDSS: n8x0 panel: handle gpio data in panel driver OMAPDSS: picodlp panel: remove platform_enable/disable callbacks OMAPDSS: picodlp panel: handle gpio data in panel driver ...
2013-04-16drm: Perform ioctl command validation on the stored kernel valuesChris Wilson1-0/+1
Userspace is free to pass in any command bits it feels like through the ioctl cmd, and for example trinity likes to fuzz those bits to create conflicting commands. So instead of relying upon userspace to pass along the correct IN/OUT flags for the ioctl, use the flags as expected by the kernel. This does have a side-effect that NULL pointers can not be substituted by userspace in place of a struct. This feature was not being used by any driver, but instead exposed all of the command handlers to a user triggerable OOPS. Reported-by: Tommi Rantala <[email protected]> Link: http://lkml.kernel.org/r/CA+ydwtpuBvbwxbt-tdgPUvj1EU7itmCHo_2B3w13HkD5+jWKow@mail.gmail.com Signed-off-by: Tommi Rantala <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
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