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2019-01-08drm/amdgpu: validate user GEM object sizeYu Zhao1-0/+8
When creating frame buffer, userspace may request to attach to a previously allocated GEM object that is smaller than what GPU requires. Validation must be done to prevent out-of-bound DMA, otherwise it could be exploited to reveal sensitive data. This fix is not done in a common code path because individual driver might have different requirement. Cc: [email protected] # v4.2+ Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Yu Zhao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-08drm/amdgpu: validate user pitch alignmentYu Zhao1-0/+10
Userspace may request pitch alignment that is not supported by GPU. Some requests 32, but GPU ignores it and uses default 64 when cpp is 4. If GEM object is allocated based on the smaller alignment, GPU DMA will go out of bound. Cc: [email protected] # v4.2+ Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Yu Zhao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-08drm/amd/powerplay: drop the unnecessary uclk hard min settingEvan Quan1-7/+0
Since soft min setting is enough. Hard min setting is redundant. Reported-by: Likun Gao <[email protected]> Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-08drm/amd/powerplay: avoid possible buffer overflowEvan Quan1-0/+14
Make sure the clock level enforced is within the allowed ranges. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-08drm/amd/powerplay: create pp_od_clk_voltage device file under OD supportEvan Quan1-8/+14
Since pp_od_clk_voltage device file is for OD related sysfs operations. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-08drm/amd/powerplay: update OD support flag for SKU with no OD capabilitiesEvan Quan1-0/+3
For those ASICs with no overdrive capabilities, the OD support flag will be reset. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-03drm/amdgpu: make gfx9 enter into rlc safe mode when set MGCGLikun Gao1-0/+4
MGCG should RLC enter into safe mode first. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-03drm/amdgpu: Cleanup 2 compiler warningsKent Russell1-2/+0
These 2 variables are unused now, so remove their references. Fixes: e4ae0fc drm/amdgpu: implement gfx8 post_soft_reset Fixes: 5e01c09 drm/amdgpu/gfx_v8_0: Reorder the gfx, kiq and kcq rings test sequence Signed-off-by: Kent Russell <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-02drm/amdgpu/gfx_v8_0: Reorder the gfx, kiq and kcq rings test sequenceTiecheng Zhou1-13/+35
The kiq ring and the very first compute ring may fail occasionally if they are tested directly following kiq_kcq_enable. Insert the gfx ring test before kiq ring test to delay the kiq and kcq ring tests will fix the issue. Acked-by: Alex Deucher <[email protected]> Signed-off-by: Tiecheng Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-02drm/amdgpu/sriov:Correct pfvf exchange logicEmily Deng2-5/+5
The pfvf exchange need be in exclusive mode. And add pfvf exchange in gpu reset. Signed-off-by: Emily Deng <[email protected]> Reviewed-By: Xiangliang Yu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-02drm/amd/powerplay: support BOOTUP_DEFAULT power profile modeEvan Quan6-29/+40
This can avoid unexpected profile mode change after running compute workload. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-02drm/amdgpu/virtual_dce: No need to pin the cursor boEmily Deng1-2/+2
For virtual display feature, no need to pin cursor bo. Signed-off-by: Emily Deng <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-02drm/amdgpu/virtual_dce: No need to pin the fb's boEmily Deng2-22/+15
For virtual display, no need to pin the fb's bo. Signed-off-by: Emily Deng <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-31Merge branch 'drm-next-4.21' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie43-285/+582
into drm-next Fixes for 4.21. A bit more than usual due to the holidays. Highlights: - add new vegaM pci id - sr-iov fixes - DC fix for fast cursor updates - DC freesync fix - DC display clock fix for polaris - DC fixes for dongles - DC fix for some eDP panels - misc vega20 fixes - kfd return code fix for dma_buf support - VCN fixes for PCO - nbio hw bug workaround Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-12-28Merge tag 'drm-intel-next-fixes-2018-12-27' of ↵Dave Airlie6-5/+43
git://anongit.freedesktop.org/drm/drm-intel into drm-next GVT fixes for v4.21-rc1 Signed-off-by: Dave Airlie <[email protected]> From: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-12-21drm/amdgpu: Add new VegaM pci idAlex Deucher1-0/+1
Add a new pci id. Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2018-12-21drm/ttm: Use drm_debug_printer for all ttm_bo_mem_space_debug outputMichel Dänzer1-16/+17
No need for pr_err here, the pr_err message in ttm_bo_evict is enough to draw attention to something not going as planned. Reviewed-by: Christian König <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-21drm/amdgpu: add Vega20 PSP ASD firmware loadingEvan Quan1-9/+31
Add PSP ASD firmware loading on Vega20. Not sure why this was missing before. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2018-12-20drm/amd/display: Fix MST dp_blank REG_WAIT timeoutJerry (Fangzhi) Zuo1-2/+2
Need to blank stream before deallocate MST payload. [drm:generic_reg_wait [amdgpu]] *ERROR* REG_WAIT timeout 10us * 3000 tries - dce110_stream_encoder_dp_blank line:944 ------------[ cut here ]------------ WARNING: CPU: 0 PID: 2201 at /var/lib/dkms/amdgpu/18.50-690240/build/amd/amdgpu/../display/dc/dc_helper.c:249 generic_reg_wait+0xe7/0x160 [amdgpu] Call Trace: dce110_stream_encoder_dp_blank+0x11c/0x180 [amdgpu] core_link_disable_stream+0x40/0x230 [amdgpu] ? generic_reg_update_ex+0xdb/0x130 [amdgpu] dce110_reset_hw_ctx_wrap+0xb7/0x1f0 [amdgpu] dce110_apply_ctx_to_hw+0x30/0x430 [amdgpu] ? dce110_apply_ctx_for_surface+0x206/0x260 [amdgpu] dc_commit_state+0x2ba/0x4d0 [amdgpu] amdgpu_dm_atomic_commit_tail+0x297/0xd70 [amdgpu] ? amdgpu_bo_pin_restricted+0x58/0x260 [amdgpu] ? wait_for_completion_timeout+0x1f/0x120 ? wait_for_completion_interruptible+0x1c/0x160 commit_tail+0x3d/0x60 [drm_kms_helper] drm_atomic_helper_commit+0xf6/0x100 [drm_kms_helper] drm_atomic_connector_commit_dpms+0xe5/0xf0 [drm] drm_mode_obj_set_property_ioctl+0x14f/0x250 [drm] drm_mode_connector_property_set_ioctl+0x2e/0x40 [drm] drm_ioctl+0x1e0/0x430 [drm] ? drm_mode_connector_set_obj_prop+0x70/0x70 [drm] ? ep_read_events_proc+0xb0/0xb0 ? ep_scan_ready_list.constprop.18+0x1e6/0x1f0 ? timerqueue_add+0x52/0x80 amdgpu_drm_ioctl+0x49/0x80 [amdgpu] do_vfs_ioctl+0x90/0x5f0 SyS_ioctl+0x74/0x80 do_syscall_64+0x74/0x140 entry_SYSCALL_64_after_hwframe+0x3d/0xa2 ---[ end trace 3ed7b77a97d60f72 ]--- Signed-off-by: Jerry (Fangzhi) Zuo <[email protected]> Reviewed-by: Hersen Wu <[email protected]> Acked-by: Harry Wentland <[email protected]> Acked-by: Alex Deucher <[email protected]> Tested-by: Lyude Paul <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2018-12-20drm/amd/display: validate extended dongle capsWenjing Liu1-1/+2
[why] Some dongle doesn't have a valid extended dongle caps, but we still set the extended dongle caps to be valid. This causes validation fails for all timing. [how] If no dp_hdmi_max_pixel_clk is provided, don't use extended dongle caps. Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Abdoulaye Berthe <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-20drm/amd/display: Use div_u64 for flip timestamp ns to msNicholas Kazlauskas1-1/+4
Resolves __udivdi3 missing errors when building for i386. Fixes: 6378ef012ddc ("drm/amd/display: Add below the range support for FreeSync") Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-20drm/amdgpu/uvd:Change uvd ring name conventionJames Zhu1-2/+2
Since umr tool can't handle bracket, change uvd ring name convention. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-20drm/amd/powerplay: add Vega20 LCLK DPM level setting supportEvan Quan1-0/+43
Support manual LCLK DPM level switch on Vega20. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Rex Zhu <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-20drm/amdgpu: print process info when job timeoutTrigger Huang1-0/+6
When a job is timeout, try to print the related process information for debugging Signed-off-by: Trigger Huang <[email protected]> Reviewed-by: Christian König <[email protected]>. Signed-off-by: Alex Deucher <[email protected]>
2018-12-20drm/amdgpu/nbio7.4: add hw bug workaround for vega20Alex Deucher1-0/+7
Configure PCIE_CI_CNTL to work around a hw bug that affects some multi-GPU compute workloads. Acked-by: Feifei Xu <[email protected]> Reviewed-by: Harish Kasiviswanathan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-20drm/amdgpu/nbio6.1: add hw bug workaround for vega10/12Alex Deucher1-0/+7
Configure PCIE_CI_CNTL to work around a hw bug that affects some multi-GPU compute workloads. Acked-by: Feifei Xu <[email protected]> Reviewed-by: Harish Kasiviswanathan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amd/display: Optimize passive update planes.Yongqiang Sun1-3/+0
[Why] passive update planes still spends a litte more time on some cases. [How] Remove unnecessary trace which involving in some register read. Disable debug output for release build. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amd/display: verify lane status before exiting verify link capWenjing Liu2-119/+127
[why] DP LL CTS1.4 4.3.2.1 test failure. [how] The failure is caused by not handling DP link loss hpd short pusle during set mode. The change is to read link status before set mode link training. If link is lost, re-verify link caps. Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amd/display: Fix bug with not updating VSP infoframeSivapiriyanKumarasamy1-1/+2
[WHY] Currently, when the VSP infopacket is rebuilt in DM, it is not updated when being programmed in encoder. [HOW] Add new VSP case for update_info_frame Signed-off-by: SivapiriyanKumarasamy <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Krunoslav Kovac <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amd/display: Add retry to read ddc_clock pinPaul Hsieh1-6/+17
[WHY] On customer board, there is one pluse (1v , < 1ms) on DDC_CLK pin when plug / unplug DP cable. Driver will read it and config DP to HDMI/DVI dongle. [HOW] If there is a real dongle, DDC_CLK should be always pull high. Try to read again to recovery this special case. Retry times = 3. Need additional 3ms to detect DP passive dongle(3 failures) Signed-off-by: Paul Hsieh <[email protected]> Reviewed-by: Eric Yang <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amd/display: Don't skip link training for empty dongleEric Yang1-2/+16
[Why] Skipping initial link training will result in no verified link cap for mode enumeration. Some versions of the BIOS seem to have PHY programming sequence issue as well if initial link training is skipped, resulting in a softlock in BIOS command table. [How] Identify the empty dongle hotplug case, and still do initial link training. Signed-off-by: Eric Yang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amd/display: Wait edp HPD to high in detect_sinkDale Zhao1-0/+3
[Why] In 99% user case, edp will be post by vbios. In 1% / current case: Lenovo don't light up edp panel in vbios post stage, vbios won't be lit up. Thus in dal when we init DCN 10 hw, we power up edp, then we start detect_sink, but internal time is too short, when we detect it, HPD is still low, so we don't detect the edp, and edp shows black. [How] When we init hw, we wait edp HPD to high after power up edp. Signed-off-by: Dale Zhao <[email protected]> Reviewed-by: Eric Yang <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amd/display: fix surface update sequenceDmytro Laktyushkin1-2/+4
An earlier change added update of interdependent dlg/ttu params for pipes not being updated in the current call. The code fails to check if the other pipes are actually active yet causing an assert. This change adds a check for surface presence on the pipes before updating the interdepenednt params. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Nikola Cornij <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amd/display: fix YCbCr420 blank colorEric Yang2-1/+19
[Why] YCbCr420 packing format uses two chanels for luma, and 1 channel for both chroma component. Our previous implementation did not account for this and results in every other pixel having very high luma value, showing greyish color instead of black. YCbCr444 = <Y1, Cb1, Cr1>; <Y2, Cb2, Cr2> ..... YCbCr420 = <Y1, Y2, Cb1>; <Y3, Y4, Cr1> ..... [How] Program the second channel with the black color value for luma as well. Signed-off-by: Eric Yang <[email protected]> Reviewed-by: Hugo Hu <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amd/display: Warn instead of error on REG_WAIT timeoutDavid Francis1-2/+2
[Why] DC warns when a REG_WAIT takes a while and full-on errors with stack dump on REG_WAIT timeout. Most of the time it isn't a real issue. [How] Make DC cool its jets - taking a while is a debug message (because it is not something that normal users should need to be aware of), and timeouts are warnings (because it technically shouldn't happen, but it's not a big deal if it does) Signed-off-by: David Francis <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amd/display: move AYCrCb8888 format to video sectionDmytro Laktyushkin1-1/+1
This is a dual channel format and should be treated like other video formats Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Eric Bernstein <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amd/display: Don't log error if we have no connectorsHarry Wentland1-4/+0
[Why] In certain configurations, such as PX configs or some Vega20 parts DC gets created without connectors. [How] Drop the dm_error print when no connectors. Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amd/display: Add functionality to get XGMI SS infoLeo Li2-0/+16
[Why] When XGMI is enabled, the DP reference clock needs to be adjusted according to the XGMI spread spectrum percentage and mode. But first, we need the ability to fetch this info. [How] Within the BIOS parser, Read from vBIOS when XGMI SS info is requested. In addition, diags build uses include_legacy/atomfirmware.h for the smu_info_v3_3 table headers. Update that as well. Signed-off-by: Leo Li <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Tony Cheng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amd/display: Add DCE_VERSION_12_1 enum for Vega 20Leo Li6-1/+10
[Why] We'll need a way to differentiate Vega 20 in DC [How] Add a DCE_VERSION_12_1 enum, which will be returned as the DC version if the ASIC used is a Vega 20. Signed-off-by: Leo Li <[email protected]> Reviewed-by: David Francis <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amd/display: Add below the range support for FreeSyncNicholas Kazlauskas2-19/+63
[Why] When the flip-rate is below the minimum supported variable refresh rate range for the monitor the front porch wait will timeout and be frequently misaligned resulting in stuttering and/or flickering. The FreeSync module can still maintain a smooth and flicker free image when the monitor has a refresh rate range such that the maximum refresh > 2 * minimum refresh by utilizing low framerate compensation, "below the range". [How] Hook up the pre-flip and post-flip handlers from the FreeSync module. These adjust the minimum/maximum vrr range to duplicate frames when appropriate by tracking flip timestamps. Signed-off-by: Nicholas Kazlauskas <[email protected]> Acked-by: Leo Li <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amd/display: Raise dispclk value for PolarisRoman Li1-0/+7
[Why] The visual corruption due to low display clock value observed on some systems [How] There was earlier patch for dspclk: 'drm/amd/display: Raise dispclk value for dce_update_clocks' Adding +15% workaround also to to dce112_update_clocks Signed-off-by: Roman Li <[email protected]> Reviewed-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amd/display: Skip fast cursor updates for fb changesNicholas Kazlauskas1-0/+10
[Why] The behavior of drm_atomic_helper_cleanup_planes differs depending on whether the commit was asynchronous or not. When it's called from amdgpu_dm_atomic_commit_tail during a typical atomic commit the plane state has been swapped so it calls cleanup_fb on the old plane state. However, in the asynchronous commit codepath the call to drm_atomic_helper_commit also calls dm_plane_helper_cleanup_fb after atomic_async_update has been called. Since the plane state is updated in place and has not been swapped the cleanup_fb call affects the new plane state. This results in a use after free for the given sequence: - Fast update, fb1 pin/ref, fb1 unpin/unref - Fast update, fb2 pin/ref, fb2 unpin/unref - Slow update, fb1 pin/ref, fb2 unpin/unref - Fast update, fb2 pin/ref -> use after free. bug [How] Disallow framebuffer changes in the fast path. Since this includes a NULL framebuffer, this means that only framebuffers that have been previously pin+ref at least once will be used, preventing a use after free. This has a significant throughput reduction for cursor updates where the framebuffer changes. For most desktop usage this isn't a problem, but it does introduce performance regressions for two specific IGT tests: - cursor-vs-flip-toggle - cursor-vs-flip-varying-size Fixes: 2cc751931afc ("drm/amd/display: Add fast path for cursor plane updates") Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amdgpu: correct the return value for error caseEvan Quan3-16/+31
It should not return 0 for error case as '0' is actually a special value for index. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amdkfd: Fix handling of return code of dma_buf_getFelix Kuehling1-2/+2
On errors, dma_buf_get returns a negative error code, rather than NULL. Reported-by: Dan Carpenter <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amdgpu:Improves robustness of SOC15_WAIT_ON_RREGJames Zhu1-2/+7
If register value is updating, reset timeout counter. It improves robustness of SOC15_WAIT_ON_RREG. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amdgpu/vcn:Remove bit 31 for scratch2 to indicate the WA is activeJames Zhu1-2/+2
Remove bit 31 for scratch2 to indicate the Hardware bug work around is active. Signed-off-by: James Zhu <[email protected]> Acked-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amdgpu/vcn:Scan enc/jpeg fences to init dpg pause new stateJames Zhu1-4/+14
Scan enc/jpeg fences to init dpg pause new state in begin use. It will help set dpg mode to desire state actively. Signed-off-by: James Zhu <[email protected]> Acked-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amdgpu/vcn:Always check all vcn ring status during dpg mode stopJames Zhu1-8/+16
Always check all vcn ring status during dpg mode stop, it will help identify which vcn ring may cause the issue. Signed-off-by: James Zhu <[email protected]> Acked-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amdgpu/vcn:Update ring point to JPEG before init JPEG wptrJames Zhu1-1/+2
It is a bug fix. Signed-off-by: James Zhu <[email protected]> Acked-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amdgpu/vcn:Always gate vcn block during hw finishingJames Zhu1-1/+2
Under Dynamic Power Gate mode, UVD_STATUS needn't be checked. Signed-off-by: James Zhu <[email protected]> Acked-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>