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2019-03-20drm/amd/display: add global master update lock interfacesWenjing Liu2-0/+6
Add these interfacese for future use setup_global_lock() lock_global() pipe_control_lock_global() Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: Use dc_is_hdmi_signal() instead of ENUMEric Bernstein2-3/+2
Signed-off-by: Eric Bernstein <[email protected]> Reviewed-by: Nevenko Stupar <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: cache additional dpcd caps for HDR capability checkHarmanprit Tatla3-5/+50
[Why] Currently we are missing a few checks to see if HDR10 is allowed. In particular we never check for the extended colorimetry bit (whether its present or set to 1). Further we don't read in the dpcd block in DC that would provide these bits. [How] - Added in DC code to read in the block containing the extended colorimetry bit. Signed-off-by: Harmanprit Tatla <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: Update ABM crtc state on non-modesetDavid Francis1-0/+3
[Why] Somewhere in the atomic check reshuffle ABM got lost. ABM is a crtc property (copied from a connector property). It can change without a modeset, just like underscan. [How] In the skip_modeset branch of atomic check crtc updates, copy over the abm property. Signed-off-by: David Francis <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: Programming correct VRR_EN bit in VTEM structureHugo Hu1-2/+2
[Why] In HDMI plugfest, MTK report our EMP with VRR_EN bit = 0. VRR_EN bit is EMP-MD0-bit 0. Currently driver set 1 to bit 3. [How] Programming correct VRR_EN bit in EMP-MD0-bit0. Signed-off-by: Hugo Hu <[email protected]> Reviewed-by: Reza Amini <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: 3.2.22Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: extend EDID support to 1kbJun Lei1-1/+1
[why] There exist displays with EDIDs > 512 bytes, existing code will cause us to ignore all extension blocks. Signed-off-by: Jun Lei <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: Fix DP audio regressionWesley Chalmers1-3/+2
Audio was unmuted for HDMI only, need to do so for DP as well. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Chris Park <[email protected]> Reviewed-by: Eric Bernstein <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: Add a hysteresis to BTR frame multiplierAric Cyr1-2/+22
[Why] Flickering is observed on some displays when the number of inserted BTR frames changes frequently. [How] Add in a margin of drift to prevent the inserted number of frames from jumping around too frequently. Signed-off-by: Aric Cyr <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: fix DP 422 VID_M half the rate issue.Charlene Liu5-9/+31
[Description] when programming VID_TIMING, we were using the original VESA timing for DP_VIDM/N. for YCbCr420 or compressed YCbCr422, using half rate as YCbCr444. Signed-off-by: Charlene Liu <[email protected]> Reviewed-by: Nikola Cornij <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: Fix setting DP_VID_N_MULEric Bernstein3-4/+11
[Why] Need to set VID_N_MUL for 4:2:0 cases [How] Move setting to enc1_stream_encoder_dp_unblank and ensure it is also set for non-4:2:0 cases. Signed-off-by: Eric Bernstein <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: Move dm_read_reg_func to dc_helper.Yongqiang Sun2-17/+22
Move out of header to dc_helper.c, in preparation for future implementations. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: Use drm helper for resetting plane stateNicholas Kazlauskas1-7/+2
[Why] To help prevent plane state not being set to the correct default value if any new properties are added in the future. [How] Use the drm helper - which seems to be the common solution among other DRM drivers. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Sun peng Li <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: change generic_reg_wait to void.Yongqiang Sun3-6/+5
we were only checking the return value in one place, thus changing generic_reg_wait from int to void and reading the register instead of getting it from generic_reg_wait, when we need the return value. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: Reset alpha state for planes to the correct valuesNicholas Kazlauskas1-0/+2
[Why] The plane_reset callback is subclassed but hasn't been updated since the drm helper got updated to include resetting alpha related state (state->alpha and state->pixel_blend_mode). The overlay planes exposed by amdgpu_dm were therefore being rendered as invisible by default ever since supported was exposed for alpha blending properties on overlays. This caused regressions in igt@kms_plane_multiple@atomic-tiling-none and igt@kms_plane@plane-position-covered-pipe tests. [How] Reset the plane state values to their correct values as defined in the drm helper. This fixes the IGT test regression. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amdgpu: use more entries for the first paging queueChristian König1-0/+2
To aid recoverable page faults. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amdgpu: free up the first paging queue v2Christian König1-8/+14
We need the first paging queue to handle page faults. v2: handle any number of SDMA instances gracefully Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amdgpu: re-enable retry faultsChristian König2-2/+2
Now that we have re-reoute faults to the other IH ring we can enable retries again. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amdkfd/sriov:Put the pre and post reset in exclusive mode v2Wentao Lou1-0/+3
add amdgpu_amdkfd_pre_reset and amdgpu_amdkfd_post_reset inside amdgpu_device_reset_sriov. Signed-off-by: Wentao Lou <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amd/display: Respect DRM framebuffer info for video surfacesNicholas Kazlauskas1-11/+10
[Why] Incorrect hardcoded assumptions are made regarding luma and chroma alignment. The actual values set for the DRM framebuffer should be used when programming the address. [How] Respect the given pitch for both luma and chroma planes - it's not like we can force the alignment to anything else at this point anyway. Use the FB offset for the chroma planes directly. DRM already provides this to us so there's no need to calculate it manually. While we don't actually use the chroma surface size parameters on Raven, these should have technically been fb->width / 2 and fb->height / 2 since the chroma plane is half size of the luma plane for NV12. Leave a TODO indicating that those should be set based on the actual surface format instead since this is only correct for YUV420 formats. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amdgpu: Wait for newly allocated PTs to be idleFelix Kuehling1-7/+13
When page table are updated by the CPU, synchronize with the allocation and initialization of newly allocated page tables. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-20drm/amdgpu: more descriptive message if HMM not enabledPhilip Yang1-0/+2
If using old kernel config file, CONFIG_ZONE_DEVICE is not selected, so CONFIG_HMM and CONFIG_HMM_MIRROR is not enabled, the current driver error message "Failed to register MMU notifier" is not clear. Inform user with more descriptive message on how to fix the missing kernel config option. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109808 Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: support userptr cross VMAs case with HMMPhilip Yang1-35/+91
userptr may cross two VMAs if the forked child process (not call exec after fork) malloc buffer, then free it, and then malloc larger size buf, kerenl will create new VMA adjacent to old VMA which was cloned from parent process, some pages of userptr are in the first VMA, the rest pages are in the second VMA. HMM expects range only have one VMA, loop over all VMAs in the address range, create multiple ranges to handle this case. See is_mergeable_anon_vma in mm/mmap.c for details. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdkfd: support concurrent userptr update for HMMPhilip Yang1-6/+19
Userptr restore may have concurrent userptr invalidation after hmm_vma_fault adds the range to the hmm->ranges list, needs call hmm_vma_range_done to remove the range from hmm->ranges list first, then reschedule the restore worker. Otherwise hmm_vma_fault will add same range to the list, this will cause loop in the list because range->next point to range itself. Add function untrack_invalid_user_pages to reduce code duplication. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: stop evicting busy PDs/PTsChristian König1-0/+7
Otherwise we won't be able to cleanly handle page faults. Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: wait for VM to become idle during flushChristian König5-7/+22
Make sure that not only the entities are flush, but that we also wait for the HW to finish all processing. Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: remove non-sense NULL ptr checkChristian König1-10/+0
It's a bug having a dead pointer in the IDR, silently returning is the worst we can do. Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: remove chashChristian König8-1186/+0
Remove the chash implementation for now since it isn't used any more. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: use ring/hash for fault handling on GMC9 v3Christian König3-57/+92
Further testing showed that the idea with the chash doesn't work as expected. Especially we can't predict when we can remove the entries from the hash again. So replace the chash with a ring buffer/hash mix where entries in the container age automatically based on their timestamp. v2: use ring buffer / hash mix v3: check the timeout to make sure all entries age Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> (v2) Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: limit the number of IVs processed at onceChristian König2-1/+5
Only process a maximum of 32 IVs before writing back the RPTR. This improves hw handling when we get close to an overflow in the ring buffer. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: enable IH ring 1&2 for Vega20 as wellChristian König1-17/+13
That doesn't seem to have any negative effects. Signed-off-by: Christian König <[email protected]> Acked-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: enable IH doorbell for ring 1&2 on VegaChristian König2-24/+45
The doorbells should already be reserved, just enable them. Signed-off-by: Christian König <[email protected]> Acked-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: change Vega IH ring 1 configChristian König1-0/+4
Disable overflow and enable full drain. This makes fault handling on ring 1 much more reliable since we don't generate back pressure any more. Signed-off-by: Christian König <[email protected]> Acked-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: Only clear dumb buffers if ring is enabledNicholas Kazlauskas1-3/+10
The buffers should be cleared when possible but we also don't want buffer creation to fail in the rare case where the ring isn't ready during the call. This could happen during some suspend/resume sequences. Cc: Christian König <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: Clear VRAM for DRM dumb_create buffersNicholas Kazlauskas1-1/+2
The dumb_create API isn't intended for high performance rendering and it's more useful for userspace (ie. IGT) to have them precleared. The bonus here is that we also won't needlessly leak whatever was previously in VRAM, but it also probably wasn't sensitive if it was going through this API. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: fix semicolon.cocci warningskbuild test robot1-2/+2
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:405:2-3: Unneeded semicolon drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:435:2-3: Unneeded semicolon Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci CC: xinhui pan <[email protected]> Signed-off-by: kbuild test robot <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: add new ras workflow control flagsxinhui pan3-1/+39
add ras post init function. Do some initialization after all IP have finished their late init. Add new member flags which will control the ras work flow. For now, vbios enable ras for us on boot. That might change in the future. So there should be a flag from vbios to tell us if ras is enabled or not on boot. Looks like there is no such info now. Other bits of the flags are reserved to control other parts of ras. Signed-off-by: xinhui pan <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: let ras initialization a little noticeablexinhui pan1-2/+7
add drm info output if ras initialized successfully. add ras atomfirmware sanity check. Signed-off-by: xinhui pan <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: Fix lockdep warning more gracelyxinhui pan1-6/+2
lockdep need a static key. Previously we set ignore bit to avoid the warning. Now call sysfs_attr_init to initialize the static key. Signed-off-by: xinhui pan <[email protected]> Reviewed-and-Tested-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: Fix ras debugfs data parsexinhui pan1-1/+1
Unzero char is accepted by sscanf, so when data is structure but unexpectedly return error invalid; Signed-off-by: xinhui pan <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: add new member hw_supportedxinhui pan2-12/+33
Currently, it is not clear how ras is supported. Both software and hardware can set the supported. That is confusing. Fix it by adding new member hw_supported. Signed-off-by: xinhui pan <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: Fix warning when lockdep is enabledxinhui pan1-0/+6
Set ignore bit to satisfy locpdep. Signed-off-by: xinhui pan <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: Fix NULL pointer when ta is missingxinhui pan1-9/+15
Ta is optional, so check if ta firmware is loaded or not. Signed-off-by: xinhui pan <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: fix ras parameter descriptionsEvan Quan1-4/+4
The descriptions of modinfo wrongly show two parameters for each feature(see below). This patch can fix this incorrect outputs. parm: amdgpu_ras_enable:Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) parm: ras_enable:int parm: amdgpu_ras_mask:Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 parm: ras_mask:uint Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: xinhui pan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: export both supported and enabled ras featuresxinhui pan1-2/+5
Signed-off-by: xinhui pan <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: lookup vbios table to check ecc capabilityxinhui pan1-27/+13
Signed-off-by: xinhui pan <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: query sram ecc/ecc availability from atombiosHawking Zhang1-205/+23
query sram ecc capability via amdgpu_atomfirmware_ecc_default_enabled query ecc availability via amdgpu_atomfirmware_sram_ecc_supported Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: add atomfirmware helper function to query sram ecc capsHawking Zhang2-0/+31
sram ecc capability could be get from firmware_capability field in firmwareinfo table Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: add atomfirmware helper function to query ecc statusHawking Zhang2-0/+32
ecc default status (enabled or disabled) could be get from umc_config field in umc_info table Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: update atomfirmware header with ecc related membersHawking Zhang1-0/+53
add new umc_info structures and new firmware_capability defines Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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