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2019-02-15arm64: dts: ti: k3-am65: Add MSMC RAM nodeRoger Quadros1-0/+20
The AM65 SoC has 2MB MSMC RAM. Add this as a mmio-sram node so drivers can use it via genpool API. Following areas are marked reserved: - Lower 128KB for ATF - 64KB@0xf0000 for SYSFW - Upper 1MB for cache The reserved locations are subject to change at runtime by the bootloader. Cc: Nishanth Menon <[email protected]> Cc: Lokesh Vutla <[email protected]> Cc: Andrew F. Davis <[email protected]> Signed-off-by: Roger Quadros <[email protected]> Signed-off-by: Tero Kristo <[email protected]>
2019-02-15arm64: dts: uniphier: sort labels in the same order as in dtsiMasahiro Yamada2-6/+6
Sort the labels in the same order as in the corresponding dtsi file, in other words, the order of reg address. Signed-off-by: Masahiro Yamada <[email protected]>
2019-02-15arm64: dts: uniphier: Add PCIe host controller and PHY nodesKunihiko Hayashi3-0/+98
Add PCIe host controller and PHY nodes. This supports for LD20, PXs3 and their boards. This node defines PCIe memory, I/O, and config spaces as follows. MEM: 20000000-2ffdffff (255MB) I/O: 2ffe0000-2ffeffff ( 64KB) CFG: 2fff0000-2fffffff ( 64KB) Signed-off-by: Kunihiko Hayashi <[email protected]> Signed-off-by: Masahiro Yamada <[email protected]>
2019-02-12ARM: dts: omap3-gta04: declare backlight in lcd nodeAndreas Kemnade1-1/+2
The lcd display of the gta04 has a backlight but the backlight was not referenced in the lcd node, so screen blanking did not turn off the backlight. Fix that. Signed-off-by: Andreas Kemnade <[email protected]> Tested-by: H. Nikolaus Schaller <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
2019-02-12ARM: dts: am335x: Add support for Bosch GuardianMartyn Welch2-0/+512
The Bosch Guardian is a TI am335x based device. It's hardware specifications are as follows: * 256 MB DDR3 memory * 512 MB NAND Flash * USB OTG * RS232 * MicroSD external storage * LCD Display interface Signed-off-by: Martyn Welch <[email protected]> [[email protected]: updated to use #include] Signed-off-by: Tony Lindgren <[email protected]>
2019-02-12ARM: dts: zynq: replace gpio-key,wakeup with wakeup-source propertySudeep Holla1-1/+1
Most of the legacy "gpio-key,wakeup" boolean property is already replaced with "wakeup-source". However few occurrences of old property has popped up again, probably from the remnants in downstream trees. Replace the legacy properties with the unified "wakeup-source" property introduced in the commit 700a38b27eef ("Input: gpio_keys - switch to using generic device properties") Cc: Michal Simek <[email protected]> Signed-off-by: Sudeep Holla <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2019-02-12ARM: dts: imx: Add support for Logic PD i.MX6QD EVMAdam Ford3-0/+1040
The EVM consists of a system on module (SOM) and baseboard, and LCD. This patch adds a DTSI file for the SOM and baseboard separately, then a wrapper to combine them and specify processor type and a LCD information. Signed-off-by: Adam Ford <[email protected]> Reviewed-by: Fabio Estevam <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-12ARM: dts: imx6qdl-sabresd: remove reg_sensors' regulator-always-onAnson Huang1-1/+0
Now that all sensors supplied by reg_sensors have supported regulator control, reg_sensors does NOT need to be always ON, remove "regulator-always-on" to save power. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-12ARM: dts: imx6qdl-sabresd: add regulators control for mma8451 sensorAnson Huang1-0/+2
The mma8451 sensor driver has supported regulators control, assign the power supplies for mma8451 to enable the control. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-12ARM: dts: imx6qdl-sabresd: add regulators control for mag3110 sensorAnson Huang1-0/+2
The mag3110 sensor driver has supported regulators control, assign the power supplies for mag3110 to enable the control. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-12ARM: dts: imx6qdl-sabresd: add regulator control for isl29023 sensorAnson Huang1-0/+1
The isl29023 light sensor driver has supported regulator control, assign the power supply for isl29023 to enable the control. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-12ARM: dts: vf610: Add ZII SSMB DTU boardAndrew Lunn2-0/+312
Add the Zodiac Digital Tapping Unit, a VF610 based network device with 5 Ethernet ports. One of these ports supports 1000Base-T2. Signed-off-by: Andrew Lunn <[email protected]> Reviewed-by: Fabio Estevam <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-12ARM: dts: pfla02: add ksz9031 clock skew valuesPhilipp Zabel1-0/+13
The pfla02 SoM has a Micrel KSZ9031RNX ethernet phy connected to the FEC, which needs RX and TX clock skew settings to compensate for differences in line length. The skew values are taken from barebox commit 4c65c20f1071 ("ARM: pfla02: Set new ethernet phy tx timings"), which is based on patches originally provided by Phytec: TX_CLK line is approx. 54mm longer than other TX lines which adds a delay of 0.36ns. RGMII need a delay of min. 1.0ns. This mean we have to add a delay of 0.64ns. We choose 0.78 to have a little gap. This can be done by setting GTX pad skew value to 11100 Also add a delay for the RX delay lines, needed for the Duallite variant. => Set register 2.8 (RGMII Clock Pad Skew) to 0x039F. Cc: Christian Hemp <[email protected]> Signed-off-by: Philipp Zabel <[email protected]> Signed-off-by: Marco Felsch <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-12ARM: dts: imx6qdl-phytec-pfla02: add missing interrupt-controller propertyMarco Felsch1-0/+1
The DA9063 device need the required "interrupt-controller" property as documented by the bindings [1]. [1] Documentation/devicetree/bindings/mfd/da9063.txt Signed-off-by: Marco Felsch <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-11ARM: dts: meson8b: ec100: add the GPIO line namesMartin Blumenstingl1-0/+50
This adds the GPIO line names from the schematics to get them displayed in the debugfs output of each GPIO controller. Signed-off-by: Martin Blumenstingl <[email protected]> Signed-off-by: Kevin Hilman <[email protected]>
2019-02-11ARM: dts: meson8b: ec100: improve the description of the regulatorsMartin Blumenstingl1-0/+68
USB_VBUS is a controlled by a Silergy SY6288CCAC-GP 2A Power Distribution Switch. The name of it's enable GPIO signal is USB_PWR_EN. VCC5V is supplied by the main power input called PWR_5V_STB. The name of it's enable GPIO signal is 3V3_5V_EN. VCC3V3, VCC_DDR3_1V5 and VCCK (the CPU power supply) each use a separate Silergy SY8089AAC-GP 2A step down regulator. They are all supplied by the board's main 5V. VCC3V3 and VCC_DDR3_1V5 are fixed regulators while the voltage of VCCK can be changed by changing it's feedback voltage via PWM_C. VCC1V8 is an ABLIC S-1339D18-M5001-GP fixed voltage regulator which is supplied by VCC3V3. VCC_RTC is a Global Mixed-mode Technology Inc. G918T12U-GP LDO which. It is supplied by either VCC3V3 (when the board is powered) or the RTC coin cell battery. Signed-off-by: Martin Blumenstingl <[email protected]> Signed-off-by: Kevin Hilman <[email protected]>
2019-02-11ARM: dts: meson8b: ec100: enable the Ethernet PHY interruptMartin Blumenstingl1-0/+4
The INTR32 pin of the IP101GR Ethernet PHY is routed to the GPIOH_3 pad on the SoC. Enable the interrupt function of the PHY's INTR32 pin to switch it from it's default "receive error" mode to "interrupt pin" mode. Signed-off-by: Martin Blumenstingl <[email protected]> Signed-off-by: Kevin Hilman <[email protected]>
2019-02-11ARM: dts: meson8m2: mxiii-plus: add iio-hwmon for the chip temperatureMartin Blumenstingl1-0/+5
SAR ADC enabled channel 8 can be used to measure the chip temperature. This can be made available to the hwmon subsystem by using iio-hwmon. Signed-off-by: Martin Blumenstingl <[email protected]> Signed-off-by: Kevin Hilman <[email protected]>
2019-02-11ARM: dts: meson8b: odroidc1: add iio-hwmon for the chip temperatureMartin Blumenstingl1-0/+5
SAR ADC enabled channel 8 can be used to measure the chip temperature. This can be made available to the hwmon subsystem by using iio-hwmon. Signed-off-by: Martin Blumenstingl <[email protected]> Signed-off-by: Kevin Hilman <[email protected]>
2019-02-11ARM: dts: meson8b: ec100: add iio-hwmon for the chip temperatureMartin Blumenstingl1-0/+5
SAR ADC enabled channel 8 can be used to measure the chip temperature. This can be made available to the hwmon subsystem by using iio-hwmon. Signed-off-by: Martin Blumenstingl <[email protected]> Signed-off-by: Kevin Hilman <[email protected]>
2019-02-11ARM: dts: meson8b: add the temperature calibration data for the SAR ADCMartin Blumenstingl1-0/+8
The SAR ADC can measure the chip temperature of the SoC. This only works if the chip is calibrated and if the calibration data is written to the correct registers. The calibration data is stored in the upper two bytes of eFuse offset 0x1f4. This adds the eFuse cell for the temperature calibration data and passes it to the SAR ADC. We also need to pass the HHI sysctrl node to the SAR ADC because the 4th TSC (temperature sensor calibration coefficient) bit is stored in the HHI region (unlike bits [3:0] which are stored directly inside the SAR ADC's register area). On boards that have the SAR ADC enabled channel 8 can be used to measure the chip temperature. Signed-off-by: Martin Blumenstingl <[email protected]> Signed-off-by: Kevin Hilman <[email protected]>
2019-02-11ARM: dts: meson8: add the temperature calibration data for the SAR ADCMartin Blumenstingl1-0/+8
The SAR ADC can measure the chip temperature of the SoC. This only works if the chip is calibrated and if the calibration data is written to the correct registers. The calibration data is stored in the upper two bytes of eFuse offset 0x1f4. This adds the eFuse cell for the temperature calibration data and passes it to the SAR ADC. We also need to pass the HHI sysctrl node to the SAR ADC because the 4th TSC (temperature sensor calibration coefficient) bit is stored in the HHI region (unlike bits [3:0] which are stored directly inside the SAR ADC's register area). On boards that have the SAR ADC enabled channel 8 can be used to measure the chip temperature. Signed-off-by: Martin Blumenstingl <[email protected]> Signed-off-by: Kevin Hilman <[email protected]>
2019-02-11ARM: dts: meson8m2: use the Meson8m2 specific SAR ADC compatibleMartin Blumenstingl1-0/+4
The SAR ADC on Meson8m2 is slightly different compared to Meson8. The ADC functionality is identical but the calibration of the internal thermal sensor is different. Use the Meson8m2 specific compatible so the temperature sensor is calibrated correctly on boards using the Meson8m2 SoC. Signed-off-by: Martin Blumenstingl <[email protected]> Signed-off-by: Kevin Hilman <[email protected]>
2019-02-11ARM: dts: meson: switch the clock controller to the HHI register areaMartin Blumenstingl3-14/+23
The clock controller on Meson8/Meson8m2 and Meson8b is part of a register region called "HHI". This register area contains more functionality than just a clock controller: - the clock controller - some reset controller bits - temperature sensor calibration data (on Meson8b and Meson8m2 only) - HDMI controller Allow access to this HHI register area as "system controller". Also migrate the Meson8 and Meson8b clock controllers to this new node. Signed-off-by: Martin Blumenstingl <[email protected]> Acked-by: Neil Armstrong <[email protected]> Signed-off-by: Kevin Hilman <[email protected]>
2019-02-11ARM: dts: meson8b: fix the Ethernet data line signals in eth_rgmii_pinsMartin Blumenstingl1-3/+3
According to the Odroid-C1+ schematics the Ethernet TXD1 signal is routed to GPIOH_5 and the TXD0 signal is routed to GPIOH_6. The public S805 datasheet shows that TXD0 can be routed to DIF_2_P and TXD1 can be routed to DIF_2_N instead. The pin groups eth_txd0_0 (GPIOH_6) and eth_txd0_1 (DIF_2_P) are both configured as Ethernet TXD0 and TXD1 data lines in meson8b.dtsi. At the same time eth_txd1_0 (GPIOH_5) and eth_txd1_1 (DIF_2_N) are configured as TXD0 and TXD1 data lines as well. This results in a bad Ethernet receive performance. Presumably this is due to the eth_txd0 and eth_txd1 signal being routed to the wrong pins. As a result of that data can only be transmitted on eth_txd2 and eth_txd3. However, I have no scope to fully confirm this assumption. The vendor u-boot sources for Odroid-C1 use the following Ethernet pinmux configuration: SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_6, 0x3f4f); SET_CBUS_REG_MASK(PERIPHS_PIN_MUX_7, 0xf00000); This translates to the following pin groups in the mainline kernel: - register 6 bit 0: eth_rxd1 (DIF_0_P) - register 6 bit 1: eth_rxd0 (DIF_0_N) - register 6 bit 2: eth_rx_dv (DIF_1_P) - register 6 bit 3: eth_rx_clk (DIF_1_N) - register 6 bit 6: eth_tx_en (DIF_3_P) - register 6 bit 8: eth_ref_clk (DIF_3_N) - register 6 bit 9: eth_mdc (DIF_4_P) - register 6 bit 10: eth_mdio_en (DIF_4_N) - register 6 bit 11: eth_tx_clk (GPIOH_9) - register 6 bit 12: eth_txd2 (GPIOH_8) - register 6 bit 13: eth_txd3 (GPIOH_7) - register 7 bit 20: eth_txd0_0 (GPIOH_6) - register 7 bit 21: eth_txd1_0 (GPIOH_5) - register 7 bit 22: eth_rxd3 (DIF_2_P) - register 7 bit 23: eth_rxd2 (DIF_2_N) Drop the eth_txd0_1 and eth_txd1_1 groups from eth_rgmii_pins to fix the Ethernet transmit performance on Odroid-C1. Also add the eth_rxd2 and eth_rxd3 groups so we don't rely on the bootloader to set them up. iperf3 statistics before this change: - transmitting from Odroid-C1: 741 Mbits/sec (0 retries) - receiving on Odroid-C1: 199 Mbits/sec (1713 retries) iperf3 statistics after this change: - transmitting from Odroid-C1: 667 Mbits/sec (0 retries) - receiving on Odroid-C1: 750 Mbits/sec (0 retries) Fixes: b96446541d8390 ("ARM: dts: meson8b: extend ethernet controller description") Signed-off-by: Martin Blumenstingl <[email protected]> Cc: Emiliano Ingrassia <[email protected]> Cc: Linus Lüssing <[email protected]> Tested-by: Emiliano Ingrassia <[email protected]> Reviewed-by: Emiliano Ingrassia <[email protected]> Signed-off-by: Kevin Hilman <[email protected]>
2019-02-11arm64: dts: imx8mq: specify dma-rangesLucas Stach1-0/+1
The peripheral bus on the i.MX8MQ is still limited to 32bits, so we need to declare the usable range for device DMA operations, as the DRAM will extend across the 32bit boundary if more than 3GB are installed. Signed-off-by: Lucas Stach <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-11arm64: dts: imx8mq: Add ARM PMU nodeCarlo Caione1-0/+7
Add the node for the ARM Performance Monitor Units. Signed-off-by: Carlo Caione <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-11arm64: dts: imx8mq: Add RTC supportAbel Vesa1-0/+14
Add RTC support for i.MX8MQ. Signed-off-by: Abel Vesa <[email protected]> Tested-by: Chris Spencer <[email protected]> Reviewed-by: Fabio Estevam <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-11arm64: dts: imx8mq-evk: Enable the QuadSPI controllerCarlo Caione1-0/+26
Enable the Freescale/NXP QuadSPI controller with a proper pinctrl set on the i.MX8MQ EVK board. Signed-off-by: Carlo Caione <[email protected]> Reviewed-by: Lucas Stach <[email protected]> Reviewed-by: Fabio Estevam <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-11arm64: dts: imx8mq: Add QuadSPI controllerCarlo Caione1-1/+16
Add a node for the Freescale/NXP QuadSPI controller and extend the AIPS3 memory range to accommodate the QuadSPI-memory region. Signed-off-by: Carlo Caione <[email protected]> Reviewed-by: Lucas Stach <[email protected]> Reviewed-by: Fabio Estevam <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-11arm64: dts: imx8mq: Add ECSPI supportFabio Estevam1-0/+39
Add support for the three ECSPI ports present on i.MX8MQ. Signed-off-by: Fabio Estevam <[email protected]> Reviewed-by: Lucas Stach <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-11ARM: dts: Add stmpe-adc DT node to Toradex iMX6 modulesPhilippe Schenker2-16/+28
Add the stmpe-adc DT node as found on Toradex iMX6 modules Signed-off-by: Philippe Schenker <[email protected]> Reviewed-by: Stefan Agner <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-11ARM: dts: Add devicetree compatibles for LS1021A based boardsManivannan Sadhasivam3-0/+3
Add missing devicetree compatibles for the following LS1021A based boards: ls1021a-moxa-uc-8410a.dts ls1021a-qds.dts ls1021a-twr.dts Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-11ARM: dts: colibri: use valid range configuration for weimStefan Agner1-2/+3
A valid WEIM range configuration must specify range entries for all four chip selects. This fixes an error on boot: imx-weim: probe of 21b8000.weim failed with error -22 Signed-off-by: Stefan Agner <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-11ARM: dts: imx6: Add support for Phytec phyBOARD i.MX6UL SeginMartyn Welch5-0/+622
The Phytec phyBOARD Segin is i.MX6 based SBC, available with either an i.MX6UL or i.MX6ULL SOM and various add-on boards. The following adds support for the "Full Featured" version of the Segin, which is provided with the i.MX6UL SOM and the PEB-EVAL-01 evaluation module. Its hardware specifications are: * 512MB DDR3 memory * 512MB NAND flash * Dual 10/100 Ethernet * USB Host and USB OTG * RS232 * MicroSD external storage * Audio, RS232, I2C, SPI, CAN headers * Further I/O options via A/V and Expansion headers Signed-off-by: Martyn Welch <[email protected]> Reviewed-by: Fabio Estevam <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-11ARM: dts: imx6*-apalis/-colibri: mark I2C recovery GPIOs as open drainStefan Agner3-8/+8
Since commit d2d0ad2aec4a ("i2c: imx: use open drain for recovery GPIO") GPIO lib expects this GPIO to be configured as open drain. Make sure we define this GPIO as open drain in the device tree. This gets rid of the following warning: gpio-81 (scl): enforced open drain please flag it properly in DT/ACPI DSDT/board file Note that currently the i.MX pinctrl driver does not support enabling open drain directly, so this patch has no effect in practice. Open drain is enabled by the fixed pinmux entry. Signed-off-by: Stefan Agner <[email protected]> Reviewed-by: Philippe Schenker <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-11ARM: dts: vf610-zii-ssmb-spu3: Pass "no-sdio"/"no-sd" propertiesFabio Estevam1-0/+3
esdhc0 is connected to an eMMC, so it is safe to pass the "no-sdio"/"no-sd" properties. esdhc1 is wired to a standard SD socket, so pass the "no-sdio" property. Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-11ARM: dts: imx: Add Y Soft IOTA Draco, Hydra and Ursa boardsVokáč Michal5-0/+760
These are i.MX6S/DL based SBCs embedded in various Y Soft products. All share the same board design but have slightly different HW configuration. Ursa - i.MX6S SoC, 512MB RAM DDR3, 4GB eMMC, microSD - parallel WVGA 7" LCD with touch panel - 1x Eth (QCA8334 switch) - USB OTG - USB host (micro-B) Draco - i.MX6S SoC, 512MB RAM DDR3, 4GB eMMC, microSD - parallel WVGA 7" LCD with touch panel - 2x Eth (QCA8334 switch) - USB OTG - USB host (micro-B) - RGB LED (I2C LP5562) - 3.5mm audio jack + codec (LM49350) Hydra - i.MX6DL SoC, 2GB RAM DDR3, 4GB eMMC, microSD - I2C OLED display, capacitive matrix keys - 2x Eth (QCA8334 switch) - USB OTG - RGB LED (I2C LP5562) - 3.5mm audio jack + codec (LM49350) - HDMI - miniPCIe slot Cc: Andrew Lunn <[email protected]> Signed-off-by: Michal Vokáč <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-11ARM: dts: imx7ulp: add sim nodeAnson Huang1-0/+13
i.MX7ULP SoC revision info is inside the SIM mode's JTAG_ID register, add sim node to support SoC revision check. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-11ARM: dts: imx6ull: change to use new compatible "fsl,imx6ull-usdhc" for usdhcBOUGH CHEN1-0/+8
i.MX6ULL has errata ERR010450, there is I/O timing limitation, for SDR mode, SD card clock can't exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz. This patch change to use the new compatible "fsl,imx6ull-usdhc" to follow this limitation. Signed-off-by: Haibo Chen <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-11ARM: dts: imx6ull: Fix i.MX6ULL/ULZ ocotp compatibleStefan Wahren1-0/+4
Since imx6ulz.dtsi includes imx6ull.dtsi, we only need to fix the compatible string here to achieve the correct OTP size for both SoCs. Signed-off-by: Stefan Wahren <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-11ARM: dts: imx6sx: Add DISPLAY power domain supportLeonard Crestez1-1/+18
This was implemented in the driver but not actually defined and referenced in dts. This makes it always on. From reference manual in section "10.4.1.4.1 Power Distribution": "Display domain - The DISPLAY domain contains GIS, CSI, PXP, LCDIF, PCIe, DCIC, and LDB. It is supplied by internal regulator." The current pd_pcie is actually only for PCIE_PHY, the PCIE ip block is actually inside the DISPLAY domain. Handle this by adding the pcie node in both power domains. Signed-off-by: Leonard Crestez <[email protected]> Acked-by: Lucas Stach <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-08arm64: dts: marvell: armada-37xx: link USB hosts with their PHYsMiquel Raynal1-0/+4
Reference the PHY nodes from the USB controller nodes. The USB3 host controller is wired to: * the first PHY of the COMPHY IP * the OTG-capable UTMI PHY The USB2 host controller is wired to: * the host-only UTMI PHY Signed-off-by: Miquel Raynal <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]>
2019-02-08arm64: dts: marvell: armada-3720-espressobin: declare SATA PHY propertyMiquel Raynal1-0/+2
The SATA node is wired to the third PHY of the COMPHY IP. Suggested-by: Grzegorz Jaszczyk <[email protected]> Signed-off-by: Miquel Raynal <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]>
2019-02-08arm64: dts: marvell: armada-3720-espressobin: declare PCIe PHYMiquel Raynal1-0/+1
The PCIe node is wired to the second PHY of the COMPHY IP. Suggested-by: Grzegorz Jaszczyk <[email protected]> Signed-off-by: Miquel Raynal <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]>
2019-02-08arm64: dts: marvell: armada-37xx: declare the COMPHY nodeMiquel Raynal1-0/+29
Describe the A3700 COMPHY node. It has three PHYs that can be configured as follow: * PCIe or GbE * USB3 or GbE * SATA or USB3 Each of them has its own memory area. Suggested-by: Grzegorz Jaszczyk <[email protected]> Signed-off-by: Miquel Raynal <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]>
2019-02-08arm64: dts: marvell: Remove unnecessary #address-cells/#size-cells under flashesGregory CLEMENT2-8/+0
By using the new binding for the partitions for the flashes we don't need anymore to use #size-cells and #address-cells at the flash node level. Signed-off-by: Gregory CLEMENT <[email protected]>
2019-02-08arm64: dts: armada-3720-espressobin: Set mv88e6341 cpu port as RGMII-IDRemi Pommarel1-0/+5
The mv88e6341 ethernet switch needs the cpu port control register to be set with TX and RX internal delay in order to work. This fixes ethernet support on system booted via a bootloader that has not already configured this register (e.g. mainline u-boot, or vendor u-boot compiled without ethernet support). Signed-off-by: Remi Pommarel <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]>
2019-02-08arm64: dts: armada-3720-espressobin: Configure RGMII and SMI pinsRemi Pommarel2-0/+7
In order to be able to communicate with the 88e6341 switch some pins have to be repurposed as RGMII and SMI pins. This fixes ethernet support on system booted via a bootloader that has not already configured those pins (e.g. mainline u-boot, or vendor u-boot compiled without ethernet support). Signed-off-by: Remi Pommarel <[email protected]> Signed-off-by: Gregory CLEMENT <[email protected]>
2019-02-08arm64: dts: meson: add g12a x96 max boardKevin Hilman2-0/+29
Add the G12a (S905X2) based X96 Max board[1]. There is no branding for the manufacturer anywhere on the product, so it took some digging[2] to find the manufacturer. But since there's nothing about the maker on the product I've left it out of the DT name because 1) nobody will know that name and 2) keeps the DT filename shorter. [1] https://www.cnx-software.com/2018/09/25/x96-max-amlogic-s905x2-tv-box/ [2] https://fccid.io/2AI6D-X96MAX Acked-by: Martin Blumenstingl <[email protected]> Signed-off-by: Kevin Hilman <[email protected]>
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