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2019-02-01ARM: dts: bcm2837-rpi-3-b-plus: Clarify label for STATUS_LEDStefan Wahren1-1/+1
The RPI 3 B+ provides control to both LEDs (PWR and ACT). So append the first letter of the LED color (like in the schematics) in order to clarify this. Signed-off-by: Stefan Wahren <[email protected]> Tested-by: Peter Robinson <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
2019-02-01ARM: dts: bcm2837-rpi-3-b: Use consistent label for HDMI hotplugStefan Wahren1-1/+1
This make the GPIO label for HDMI hotplug more consistent to the other boards. Signed-off-by: Stefan Wahren <[email protected]> Tested-by: Peter Robinson <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
2019-02-01ARM: dts: bcm2835: Fix labels for GPIO 0,1Stefan Wahren4-8/+8
According to the schematics for all RPis with a 40 pin header, the GPIOs 0 and 1 are labeled as ID_SD and ID_SC. In order to clarify that is a I2C bus, append the third letter. Signed-off-by: Stefan Wahren <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
2019-02-01ARM: dts: bcm2835-rpi: Drop unnecessary #address-cells/#size-cellsStefan Wahren1-2/+0
Compiling the bcm2835-rpi.dtsi with W=1 leads to the following warning: Warning (avoid_unnecessary_addr_size): /soc/firmware: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Fix this by removing these unnecessary properties. Signed-off-by: Stefan Wahren <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
2019-02-01ARM: dts: bcm283x: Fix DTC warning for memory nodeStefan Wahren6-6/+6
Compiling the bcm283x DTS with W=1 leads to the following warning: Warning (unit_address_vs_reg): /memory: node has a reg or ranges property, but no unit name Fix this by adding the unit address. Signed-off-by: Stefan Wahren <[email protected]> Tested-by: Peter Robinson <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
2019-02-01ARM: dts: add Raspberry Pi 3 A+Stefan Wahren2-0/+176
The Raspberry Pi 3 A+ is similar to the Pi 3 B+ but has only 512 MB RAM, 1 USB 2.0 port and no Ethernet. Compared to the Raspberry Pi 3 B it isn't possible to control BT_ON and WL_ON separately. Signed-off-by: Stefan Wahren <[email protected]> Acked-by: Eric Anholt <[email protected]>
2019-02-01dt-bindings: bcm: Add Raspberry Pi 3 A+Stefan Wahren1-0/+4
This adds the root properties for the Raspberry Pi 3 A+ . Signed-off-by: Stefan Wahren <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2019-02-01ARM: dts: stm32: Enable thermal sensor support on STM32MP157c-ed1David Hernandez Sanchez1-0/+4
Enable STM32 Digital Thermal Sensor (dts) driver for STM32MP157c-ed1 board. Signed-off-by: David Hernandez Sanchez <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2019-02-01ARM: dts: stm32: add SPI support on STM32F429 SoCCezary Gapinski1-0/+60
This patch adds all SPI instances of the STM32F429 SoC. Signed-off-by: Cezary Gapinski <[email protected]> Signed-off-by: Alexandre Torgue <[email protected]>
2019-02-01arm64: dts: ti: k3-am654-base-board: Add eMMC SupportFaiz Abbas1-0/+25
On the am654x-evm, sdhci0 node is connected to an eMMC. Add node and pinmux for the same. Signed-off-by: Faiz Abbas <[email protected]> Acked-by: Nishanth Menon <[email protected]> Signed-off-by: Tero Kristo <[email protected]>
2019-02-01arm64: dts: ti: k3-am654: Add Support for eMMC host controllerFaiz Abbas1-0/+14
Add support for the Secure Digital Host Controller Interface (SDHCI) present on TI's AM654 SOCs. It is compatible with eMMC5.1 Host Specifications. Enable only upto HS200 speed mode. Signed-off-by: Faiz Abbas <[email protected]> Acked-by: Nishanth Menon <[email protected]> Signed-off-by: Tero Kristo <[email protected]>
2019-02-01arm64: dts: imx8mq: properly describe IRQ hierarchyLucas Stach1-2/+4
The GPCv2 sits between most of the peripherals and the GIC and functions as a wakeup controller for the CPU cores. Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Fabio Estevam <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-01dt-bindings: fsl: scu: add imx8qm scu clock supportAisheng Dong1-0/+1
Add imx8qm scu clock support Cc: Shawn Guo <[email protected]> Cc: Sascha Hauer <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Michael Turquette <[email protected]> Acked-by: Stephen Boyd <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Dong Aisheng <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-01dt-bindings: fsl: scu: add fallback compatible string for clockAisheng Dong1-2/+4
SCU clock can be used in a similar way by IMX8QXP and IMX8QM SoCs. Let's add a "fsl,scu-clk" fallback compatible string to allow other SoCs to reuse the common part. Cc: Shawn Guo <[email protected]> Cc: Sascha Hauer <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Michael Turquette <[email protected]> Acked-by: Stephen Boyd <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Dong Aisheng <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-01-31ARM: dts: BCM5301X: Add basic DT for Phicomm K3Hao Dong2-0/+72
This router has BCM4709C0 SoC, 128 MiB NAND flash (MX30LF1G18AC-TI), 512 MiB memory and 3 x LAN and 1 x WAN ports. WiFi chips are BCM4366C0 x 2. The router has a small LCD and 3 capactive keys driven by a PIC microcontroller, which is in turn wired to UART1 of main board. Signed-off-by: Hao Dong <[email protected]> [rmilecki: drop chosen { }, fix whitespaces, update commit message] Signed-off-by: Rafał Miłecki <[email protected]> Signed-off-by: Florian Fainelli <[email protected]>
2019-02-01arm64: dts: lx2160a: update fspi nodeYogesh Narayan Gaur1-0/+4
Flash mt35xu512aba connected to FlexSPI controller supports 1-1-8/1-8-8 protocol. Added flag spi-rx-bus-width and spi-tx-bus-width with values as 8 and 8 respectively for both flashes connected at CS0 and CS1. Signed-off-by: Yogesh Narayan Gaur <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-01arm64: dts: freescale: Add devicetree for OxalisManivannan Sadhasivam2-0/+97
Add devicetree support for Oxalis SoM board from EBS-SYSTART. This board is one of the 96Boards Enterprise Edition platform. Below are some of the key features of this board: * SoC: NXP Layerscape LS1012A * RAM: 1GB DDR3L * PMU: NXP VR5100 * Storage: 64MByte SPI Flash for bootloader and RCW, MicroSD Card, SATA * Connectivity: 2x Ethernet * USB: 2x USB3.0 More information about this board can be found in 96Boards product page: https://www.96boards.org/product/oxalis/ Ethernet and SPI flash are not supported yet! Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-01dt-bindings: arm: fsl: Add devicetree binding for OxalisManivannan Sadhasivam1-0/+1
Add devicetree binding for LS1012A SoC based Oxalis board. Signed-off-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-01dt-bindings: vendor-prefixes: Add EBS-SYSTART GmbH Vendor PrefixManivannan Sadhasivam1-0/+1
Add vendor prefix for EBS-SYSTART GmbH. Signed-off-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-01dt-bindings: arm: fsl: Fix bindings for LS1012A and LS1021A based boardsManivannan Sadhasivam1-1/+9
Fix devicetree bindings for Freescale LS1012A and LS1021A SoC based boards. Fixes: a1a38e1f4d1d ("dt-bindings: arm: Convert FSL board/soc bindings to json-schema") Signed-off-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-02-01arm64: dts: lx2160a: add FlexSPI node propertyYogesh Narayan Gaur2-0/+35
Add fspi node property for LX2160A SoC for FlexSPI driver. Property added for the FlexSPI controller and for the connected slave device for the LX2160ARDB target. This is having two SPI-NOR flash device, mt35xu512aba, connected at CS0 and CS1. Signed-off-by: Yogesh Narayan Gaur <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-01-31arm64: dts: hi3798cv200: fix malformed SPDX license identifierShawn Guo2-6/+2
It fixes malformed SPDX license identifier in Hi3798CV200 and Poplar DTS, accroding to Documentation/process/license-rules.rst. Signed-off-by: Shawn Guo <[email protected]> Signed-off-by: Wei Xu <[email protected]>
2019-01-31arm64: dts: hikey960: fix SDcard detectionVincent Guittot1-2/+1
The SDcard detection of hikey960 is active low so cd-inverted is wrong. Instead of adding cd-inverted, we should better set correctly cd-gpios to use GPIO_ACTIVE_LOW. Signed-off-by: Vincent Guittot <[email protected]> Reviewed-by: Linus Walleij <[email protected]> Signed-off-by: Wei Xu <[email protected]>
2019-01-31arm64: dts: hikey: Add DMA entries for Bluetooth UARTJohn Stultz1-0/+2
Add dma0 references for bluetooth uart to enable dma for bt transfers. Cc: Manivannan Sadhasivam <[email protected]> Cc: Ryan Grachek <[email protected]> Cc: Wei Xu <[email protected]> Cc: Rob Herring <[email protected]> Cc: Mark Rutland <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: John Stultz <[email protected]> Acked-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Wei Xu <[email protected]>
2019-01-30Merge tag 'juno-updates-5.1' of ↵Arnd Bergmann11-167/+488
git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/dt ARMv8 Juno/fast models updates for v5.1 1. Support for Fixed Virtual Platforms(FVP) Base RevC model to enable development of software around the new features available 2. Addition of dynamic-power-coefficient information for CPUs on Juno 3. Miscellaneous changes like re-ordering device nodes, using existing macros for GIC flags in interrupt-maps and using list instead of tuple(which is wrong but works as number of interrupt cells is 1) for mmci interrupts * tag 'juno-updates-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: arm64: dts: juno: Add cpu dynamic-power-coefficient information arm64: dts: fast models: Add DTS fo Base RevC FVP arm64: dts: juno/fast models: sort couple of device nodes arm64: dts: models: use list instead of tuple for mmci interrupts arm64: dts: juno/fast models: using GIC macros instead of hardcoded values Signed-off-by: Arnd Bergmann <[email protected]>
2019-01-30Merge tag 'vexpress-updates-5.1' of ↵Arnd Bergmann4-5/+10
git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/dt ARMv7 Vexpress updates for v5.1 Couple of simple changes to add dynamic-power-coefficient information for CPUs on TC2 and fix tuple used for uart and mmci interrupts with lists. * tag 'vexpress-updates-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: arm: dts: vexpress-v2p-ca15_a7: Add cpu dynamic-power-coefficient information ARM: dts: vexpress: use list instead of tuple for mmci interrupts ARM: dts: mps2: use list instead of tuple for uart interrupts Signed-off-by: Arnd Bergmann <[email protected]>
2019-01-30Merge tag 'aspeed-5.1-devicetree' of ↵Arnd Bergmann7-3/+255
git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed into arm/dt ASPEED device tree updates for 5.1 - New machine: Inspur ON5263M5, an Intel Xeon OCP compute node - Misc device tree updates from the OpenBMC project - #interrupt-cells fix for GPIO controller * tag 'aspeed-5.1-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/aspeed: ARM: dts: aspeed: quanta-q71l: enable uart1 ARM: dts: aspeed: quanta-q71l: enable lpc_ctrl node ARM: dts: aspeed: tiogapass: Add uarts for SoL ARM: dts: aspeed: tiogapass: Add LPC devices ARM: dts: aspeed: Add Inspur on5263m5 BMC ARM: dts: aspeed: tiogapass: Add sensors ARM: dts: aspeed: tiogapass: Enable KCS ARM: dts: aspeed: Add KCS support for LPC BMC ARM: dts: aspeed: Add #interrupt-cells property to gpio controllers ARM: dts: aspeed-palmetto: Add i2c OCC hwmon node ARM: dts: aspeed: stardragon4800: Add power supply Signed-off-by: Arnd Bergmann <[email protected]>
2019-01-30Merge tag 'sunxi-dt64-for-5.1' of ↵Arnd Bergmann2-1/+11
git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt Allwinner DT64 changes for 5.1 A few small improvements for the A64 this cycle: - ARM PMU added - Allwinner ARM architected timer workaround enabled This works around timer value wrapping found in the Allwinner implementation of the ARM architected timer. * tag 'sunxi-dt64-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: arm64: dts: allwinner: a64: Enable A64 timer workaround arm64: dts: allwinner: a64: Fix a typo arm64: dts: allwinner: a64: Add PMU node Signed-off-by: Arnd Bergmann <[email protected]>
2019-01-30Merge tag 'sunxi-dt-for-5.1' of ↵Arnd Bergmann10-172/+379
git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into arm/dt Allwinner DT changes for 5.1 As usual, this is a random assortment of changes: - ARM PMU is enabled on the A10 - The first usage of the PIO pinbank regulator supplies added, for the Bananapi - Broadcom-based Bluetooth enabled on the Bananapi M2 Magic and M2 Ultra, using the serdev bindings - Video codec added for the A10 - Display pipeline for the A23 added and enabled for the generic Q8 tablets * tag 'sunxi-dt-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: ARM: dts: sun8i-a23-q8: Set compatible string for LCD panel ARM: dts: sun8i-q8-common: Enable display pipeline with RGB LCD panel ARM: dts: sun8i-a23: Add compatible strings to display pipeline device nodes ARM: dts: sun8i-a33: Move display pipeline nodes to a23/a33 common dtsi ARM: dts: sun8i-a23-a33: Move NAND controller device node to sort by address ARM: dts: sun4i-a10: Add Video Engine and reserved memory nodes ARM: dts: sun4i: Add support for the C1 SRAM region with the SRAM controller ARM: dts: sunxi: bananapi-m2-plus: Add Bluetooth device node ARM: dts: sun8i: r40: bananapi-m2-ultra: Add Bluetooth device node ARM: dts: sun8i: r40: bananapi-m2-ultra: Fix WiFi regulator definitions ARM: dts: sun8i: r40: Add pinmux setting for CLK_OUT_A ARM: dts: sun8i: r40: Add pinmux settings for UART3 on PG pingroup ARM: dts: sun7i: bananapi: Add GPIO banks regulators ARM: dts: sun4i-a10: Add PMU node Signed-off-by: Arnd Bergmann <[email protected]>
2019-01-30Merge tag 'renesas-arm64-dt-for-v5.1' of ↵Arnd Bergmann11-163/+2107
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into arm/dt Renesas ARM64 Based SoC DT Updates for v5.1 R-Car H3 (r8a7795) SoC - Sort i2c and pciec0 nodes within soc node R-Car H3 (r8a7795) and M3-W (r8a7796) SoCs - Remove BUSIF0 settings from rcar_sound,ssi R-Car M3-W (r8a7796) based Salvator-XS board - Convert to new LVDS DT bindings R-Car H3 (r8a7795), M3-W (r8a7796) and M3-N (r8a77965) based ULCB boards - Use audio-graph-card to allow secondary sound device on kingfisher daugher board - Add HDMI sound support Kingfisher daughterboard for R-Car H3 (r8a7795), M3-W (r8a7796) and M3-N (r8a77965) based ULCB boards - Add pcm3168 sound codec R-Car E3 (r8a77990) SoC - Enable DMA for SCIF2 R-Car E3 (r8a77990) based Ebisu board - HS400 for onboard eMMC - Use simple-audio-card rather than simple-scu-audio-card - Correct EthernetAVB phy mode as rgmii - Add backlight and follow-up to correct duplicate regulator number R-Car V3M (r8a77970) based v3msk starter kit - Specify EtherAVB PHY IRQ now that GPIO support is present R-Car D3 (r8a77995) based draak board - Set better backlight levels RZ/G2M (r8a774a1) SoC - Correct hsusb reg size RZ/G2E (r8a774c0) SoC - Intial SoC DT - Add: and SYS-DMAC controller, SCIF, HSCIF, INTC-EX PFC, GPIO, Ethernet AVB, watchdog, secondary CA3 core, SDHI, I2C, IIC-DVFS, IPMU, CAN, thermal, MSIOF, audio, PWM, display output, USB2.0, USB-DMAC, HSUSB, USB3.0, IPMMU, PCIe, VIN and CSI-2 support - A follow-up patch included in this pull-request enables DMA for SCIF2 so that DMA is enabled for all SCIF nodes * tag 'renesas-arm64-dt-for-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (44 commits) arm64: dts: renesas: r8a77990: ebisu: Enable HS400 of SDHI3 arm64: dts: renesas: r8a77990: Enable DMA for SCIF2 arm64: dts: renesas: r8a774c0: Enable DMA for SCIF2 arm64: dts: renesas: r8a77990: ebisu: Fix backlight regulator numbering arm64: dts: renesas: v3msk: specify EtherAVB PHY IRQ arm64: dts: renesas: r8a77990-ebisu: use simple-audio-card arm64: dts: renesas: r8a7796: remove BUSIF0 settings from rcar_sound,ssi arm64: dts: renesas: r8a7795: remove BUSIF0 settings from rcar_sound,ssi arm64: dts: renesas: ulcb-kf: add pcm3168 sound codec arm64: dts: renesas: ulcb: add HDMI sound support arm64: dts: renesas: ulcb: use audio-graph-card arm64: dts: renesas: r8a7796: salvator-xs: Convert to new LVDS DT bindings arm64: dts: renesas: r8a77990: Sort i2c nodes within soc node arm64: dts: renesas: r8a77990: sort pciec0 node within soc node arm64: dts: renesas: r8a774a1: Fix hsusb reg size arm64: dts: renesas: r8a774c0: Add VIN and CSI-2 device nodes arm64: dts: renesas: r8a774c0: Add PCIe device node arm64: dts: renesas: r8a774c0: Connect RZ/G2E Audio-DMAC to IPMMU arm64: dts: renesas: r8a774c0: Connect RZ/G2E AVB to IPMMU arm64: dts: renesas: r8a774c0: Connect RZ/G2E SYS-DMAC to IPMMU ... Signed-off-by: Arnd Bergmann <[email protected]>
2019-01-30Merge tag 'integrator-dts-v5.1' of ↵Arnd Bergmann1-32/+57
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into arm/dt This updates the Integrator DTS files with the device tree nodes required by the DRM driver. * tag 'integrator-dts-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator: ARM: dts: Augment panel setting for Integrator/CP Signed-off-by: Arnd Bergmann <[email protected]>
2019-01-30Merge tag 'nomadik-dts-v5.1' of ↵Arnd Bergmann1-34/+51
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into arm/dt This add the new display driver and DRM driver device nodes to the Nomadik NHK8815. * tag 'nomadik-dts-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik: ARM: dts: nomadik: Augment NHK15 panel setting Signed-off-by: Arnd Bergmann <[email protected]>
2019-01-30arm64: dts: Remove inconsistent use of 'arm,armv8' compatible stringRob Herring67-427/+427
The 'arm,armv8' compatible string is only for software models. It adds little value otherwise and is inconsistently used as a fallback on some platforms. Remove it from those platforms. This fixes warnings generated by the DT schema. Reported-by: Michal Simek <[email protected]> Cc: Mark Rutland <[email protected]> Cc: Will Deacon <[email protected]> Acked-by: Antoine Tenart <[email protected]> Acked-by: Nishanth Menon <[email protected]> Acked-by: Maxime Ripard <[email protected]> Acked-by: Manivannan Sadhasivam <[email protected]> Acked-by: Chanho Min <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Acked-by: Masahiro Yamada <[email protected]> Acked-by: Gregory CLEMENT <[email protected]> Acked-by: Thierry Reding <[email protected]> Acked-by: Heiko Stuebner <[email protected]> Acked-by: Simon Horman <[email protected]> Acked-by: Tero Kristo <[email protected]> Acked-by: Wei Xu <[email protected]> Acked-by: Liviu Dudau <[email protected]> Acked-by: Matthias Brugger <[email protected]> Acked-by: Michal Simek <[email protected]> Acked-by: Scott Branden <[email protected]> Acked-by: Kevin Hilman <[email protected]> Acked-by: Chunyan Zhang <[email protected]> Acked-by: Robert Richter <[email protected]> Acked-by: Jisheng Zhang <[email protected]> Acked-by: Dinh Nguyen <[email protected]> Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]>
2019-01-30ARM: dts: Kill off skeleton{64}.dtsiRob Herring141-141/+309
Remove the usage of skeleton.dtsi in the remaining dts files. It was deprecated since commit 9c0da3cc61f1 ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"). This will make adding a unit-address to memory nodes easier. The main tricky part to removing skeleton.dtsi is we could end up with no /memory node at all when a bootloader depends on one being present. I hacked up dtc to check for this condition. Acked-by: Linus Walleij <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Matthias Brugger <[email protected]> Acked-by: Viresh Kumar <[email protected]> Acked-by: Alexandre Belloni <[email protected]> Acked-by: Neil Armstrong <[email protected]> Acked-by: Antoine Tenart <[email protected]> Acked-by: Alexandre TORGUE <[email protected]> Acked-by: Robert Jarzmik <[email protected]> Acked-by: Vladimir Zapolskiy <[email protected]> Tested-by: Kevin Hilman <[email protected]> Reviewed-by: Kevin Hilman <[email protected]> Tested-by: Martin Blumenstingl <[email protected]> Reviewed-by: Martin Blumenstingl <[email protected]> Signed-off-by: Rob Herring <[email protected]> Reviewed-by: Gregory CLEMENT <[email protected]> Tested-by: Gregory CLEMENT <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]>
2019-01-30Merge tag 'stm32-dt-for-v4.21-1' of ↵Arnd Bergmann4-3/+114
git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt STM32 DT updates for v4.21, round 1 Highlights: ---------- -MPU STM32MP157 platform update: -Declare DMAs for timers -Add sleep support for CAN -Split CAN RAM mapping between the 2 FDCAN instances -Add support of thermal sensor (DTS) * tag 'stm32-dt-for-v4.21-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32: ARM: dts: stm32: add thermal sensor support on STM32MP157c ARM: dts: stm32: add can1 sleep pins muxing on stm32mp157c-ev1 board ARM: dts: stm32: add can1 sleep pins muxing ARM: dts: stm32: change CAN RAM mapping on stm32mp157c ARM: dts: stm32: don't use timers dmas on stm32mp157c-ev1 ARM: dts: stm32: don't use timers dmas on stm32mp157c-ed1 ARM: dts: stm32: Add dmas to timer on stm32mp157c Signed-off-by: Arnd Bergmann <[email protected]>
2019-01-30ARM: dts: aspeed: quanta-q71l: enable uart1Patrick Venture1-0/+4
Enable the uart1 node such that the clock will be enabled. Signed-off-by: Patrick Venture <[email protected]> Signed-off-by: Joel Stanley <[email protected]>
2019-01-30ARM: dts: aspeed: quanta-q71l: enable lpc_ctrl nodePatrick Venture1-0/+4
Enable the lpc_ctrl node in the quanta-q71l dts such that the LPC_CLK is enabled. Signed-off-by: Patrick Venture <[email protected]> Signed-off-by: Joel Stanley <[email protected]>
2019-01-30ARM: dts: aspeed: tiogapass: Add uarts for SoLVijay Khemka1-0/+10
Added uart2 and uart3 in Facebook Tiogapass for routing serial input from Host to BMC for SoL via LPC. Signed-off-by: Vijay Khemka <[email protected]> Signed-off-by: Joel Stanley <[email protected]>
2019-01-30ARM: dts: aspeed: tiogapass: Add LPC devicesVijay Khemka1-0/+10
Added lpc control for enabling lpc clock and lpc snoop devices to Facebook Tiogapass device tree. Signed-off-by: Vijay Khemka <[email protected]> Signed-off-by: Joel Stanley <[email protected]>
2019-01-29ARM: dts: socfpga: update more missing reset propertiesSimon Goldschmidt1-0/+4
Add reset property for dma, can and sdram on socfpga gen5. Signed-off-by: Simon Goldschmidt <[email protected]> Signed-off-by: Dinh Nguyen <[email protected]>
2019-01-29arm64: dts: juno: Add cpu dynamic-power-coefficient informationDietmar Eggemann2-0/+12
A CPUfreq driver, like the scpi driver used on Juno boards, which provide the Energy Model with power cost information via the PM_OPP of_dev_pm_opp_get_cpu_power() function, do need the dynamic-power-coefficient (C) in the device tree. Method used to obtain the C value: C is computed by measuring energy (E) consumption of a frequency domain (FD) over a 10s runtime (t) sysbench workload running at each Operating Performance Point (OPP) affine to 1 or 2 CPUs of that FD while the other CPUs of the system are hotplugged out. By definition all CPUs of a FD have the the same micro-architecture. An OPP is characterized by a certain frequency (f) and voltage (V) value. The corresponding power values (P) are calculated by dividing the delta of the E values between the runs with 2 and 1 CPUs by t. With n data tuples (P, f, V), n equal to number of OPPs for this frequency domain, we can solve C by: P = Pstat + Pdyn P = Pstat + CV²f Cx = (Px - P1)/(Vx²fx - V1²f1) with x = {2, ..., n} The C value is the arithmetic mean out of {C2, ..., Cn}. Since DVFS is broken on Juno r1, no dynamic-power-coefficient information has been added to its dts file. Signed-off-by: Dietmar Eggemann <[email protected]> Signed-off-by: Quentin Perret <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2019-01-29arm: dts: vexpress-v2p-ca15_a7: Add cpu dynamic-power-coefficient informationDietmar Eggemann1-0/+5
A CPUfreq driver, like the ARM big.LITTLE driver used on the TC2 board, which provide the Energy Model with power cost information via the PM_OPP of_dev_pm_opp_get_cpu_power() function, do need the dynamic-power-coefficient (C) in the device tree. Method used to obtain the C value: C is computed by measuring energy (E) consumption of a frequency domain (FD) over a 10s runtime (t) sysbench workload running at each Operating Performance Point (OPP) affine to 1 or 2 CPUs of that FD while the other CPUs of the system are hotplugged out. By definition all CPUs of a FD have the the same micro-architecture. An OPP is characterized by a certain frequency (f) and voltage (V) value. The corresponding power values (P) are calculated by dividing the delta of the E values between the runs with 2 and 1 CPUs by t. With n data tuples (P, f, V), n equal to number of OPPs for this frequency domain, we can solve C by: P = Pstat + Pdyn P = Pstat + CV²f Cx = (Px - P1)/(Vx²fx - V1²f1) with x = {2, ..., n} The C value is the arithmetic mean out of {C2, ..., Cn}. Signed-off-by: Dietmar Eggemann <[email protected]> Signed-off-by: Quentin Perret <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2019-01-29arm64: dts: fast models: Add DTS fo Base RevC FVPJean-Philippe Brucker3-0/+305
Fixed Virtual Platforms(FVP) Base RevC model is an emulated Arm platform with GICv3, PCIe, SMMUv3 and various other features. These are available free of charge on the Arm Community website at Arm Development Platforms[1]. It resembles the Foundation Platform, which is a simple FVP that includes an Armv8‑A AEM processor model but this has two cluster of four cores, a CCI-550 interconnect, an SMMU and two PCI devices. In order to enable development of software, let's add a description of the Revison C version of Base platform. The documentation for this FVP model is available @[2] for reference. [1] https://community.arm.com/dev-platforms/ [2] https://static.docs.arm.com/100966/1104/fast_models_fvp_rg_100966_1104_00_en.pdf Cc: Vincent Stehlé <[email protected]> Acked-by: Liviu Dudau <[email protected]> Signed-off-by: Jean-Philippe Brucker <[email protected]> [sudeep.holla: aligned interrupt-map with other DTS, added SPE, changed PMU to use GIC PPI, moved to PSCI v0.2, commit log rewording] Signed-off-by: Sudeep Holla <[email protected]>
2019-01-29arm64: dts: juno/fast models: sort couple of device nodesSudeep Holla2-41/+41
Sort the couple device nodes with unit addresses which are out of order. Acked-by: Liviu Dudau <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2019-01-29arm64: dts: models: use list instead of tuple for mmci interruptsSudeep Holla1-1/+1
RTSM/FVP vexpress motherboard model MMCI requires dedicated interrupts for CMD and PIO, which obviously should be expressed as a list. Current form uses tuple and it works fine since interrupt-cells equal to 1. Acked-by: Liviu Dudau <[email protected]> Reported-by: Vladimir Murzin <[email protected]> Reviewed-by: Vladimir Murzin <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2019-01-29arm64: dts: juno/fast models: using GIC macros instead of hardcoded valuesSudeep Holla5-125/+129
There are macros that exist to indicate the GIC specific flags and custom cell values as per the GIC DT bindings. It's used in most of the places in these DTS files but not all. To maintain consistency, lets use the macros at all the places. Since DTC doesn't even warn is any cells are missing, it's very hard to debug if that's the case. Changing to use macros avoids missing cells/ columns. Acked-by: Liviu Dudau <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2019-01-29arm64: dts: allwinner: h6: Add support for the SRAM C1 sectionJernej Skrabec1-0/+14
Add a node for H6 SRAM C1 section. Manual calls it VE SRAM, but for consistency with older SoCs, SRAM C1 name is used. Signed-off-by: Jernej Skrabec <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2019-01-29dt-bindings: sram: sunxi: Add compatible for the H6 SRAM C1Jernej Skrabec1-0/+1
This introduces a new compatible for the H6 SRAM C1 section, that is compatible with the SRAM C1 section as found on the A10. Signed-off-by: Jernej Skrabec <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2019-01-28arm64: dts: allwinner: a64: Add A64 CSI controllerJagan Teki1-0/+20
Add dts node details for Allwinner A64 CSI controller. A64 CSI has similar features as like in H3, but the CSI_SCLK need to update it to 300MHz than default clock rate. Signed-off-by: Jagan Teki <[email protected]> Acked-by: Maxime Ripard <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2019-01-28ARM: dts: sun5i: q8-tablet: Use bananapi,s070wv20-ct16 panel compatibleChen-Yu Tsai1-1/+1
The compatible string for the LCD panel used for the Q8 tablets are just a placeholder that was shown to be compatible with the actual panels found on these devices. The real panels do not have any identifiable markings and vary between production runs. The compatibe string previously used had a pixel clock that could not be accurately reproduced on Allwinner hardware, and discussions on whether a margin should be added to the display drivers and how large a margin was acceptable had stalled. Now that we have a panel model that is actually used with Allwinner hardware, has the same dimensions, and the timings have been shown to work with the nameless panels, we can use that one instead. Signed-off-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
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