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2018-10-18Merge branches 'clk-tegra' and 'clk-bulk-get-all' into clk-nextStephen Boyd5-6/+178
- Nvidia Tegra clk driver MBIST workaround fix - clk_bulk_get_all() API and friends to get all the clks for a device * clk-tegra: clk: tegra210: Include size.h for compilation ease clk: tegra: Fixes for MBIST work around clk: tegra: probe deferral error reporting * clk-bulk-get-all: clk: add managed version of clk_bulk_get_all clk: add new APIs to operate on all available clocks clk: bulk: add of_clk_bulk_get()
2018-10-18Merge branch 'clk-ingenic-jz4725b' into clk-nextStephen Boyd7-7/+319
- Ingenic jz4725b CGU * clk-ingenic-jz4725b: clk: Add Ingenic jz4725b CGU driver dt-bindings: clock: Add jz4725b-cgu.h header dt-bindings: clock: ingenic: Explicitly list compatible strings clk: ingenic: Add proper Kconfig entries
2018-10-18Merge branch 'clk-qcom-qcs404' into clk-nextStephen Boyd6-0/+2920
- Qualcomm QCS404 GCC support * clk-qcom-qcs404: clk: qcom: gcc: Add global clock controller driver for QCS404 clk: qcom: Export clk_alpha_pll_configure()
2018-10-18Merge branch 'clk-qcom-sdm660' into clk-nextStephen Boyd5-0/+2648
- Qualcomm SDM660 GCC support * clk-qcom-sdm660: clk: qcom: gcc-sdm660: Add MODULE_LICENSE clk: qcom: Add Global Clock controller (GCC) driver for SDM660
2018-10-18Merge branches 'clk-samsung', 'clk-hisi3670' and 'clk-at91-div-0' into clk-nextStephen Boyd32-641/+1538
- Hisilicon 3670 SoC support * clk-samsung: dt-bindings: clock: samsung: Add SPDX license identifiers clk: samsung: Use clk_hw API for calling clk framework from clk notifiers clk: samsung: exynos5420: Enable PERIS clocks for suspend clk: samsung: exynos5420: Define CLK_SECKEY gate clock only or Exynos5420 clk: samsung: exynos5433: Keep sclk_uart clocks enabled in suspend clk: samsung: Remove obsolete code for Exynos4412 ISP clocks clk: samsung: exynos5433: Add suspend state for TOP, CPIF & PERIC CMUs clk: samsung: Use NOIRQ stage for Exynos5433 clocks suspend/resume clk: samsung: exynos5420: Use generic helper for handling suspend/resume clk: samsung: exynos4: Use generic helper for handling suspend/resume clk: samsung: Add support for setting registers state before suspend clk: samsung: exynos5250: Use generic helper for handling suspend/resume clk: samsung: s5pv210: Use generic helper for handling suspend/resume clk: samsung: s3c64xx: Use generic helper for handling suspend/resume clk: samsung: s3c2443: Use generic helper for handling suspend/resume clk: samsung: s3c2412: Use generic helper for handling suspend/resume clk: samsung: s3c2410: Use generic helper for handling suspend/resume clk: samsung: Remove excessive include * clk-hisi3670: clk: hisilicon: Add clock driver for Hi3670 SoC dt-bindings: clk: hisilicon: Add bindings for Hi3670 clk * clk-at91-div-0: clk: at91: Fix division by zero in PLL recalc_rate()
2018-10-18Merge branch 'clk-ti' into clk-nextStephen Boyd22-548/+2826
* clk-ti: clk: ti: Prepare for remove of OF node name clk: Clean up suspend/resume coding style clk: ti: Add functions to save/restore clk context clk: clk: Add clk_gate_restore_context function clk: Add functions to save/restore clock context en-masse clk: ti: dra7: add new clkctrl data clk: ti: dra7xx: rename existing clkctrl data as compat data clk: ti: am43xx: add new clkctrl data for am43xx clk: ti: am43xx: rename existing clkctrl data as compat data clk: ti: am33xx: add new clkctrl data for am33xx clk: ti: am33xx: rename existing clkctrl data as compat data clk: ti: clkctrl: replace dashes from clkdm name with underscore clk: ti: clkctrl: support multiple clkctrl nodes under a cm node dt-bindings: clock: dra7xx: add clkctrl indices for new data layout dt-bindings: clock: am43xx: add clkctrl indices for new data layout dt-bindings: clock: am33xx: add clkctrl indices for new data layout
2018-10-18Merge branch 'clk-k3-tisci' into clk-nextStephen Boyd4-1/+12
- TI SCI clks on K3 SoCs * clk-k3-tisci: clk: keystone: add missing MODULE_LICENSE clk: keystone: Enable TISCI clocks if K3_ARCH
2018-10-18Merge branches 'clk-mvebu-periph-pm', 'clk-meson', 'clk-allwinner', ↵Stephen Boyd24-761/+926
'clk-mvebu-dup' and 'clk-davinci' into clk-next - S2RAM support for Marvell mvebu periph clks * clk-mvebu-periph-pm: clk: mvebu: armada-37xx-periph: add suspend/resume support clk: mvebu: armada-37xx-periph: save the IP base address in the driver data * clk-meson: clk: meson: meson8b: use the regmap in the internal reset controller clk: meson: meson8b: register the clock controller early clk: meson-axg: pcie: drop the mpll3 clock parent clk: meson: axg: round audio system master clocks down clk: meson: clk-pll: drop hard-coded rates from pll tables clk: meson: clk-pll: remove od parameters clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary clk: meson: clk-pll: add enable bit * clk-allwinner: dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO0 macro clk: sunxi-ng: a64: Add max. rate constraint to video PLLs clk: sunxi-ng: a64: Add minimal rate for video PLLs clk: sunxi-ng: sun50i: h6: Add 2x fixed post-divider to MMC module clocks clk: sunxi-ng: a83t: Add max. rate constraint to video PLLs clk: sunxi-ng: nkmp: Add constraint for maximum rate clk: sunxi-ng: r40: Add max. rate constraint to video PLLs clk: sunxi-ng: h3/h5: Add max. rate constraint to pll-video clk: sunxi-ng: Add maximum rate constraint to NM PLLs clk: sunxi-ng: h6: fix PWM gate/reset offset clk: sunxi-ng: h6: fix bus clocks' divider position * clk-mvebu-dup: clk: mvebu: ap806: Remove superfluous of_clk_add_provider * clk-davinci: clk: davinci: kill davinci_clk_reset_assert/deassert()
2018-10-18Merge branches 'clk-qcom-sdm845-camcc' and 'clk-mtk-unused' into clk-nextStephen Boyd6-5/+1888
- Qualcomm SDM845 camera clock controller * clk-qcom-sdm845-camcc: clk: qcom: Add camera clock controller driver for SDM845 dt-bindings: clock: Introduce QCOM Camera clock bindings * clk-mtk-unused: clk: mediatek: remove unused array audio_parents
2018-10-18Merge branch 'clk-renesas' into clk-nextStephen Boyd38-267/+1551
* clk-renesas: (36 commits) clk: renesas: r7s9210: Add SPI clocks clk: renesas: r7s9210: Move table update to separate function clk: renesas: r7s9210: Convert some clocks to early clk: renesas: cpg-mssr: Add early clock support clk: renesas: r8a77970: Add TPU clock clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment dt-bindings: clock: renesas: cpg-mssr: Document r8a774c0 clk: renesas: cpg-mssr: Add r8a774c0 support clk: renesas: Add r8a774c0 CPG Core Clock Definitions clk: renesas: r8a7743: Add r8a7744 support clk: renesas: Add r8a7744 CPG Core Clock Definitions dt-bindings: clock: renesas: cpg-mssr: Document r8a7744 binding dt-bindings: clock: renesas: Convert to SPDX identifiers clk: renesas: cpg-mssr: Add R7S9210 support clk: renesas: r8a77970: Add TMU clocks clk: renesas: r8a77970: Add CMT clocks clk: renesas: r9a06g032: Fix UART34567 clock rate clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI clk: renesas: r8a77980: Add CMT clocks clk: renesas: r8a77990: Add missing I2C7 clock ...
2018-10-18Merge branches 'clk-dt-name', 'clk-ti-of-node' and 'clk-sa' into clk-nextStephen Boyd50-162/+166
- Use updated printk format for OF node names - Fix TI code to only search DT subnodes - Various static analysis finds * clk-dt-name: clk: Convert to using %pOFn instead of device_node.name * clk-ti-of-node: clk: ti: fix OF child-node lookup * clk-sa: clk: mvebu: armada-37xx-tbg: Switch to clk_get and balance it in probe reset: hisilicon: fix potential NULL pointer dereference clk: cdce925: release child device nodes clk: qcom: clk-branch: Use true and false for boolean values
2018-10-18Merge branches 'clk-spdx', 'clk-qcom-dfs', 'clk-smp2s11-include', ↵Stephen Boyd7-102/+580
'clk-qcom-8996-missing' and 'clk-qcom-qspi' into clk-next - Tag various drivers with SPDX license tags - Support dynamic frequency switching (DFS) on qcom SDM845 GCC - Only use s2mps11 dt-binding defines instead of redefining them in the driver - Add some more missing clks to qcom MSM8996 GCC - Quad SPI clks on qcom SDM845 * clk-spdx: clk: mvebu: use SPDX-License-Identifier clk: renesas: Convert to SPDX identifiers clk: renesas: use SPDX identifier for Renesas drivers clk: s2mps11,s3c64xx: Add SPDX license identifiers clk: max77686: Add SPDX license identifiers * clk-qcom-dfs: clk: qcom: Allocate space for NULL terimation in DFS table clk: qcom: gcc: Register QUPv3 RCGs for DFS on SDM845 clk: qcom: Add support for RCG to register for DFS * clk-smp2s11-include: clk: s2mps11: Use existing defines from bindings for clock IDs * clk-qcom-8996-missing: clk: qcom: Add some missing gcc clks for msm8996 * clk-qcom-qspi: clk: qcom: Add qspi (Quad SPI) clocks for sdm845 clk: qcom: Add qspi (Quad SPI) clock defines for sdm845 to header
2018-10-18clk: qcom: gcc-sdm660: Add MODULE_LICENSEStephen Boyd1-0/+1
Add a module license to match the license at the top of this file and silence a build warning. Reported-by: Stephen Rothwell <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16clk: mvebu: armada-37xx-tbg: Switch to clk_get and balance it in probeGregory CLEMENT1-1/+2
The parent clock is get only to have its name, and then the clock is no more used, so we can safely free it using clk_put. Furthermore as between the successful devm_clk_get() and the devm_clk_put() call we don't exit the probe function in error so I can use non managed version of clk_get() and clk_put(). Signed-off-by: Gregory CLEMENT <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16clk: add managed version of clk_bulk_get_allDong Aisheng2-0/+47
This patch introduces the managed version of clk_bulk_get_all. Cc: Michael Turquette <[email protected]> Cc: Stephen Boyd <[email protected]> Tested-by: Thor Thayer <[email protected]> Signed-off-by: Dong Aisheng <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16clk: add new APIs to operate on all available clocksDong Aisheng2-1/+92
This patch introduces of_clk_bulk_get_all and clk_bulk_x_all APIs to users who just want to handle all available clocks from device tree without need to know the detailed clock information likes clock numbers and names. This is useful in writing some generic drivers to handle clock part. Cc: Stephen Boyd <[email protected]> Cc: Masahiro Yamada <[email protected]> Tested-by: Thor Thayer <[email protected]> Signed-off-by: Dong Aisheng <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16clk: bulk: add of_clk_bulk_get()Dong Aisheng1-0/+29
'clock-names' property is optional in DT, so of_clk_bulk_get() is introduced here to handle this for DT users without 'clock-names' specified. Later clk_bulk_get_all() will be implemented on top of it and this API will be kept private until someone proves they need it because they don't have a struct device pointer. Cc: Stephen Boyd <[email protected]> Cc: Michael Turquette <[email protected]> Cc: Russell King <[email protected]> Reported-by: Shawn Guo <[email protected]> Tested-by: Thor Thayer <[email protected]> Signed-off-by: Dong Aisheng <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16clk: tegra210: Include size.h for compilation easeStephen Boyd1-0/+1
You can't compile this file by itself because it uses SZ_64K from sizes.h but doesn't include it. Instead it relies on some certain configuration pulling that in implicitly somewhere else. Just add the include to make random compile testing easier. Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16clk: tegra: Fixes for MBIST work aroundJoseph Lo1-3/+3
Fix some incorrect data in LVL2 offset and bit mask. Fixes: e403d0057343 ("clk: tegra: MBIST work around for Tegra210") Signed-off-by: Joseph Lo <[email protected]> Signed-off-by: Peter De Schrijver <[email protected]> Acked-by: Jon Hunter <[email protected]> Acked-by: Peter De Schrijver <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16clk: tegra: probe deferral error reportingMarcel Ziswiler1-2/+6
Actually report the error code from devm_regulator_get() which may as well just be a probe deferral. Signed-off-by: Marcel Ziswiler <[email protected]> Reviewed-by: Stefan Agner <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16clk: Add Ingenic jz4725b CGU driverPaul Cercueil3-0/+236
Add support for the clocks provided by the CGU in the Ingenic JZ4725B SoC. Signed-off-by: Paul Cercueil <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16dt-bindings: clock: Add jz4725b-cgu.h headerPaul Cercueil1-0/+35
This will be used from the devicetree bindings to specify the clocks that should be obtained from the jz4725b-cgu driver. Signed-off-by: Paul Cercueil <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16dt-bindings: clock: ingenic: Explicitly list compatible stringsPaul Cercueil1-2/+5
This is better than letting the other developers wondering what are the supported strings. Signed-off-by: Paul Cercueil <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16clk: ingenic: Add proper Kconfig entriesPaul Cercueil4-5/+43
Previously, the CGU code corresponding to the SoC for which we're compiling the kernel was the only one enabled, which made it impossible to build one kernel that supports them all. Now, it is possible to select more than one SoC to support. Signed-off-by: Paul Cercueil <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16clk: qcom: gcc: Add global clock controller driver for QCS404Shefali Jain5-0/+2919
Add the clocks supported in global clock controller which clock the peripherals like BLSPs, SDCC, USB, MDSS etc. Register all the clocks to the clock framework for the clients to be able to request for them. Signed-off-by: Shefali Jain <[email protected]> Signed-off-by: Taniya Das <[email protected]> Co-developed-by: Taniya Das <[email protected]> Signed-off-by: Anu Ramanathan <[email protected]> [bamse, vkoul: rebase and tidyup for upstream] Signed-off-by: Bjorn Andersson <[email protected]> Signed-off-by: Vinod Koul <[email protected]> Acked-by: Rob Herring <[email protected]> [[email protected]: Lowercase hex] Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16clk: qcom: Export clk_alpha_pll_configure()Bjorn Andersson1-0/+1
This is used by the QCS404 GCC driver, export it to allow that driver to be compiled as a module.. Signed-off-by: Bjorn Andersson <[email protected]> Signed-off-by: Vinod Koul <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16clk: qcom: Add Global Clock controller (GCC) driver for SDM660Taniya Das5-0/+2647
Add support for the global clock controller found on SDM660 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Based on CAF implementation. Signed-off-by: Taniya Das <[email protected]> [craig: rename parents to fit upstream, and other cleanups] Signed-off-by: Craig Tatlor <[email protected]> Acked-by: Rob Herring <[email protected]> [[email protected]: Rename gcc_660 to gcc_sdm660 and fix numbering of defines to avoid duplicates] Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16clk: at91: Fix division by zero in PLL recalc_rate()Ronald Wahl1-0/+3
Commit a982e45dc150 ("clk: at91: PLL recalc_rate() now using cached MUL and DIV values") removed a check that prevents a division by zero. This now causes a stacktrace when booting the kernel on a at91 platform if the PLL DIV register contains zero. This commit reintroduces this check. Fixes: a982e45dc150 ("clk: at91: PLL recalc_rate() now using cached...") Cc: <[email protected]> Signed-off-by: Ronald Wahl <[email protected]> Acked-by: Ludovic Desroches <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16clk: hisilicon: Add clock driver for Hi3670 SoCManivannan Sadhasivam3-0/+1024
Add clock driver for HiSilicon Hi3670 SoC utilizing HiSilicon's common clk code. Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16dt-bindings: clk: hisilicon: Add bindings for Hi3670 clkManivannan Sadhasivam2-0/+391
Add devicetree bindings for HiSilicon Hi3670 clock controller. Signed-off-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16clk: ti: Prepare for remove of OF node nameStephen Boyd1-6/+3
Another patch is going to change this code to use %pOFn for DT node names. Fix up the code to make this easy to pick this side of the merge instead of fixing it up in a merge commit later. Cc: Tero Kristo <[email protected]> Cc: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-15Merge tag 'clk-v4.20-samsung' of ↵Stephen Boyd26-641/+120
git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-samsung Pull Samsung clk driver updates from Sylwester Nawrocki: - consolidation of system suspend related code in Exynos, S5P, S3C SoC clk drivers, - fixes of system suspend support on Exynos542x (Odroid boards) and Exynos5433 SoC, - removal of obsoleted Exynos4212 ISP clock definitions, - correction of Exynos CPU clock implementation, - addition of SPDX license identifiers. * tag 'clk-v4.20-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk: dt-bindings: clock: samsung: Add SPDX license identifiers clk: samsung: Use clk_hw API for calling clk framework from clk notifiers clk: samsung: exynos5420: Enable PERIS clocks for suspend clk: samsung: exynos5420: Define CLK_SECKEY gate clock only or Exynos5420 clk: samsung: exynos5433: Keep sclk_uart clocks enabled in suspend clk: samsung: Remove obsolete code for Exynos4412 ISP clocks clk: samsung: exynos5433: Add suspend state for TOP, CPIF & PERIC CMUs clk: samsung: Use NOIRQ stage for Exynos5433 clocks suspend/resume clk: samsung: exynos5420: Use generic helper for handling suspend/resume clk: samsung: exynos4: Use generic helper for handling suspend/resume clk: samsung: Add support for setting registers state before suspend clk: samsung: exynos5250: Use generic helper for handling suspend/resume clk: samsung: s5pv210: Use generic helper for handling suspend/resume clk: samsung: s3c64xx: Use generic helper for handling suspend/resume clk: samsung: s3c2443: Use generic helper for handling suspend/resume clk: samsung: s3c2412: Use generic helper for handling suspend/resume clk: samsung: s3c2410: Use generic helper for handling suspend/resume clk: samsung: Remove excessive include
2018-10-11clk: Clean up suspend/resume coding styleStephen Boyd1-20/+22
The normal style is to use 'core' for struct clk_core pointers and to directly access the core pointer from the clk_hw pointer when we're within the common clk framework. Update the patches to make it a bit easier to handle. Signed-off-by: Stephen Boyd <[email protected]>
2018-10-11Merge tag 'clk-ti-for-4.20' of ↵Stephen Boyd22-553/+2835
git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into clk-ti Pull TI clock driver updates from Tero Kristo: This tag adds changes for the Texas Instruments clock driver. Included changes are: - clkctrl driver changes switching the layout from CM based to clockdomain based. Needed for ongoing hwmod transition towards sysc driver. Changed SoCs for this include am3,am4,am5,dra7. - RTC+DDR sleep mode support code for clock save/restore. The deep sleep states will wipe the clock register space on the SoC, requiring save/ restore support so that the state can be retained over the sleep state. * tag 'clk-ti-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux: clk: ti: Add functions to save/restore clk context clk: clk: Add clk_gate_restore_context function clk: Add functions to save/restore clock context en-masse clk: ti: dra7: add new clkctrl data clk: ti: dra7xx: rename existing clkctrl data as compat data clk: ti: am43xx: add new clkctrl data for am43xx clk: ti: am43xx: rename existing clkctrl data as compat data clk: ti: am33xx: add new clkctrl data for am33xx clk: ti: am33xx: rename existing clkctrl data as compat data clk: ti: clkctrl: replace dashes from clkdm name with underscore clk: ti: clkctrl: support multiple clkctrl nodes under a cm node dt-bindings: clock: dra7xx: add clkctrl indices for new data layout dt-bindings: clock: am43xx: add clkctrl indices for new data layout dt-bindings: clock: am33xx: add clkctrl indices for new data layout clk: ti: fix OF child-node lookup
2018-10-07clk: keystone: add missing MODULE_LICENSEArnd Bergmann2-0/+10
A randconfig build showed that two clk modules have no license tag: WARNING: modpost: missing MODULE_LICENSE() in drivers/clk/keystone/gate.o see include/linux/module.h for more information WARNING: modpost: missing MODULE_LICENSE() in drivers/clk/keystone/pll.o see include/linux/module.h for more information Add the appropriate information from the comment at the start of the two files. Signed-off-by: Arnd Bergmann <[email protected]> Acked-by: Santosh Shilimkar <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-05dt-bindings: clock: samsung: Add SPDX license identifiersKrzysztof Kozlowski11-50/+17
Replace GPL license statements with SPDX license identifiers (GPL-2.0). Signed-off-by: Krzysztof Kozlowski <[email protected]> Acked-by: Chanwoo Choi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
2018-10-05clk: samsung: Use clk_hw API for calling clk framework from clk notifiersMarek Szyprowski2-4/+4
clk_notifier_register() documentation states, that the provided notifier callbacks associated with the notifier must not re-enter into the clk framework by calling any top-level clk APIs. Fix this by replacing clk_get_rate() calls with clk_hw_get_rate(), which is safe in this context. Signed-off-by: Marek Szyprowski <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
2018-10-05clk: samsung: exynos5420: Enable PERIS clocks for suspendMarek Szyprowski1-0/+1
Ensure that clocks for core SoC modules (including TZPC0..9 modules) are enabled for suspend/resume cycle. This fixes suspend/resume support on Exynos5422-based Odroid XU3/XU4 boards. Suggested-by: Joonyoung Shim <[email protected]> Signed-off-by: Marek Szyprowski <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
2018-10-05clk: samsung: exynos5420: Define CLK_SECKEY gate clock only or Exynos5420Joonyoung Shim1-2/+1
The bit of GATE_BUS_PERIS1 for CLK_SECKEY is just reserved on exynos5422/5800, not exynos5420. Define gate clk for exynos5420 to handle the bit only on exynos5420. Signed-off-by: Joonyoung Shim <[email protected]> [m.szyprow: rewrote commit subject] Signed-off-by: Marek Szyprowski <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
2018-10-05clk: samsung: exynos5433: Keep sclk_uart clocks enabled in suspendMarek Szyprowski1-0/+2
All sclk_uart clocks in TOP CMU have to be kept enabled for suspend/resume cycle, otherwise TM2(e) boards hangs before entering the suspend mode. Signed-off-by: Marek Szyprowski <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
2018-10-05clk: samsung: Remove obsolete code for Exynos4412 ISP clocksMarek Szyprowski2-111/+0
Exynos4412 ISP clock are provided by separate Exynos4412 ISP clock driver, so support for them in Exynos4-clk driver can be removed. Signed-off-by: Marek Szyprowski <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
2018-10-05clk: samsung: exynos5433: Add suspend state for TOP, CPIF & PERIC CMUsMarek Szyprowski1-0/+29
Before entering system suspend, one has to ensure that some clocks from TOP, CPIF and PERIC CMUs are enabled. This is needed by the firmware to properly perform system suspend operation. Instead of adding more and more clocks with CRITICAL flag, simply enable those clocks directly in respective CMU registers using 'suspend_regs' feature. Signed-off-by: Marek Szyprowski <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
2018-10-05clk: samsung: Use NOIRQ stage for Exynos5433 clocks suspend/resumeMarek Szyprowski1-1/+1
SoC clock drivers should suspend after every other drivers in the system, which are using clocks and resume before them. The last stage for calling suspend device callbacks is NOIRQ stage and there exists driver, which use that state (dwmmc-exynos), so Exynos5433 clocks driver should also use it. During the same stage, clocks driver will be always suspended after its clients as a direct result of proper device probe order (deferred probe reorders the suspend call sequence). Signed-off-by: Marek Szyprowski <[email protected]> Acked-by: Chanwoo Choi <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
2018-10-05clk: samsung: exynos5420: Use generic helper for handling suspend/resumeMarek Szyprowski1-66/+6
Replace common suspend/resume handling code by generic helper. Almost no functional change, the only difference is in handling of hypothetical memory allocation failure on boot. Signed-off-by: Marek Szyprowski <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
2018-10-05clk: samsung: exynos4: Use generic helper for handling suspend/resumeMarek Szyprowski1-131/+14
Replace common suspend/resume handling code by generic helper. Handling of PLLs is a bit different in generic code, as they are handled in the same way as other clock registers. Such approach was already used on later Exynos SoCs and worked fine. Tests have shown that it works also on Exynos4 SoCs and significantly simplifies the code. Signed-off-by: Marek Szyprowski <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
2018-10-05clk: samsung: Add support for setting registers state before suspendMarek Szyprowski2-12/+29
Some registers of clock controller have to be set to certain values before entering system suspend state. Till now drivers did that on their own, but it will be easier to handle it by generic code and let drivers simply to provide the list of registers and their state. Signed-off-by: Marek Szyprowski <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
2018-10-05clk: samsung: exynos5250: Use generic helper for handling suspend/resumeMarek Szyprowski1-40/+2
Replace common suspend/resume handling code by generic helper. Almost no functional change, the only difference is in handling of hypothetical memory allocation failure on boot. Signed-off-by: Marek Szyprowski <[email protected]> Acked-by: Chanwoo Choi <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
2018-10-05clk: samsung: s5pv210: Use generic helper for handling suspend/resumeMarek Szyprowski1-39/+2
Replace common suspend/resume handling code by generic helper. Almost no functional change, the only difference is in handling of hypothetical memory allocation failure on boot. Signed-off-by: Marek Szyprowski <[email protected]> Acked-by: Chanwoo Choi <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
2018-10-05clk: samsung: s3c64xx: Use generic helper for handling suspend/resumeMarek Szyprowski1-60/+6
Replace common suspend/resume handling code by generic helper. Almost no functional change, the only difference is in handling of hypothetical memory allocation failure on boot. [[email protected]: Whitespace correction] Signed-off-by: Marek Szyprowski <[email protected]> Acked-by: Chanwoo Choi <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
2018-10-03clk: ti: Add functions to save/restore clk contextRuss Dill7-0/+206
SoCs like AM43XX lose clock registers context during RTC-only suspend. Hence add functions to save/restore the clock registers context. Signed-off-by: Keerthy <[email protected]> Signed-off-by: Russ Dill <[email protected]> Acked-by: Tony Lindgren <[email protected]> Signed-off-by: Tero Kristo <[email protected]>
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