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2018-10-03clk: clk: Add clk_gate_restore_context functionKeerthy2-0/+21
The clock gate restore context function enables or disables the gate clocks based on the enable_count. This is done in cases where the clock context is lost and based on the enable_count the clock either needs to be enabled/disabled. Signed-off-by: Keerthy <[email protected]> Acked-by: Tony Lindgren <[email protected]> Signed-off-by: Tero Kristo <[email protected]>
2018-10-03clk: Add functions to save/restore clock context en-masseRuss Dill3-0/+106
Deep enough power saving mode can result into losing context of the clock registers also, and they need to be restored once coming back from the power saving mode. Hence add functions to save/restore clock context. Signed-off-by: Keerthy <[email protected]> Signed-off-by: Russ Dill <[email protected]> Acked-by: Tony Lindgren <[email protected]> Signed-off-by: Tero Kristo <[email protected]>
2018-10-03clk: ti: dra7: add new clkctrl dataTero Kristo3-3/+874
The new clkctrl data layout for dra7xx is split based on clockdomain boundaries. Previously the split was based on CM boundaries. This patch adds the new data as separate data entity, retaining the compatibility data also for now. The compatibility data can be removed once no longer needed. Signed-off-by: Tero Kristo <[email protected]> Tested-by: Tony Lindgren <[email protected]>
2018-10-03clk: ti: dra7xx: rename existing clkctrl data as compat dataTero Kristo5-804/+829
Rename the existing clkctrl data in preparation of upcoming clkdm based split for it. Once the DT data has transitioned also, the compat data can be removed. Signed-off-by: Tero Kristo <[email protected]> Tested-by: Tony Lindgren <[email protected]>
2018-10-03clk: ti: am43xx: add new clkctrl data for am43xxTero Kristo3-5/+268
The new clkctrl data layout for am43xx is split based on clockdomain boundaries. Previously the split was based on CM boundaries. This patch adds the new data as separate data entity, retaining the compatibility data also for now. The compatibility data can be removed once no longer needed. Signed-off-by: Tero Kristo <[email protected]> Tested-by: Tony Lindgren <[email protected]>
2018-10-03clk: ti: am43xx: rename existing clkctrl data as compat dataTero Kristo5-207/+233
Rename the existing clkctrl data in preparation of upcoming clkdm based split for it. Once the DT data has transitioned also, the compat data can be removed. Signed-off-by: Tero Kristo <[email protected]> Tested-by: Tony Lindgren <[email protected]>
2018-10-03clk: ti: am33xx: add new clkctrl data for am33xxTero Kristo3-3/+250
The new clkctrl data layout for am33xx is split based on clockdomain boundaries. Previously the split was based on CM boundaries. This patch adds the new data as separate data entity, retaining the compatibility data also for now. The compatibility data can be removed once no longer needed. Signed-off-by: Tero Kristo <[email protected]> Tested-by: Tony Lindgren <[email protected]>
2018-10-03clk: ti: am33xx: rename existing clkctrl data as compat dataTero Kristo5-198/+224
Rename the existing clkctrl data in preparation of upcoming clkdm based split for it. Once the DT data has transitioned also, the compat data can be removed. Signed-off-by: Tero Kristo <[email protected]> Tested-by: Tony Lindgren <[email protected]>
2018-10-03clk: ti: clkctrl: replace dashes from clkdm name with underscoreTero Kristo1-0/+10
The change in the DTS data node naming prevents using underscore within the node names and force usage of dash instead. On the other hand, clockdomains use underscore instead of dash, so this must be replaced within the driver code so that the mapping between the two can be done properly. Signed-off-by: Tero Kristo <[email protected]> Tested-by: Tony Lindgren <[email protected]>
2018-10-03clk: ti: clkctrl: support multiple clkctrl nodes under a cm nodeTero Kristo4-18/+53
Currently, only one clkctrl node can be added under a specific CM node due to limitation with the implementation. Modify the code to pick-up clockdomain name from the clkctrl node instead of CM node if provided. Also, add a new flag to the TI clock driver so that both modes can be supported simultaneously. Signed-off-by: Tero Kristo <[email protected]> Tested-by: Tony Lindgren <[email protected]>
2018-10-03dt-bindings: clock: dra7xx: add clkctrl indices for new data layoutTero Kristo1-68/+258
The new data layout will be split based on clockdomain boundaries, instead of CM boundaries. This introduces a few new clkctrl providers, that have different indices for the clkctrl data. Signed-off-by: Tero Kristo <[email protected]> Tested-by: Tony Lindgren <[email protected]>
2018-10-03dt-bindings: clock: am43xx: add clkctrl indices for new data layoutTero Kristo1-0/+132
The new data layout will be split based on clockdomain boundaries, instead of CM boundaries. This introduces a few new clkctrl providers, that have different indices for the clkctrl data. Signed-off-by: Tero Kristo <[email protected]> Tested-by: Tony Lindgren <[email protected]>
2018-10-03dt-bindings: clock: am33xx: add clkctrl indices for new data layoutTero Kristo1-0/+119
The new data layout will be split based on clockdomain boundaries, instead of CM boundaries. This introduces a few new clkctrl providers, that have different indices for the clkctrl data. Signed-off-by: Tero Kristo <[email protected]> Tested-by: Tony Lindgren <[email protected]>
2018-10-02clk: keystone: Enable TISCI clocks if K3_ARCHNishanth Menon2-1/+2
K3_ARCH uses TISCI for clocks as well. Enable the same for the driver support. Signed-off-by: Nishanth Menon <[email protected]> Acked-by: Santosh Shilimkar <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-02clk: davinci: kill davinci_clk_reset_assert/deassert()Bartosz Golaszewski2-39/+0
This code is no longer used. Remove it. Signed-off-by: Bartosz Golaszewski <[email protected]> Reviewed-by: David Lechner <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-01clk: mvebu: ap806: Remove superfluous of_clk_add_providerGregory CLEMENT1-1/+0
While applying the commit a8309cedcdce ("clk: apn806: Add eMMC clock to system controller driver"), of_clk_add_provider was added wheres it was already present in the probe function. This extraneous call is harmless but not useful so remove it. Signed-off-by: Gregory CLEMENT <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-01clk: mvebu: use SPDX-License-IdentifierGregory CLEMENT17-52/+17
Convert the remaining files to SPDX license description. Signed-off-by: Gregory CLEMENT <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-01Merge tag 'sunxi-clk-for-4.20' of ↵Stephen Boyd11-86/+144
https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner Pull allwinner clock changes from Maxime Ripard: Our usual set of changes for the Allwinner SoCs clock support. The most notable changes are: - A bunch of changes and fixes to support the A64 display engine - Some fixes to support the A83t display engine * tag 'sunxi-clk-for-4.20' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO0 macro clk: sunxi-ng: a64: Add max. rate constraint to video PLLs clk: sunxi-ng: a64: Add minimal rate for video PLLs clk: sunxi-ng: sun50i: h6: Add 2x fixed post-divider to MMC module clocks clk: sunxi-ng: a83t: Add max. rate constraint to video PLLs clk: sunxi-ng: nkmp: Add constraint for maximum rate clk: sunxi-ng: r40: Add max. rate constraint to video PLLs clk: sunxi-ng: h3/h5: Add max. rate constraint to pll-video clk: sunxi-ng: Add maximum rate constraint to NM PLLs clk: sunxi-ng: h6: fix PWM gate/reset offset clk: sunxi-ng: h6: fix bus clocks' divider position
2018-10-01Merge tag 'clk-renesas-for-v4.20-tag2' of ↵Stephen Boyd31-138/+954
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Add support for CMT timer clocks on R-Car V3H - Add support for SHDI and various timer clocks on R-Car V3M - Add support for the new RZ/A2 (R7S9210) SoC, including early clock support for the Renesas CPG/MSSR driver - Add support for the new RZ/G1N (R8A7744) and RZ/G2E (R8A774C0) SoCs - Convert DT binding includes to SPDX license identifiers * tag 'clk-renesas-for-v4.20-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: r7s9210: Add SPI clocks clk: renesas: r7s9210: Move table update to separate function clk: renesas: r7s9210: Convert some clocks to early clk: renesas: cpg-mssr: Add early clock support clk: renesas: r8a77970: Add TPU clock clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment dt-bindings: clock: renesas: cpg-mssr: Document r8a774c0 clk: renesas: cpg-mssr: Add r8a774c0 support clk: renesas: Add r8a774c0 CPG Core Clock Definitions clk: renesas: r8a7743: Add r8a7744 support clk: renesas: Add r8a7744 CPG Core Clock Definitions dt-bindings: clock: renesas: cpg-mssr: Document r8a7744 binding dt-bindings: clock: renesas: Convert to SPDX identifiers clk: renesas: cpg-mssr: Add R7S9210 support clk: renesas: r8a77970: Add TMU clocks clk: renesas: r8a77970: Add CMT clocks clk: renesas: r9a06g032: Fix UART34567 clock rate clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI clk: renesas: r8a77980: Add CMT clocks
2018-10-01Merge tag 'meson-clk-4.20-1' of https://github.com/BayLibre/clk-meson into ↵Stephen Boyd9-627/+732
clk-meson Pull meson clk driver updates from Jerome Brunet: - clk-pll driver improvements and updates - add axg audio controller system clocks - drop mpll3 from the possible pcie clock parent of the axg - register meson8b clock controller early * tag 'meson-clk-4.20-1' of https://github.com/BayLibre/clk-meson: clk: meson: meson8b: use the regmap in the internal reset controller clk: meson: meson8b: register the clock controller early clk: meson-axg: pcie: drop the mpll3 clock parent clk: meson: axg: round audio system master clocks down clk: meson: clk-pll: drop hard-coded rates from pll tables clk: meson: clk-pll: remove od parameters clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary clk: meson: clk-pll: add enable bit
2018-09-28clk: renesas: Convert to SPDX identifiersKuninori Morimoto22-95/+27
This patch updates license to use SPDX-License-Identifier instead of verbose license text. Signed-off-by: Kuninori Morimoto <[email protected]> [rebased against clk-spdx] Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Simon Horman <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-09-28clk: renesas: r7s9210: Add SPI clocksChris Brandt1-0/+3
Add RSPI clocks for RZ/A2. Signed-off-by: Chris Brandt <[email protected]> Reviewed-by: Simon Horman <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2018-09-26clk: renesas: r7s9210: Move table update to separate functionChris Brandt1-45/+50
Same functionality, just easier to read. Signed-off-by: Chris Brandt <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2018-09-26clk: renesas: r7s9210: Convert some clocks to earlyChris Brandt1-6/+26
The OSTM timer driver for RZ/A2 uses TIMER_OF_DECLARE which requires the ostm module clocks to be registers early in boot. Signed-off-by: Chris Brandt <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2018-09-26clk: renesas: cpg-mssr: Add early clock supportChris Brandt2-21/+89
Add support for SoCs that need to register core and module clocks early in order to use OF drivers that exclusively use macros such as TIMER_OF_DECLARE. Signed-off-by: Chris Brandt <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2018-09-26clk: meson: meson8b: use the regmap in the internal reset controllerMartin Blumenstingl1-7/+6
For now the reset controller was using raw register access because the early init did not initialize the regmap. However, now that clocks are initialized early we can simply use the regmap also for the reset controller. No functional changes. Signed-off-by: Martin Blumenstingl <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
2018-09-26clk: meson: meson8b: register the clock controller earlyMartin Blumenstingl1-60/+34
Until now only the reset controller (part of the clock controller register space) was registered early in the boot process, while the clock controller itself was registered later on. However, some parts of the SoC are initialized early in the boot process, such as the SRAM and the TWD timer. The bootloader already enables these clocks so we didn't see any issues so far. Register the clock controller early so other drivers (such as the SRAM and TWD timer) can use the clocks early in the boot process. Signed-off-by: Martin Blumenstingl <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
2018-09-26clk: meson-axg: pcie: drop the mpll3 clock parentYixun Lan1-2/+4
We found the PCIe driver doesn't really work with the mpll3 clock which is actually reserved for debug, So drop it from the mux list. Fixes: 33b89db68236 ("clk: meson-axg: add clocks required by pcie driver") Tested-by: Jianxin Qin <[email protected]> Signed-off-by: Yixun Lan <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
2018-09-26clk: meson: axg: round audio system master clocks downJerome Brunet1-11/+23
Some of the master clocks provided by the axg audio clock controller are system clock (spdifin and pdm sysclk). They are used to clock an internal DSP of the related devices. Having them constantly rounded down instead of closest is preferable. Signed-off-by: Jerome Brunet <[email protected]>
2018-09-26clk: meson: clk-pll: drop hard-coded rates from pll tablesJerome Brunet5-142/+162
Putting hard-coded rates inside the parameter tables assumes that the parent is known and will never change. That's a big assumption we should not make. We have everything we need to recalculate the output rate using the parent rate and the rest of the parameters. Let's do so and drop the rates from the tables. Acked-by: Neil Armstrong <[email protected]> Reviewed-by: Martin Blumenstingl <[email protected]> Tested-by: Martin Blumenstingl <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
2018-09-26clk: meson: clk-pll: remove od parametersJerome Brunet8-498/+493
Remove od parameters from pll clocks and add post dividers clocks instead. Some clock, especially the one which feature several ods, may provide output between those ods. Also, some drivers, such as the hdmi driver, may require a more detailed control of the clock dividers, compared to what CCF would perform automatically. One added benefit of removing ods is that it also greatly reduce the size of the rate parameter tables. In the future, we could possibly take the predivider 'n' out of this driver as well. To do so, we will need to understand the constraints for the PLL to lock and whether or not it depends on the input clock rate. Acked-by: Neil Armstrong <[email protected]> Reviewed-by: Martin Blumenstingl <[email protected]> Tested-by: Martin Blumenstingl <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
2018-09-26clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessaryJerome Brunet3-8/+8
CLK_GET_RATE_NOCACHE should only be necessary when the registers controlling the rate of clock may change outside of CCF. On Amlogic, it should only be the case for the hdmi pll which is directly controlled by the display driver (WIP to fix this). The other plls should not require this flag. Reviewed-by: Martin Blumenstingl <[email protected]> Tested-by: Martin Blumenstingl <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
2018-09-26clk: meson: clk-pll: add enable bitJerome Brunet5-10/+113
Add the enable the bit of the pll clocks. These pll clocks may be disabled but we can't model this as an external gate since the pll needs to lock when enabled. Adding this bit allows to drop the poke of the first register of PLL. This will be useful to model the different components of the pll using generic clocks elements Acked-by: Neil Armstrong <[email protected]> Reviewed-by: Martin Blumenstingl <[email protected]> Tested-by: Martin Blumenstingl <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
2018-09-25clk: renesas: r8a77970: Add TPU clockSergei Shtylyov1-0/+1
The TPU0 clock wasn't present in the original R8A77970 patch by Daisuke Matsushita, it was added in a later BSP version... Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <[email protected]> Signed-off-by: Sergei Shtylyov <[email protected]> Reviewed-by: Simon Horman <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2018-09-25clk: renesas: r8a77990: Fix incorrect PLL0 divider in commentGeert Uytterhoeven1-2/+2
PLL0 runs at 4.8 GHz, i.e. EXTAL x 100. Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Simon Horman <[email protected]>
2018-09-19dt-bindings: clock: renesas: cpg-mssr: Document r8a774c0Fabrizio Castro1-2/+4
This patch documents RZ/G2E (a.k.a. R8A774C0) bindings for the Clock Pulse Generator driver. Signed-off-by: Fabrizio Castro <[email protected]> Reviewed-by: Biju Das <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2018-09-19clk: renesas: cpg-mssr: Add r8a774c0 supportFabrizio Castro5-0/+299
Add RZ/G2E (R8A774C0) Clock Pulse Generator / Module Standby and Software Reset support. Based on Table 8.2g of "RZ/G Series, 2nd Generation User's Manual: Hardware (Rev. 0.61, June 12, 2018)". Signed-off-by: Fabrizio Castro <[email protected]> Reviewed-by: Biju Das <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2018-09-19clk: renesas: Add r8a774c0 CPG Core Clock DefinitionsFabrizio Castro1-0/+60
Add all RZ/G2E (a.k.a. R8A774C0) Clock Pulse Generator Core Clock Outputs, as listed in Table 8.2g ("List of Clocks [RZ/G2E]") of the RZ/G2 Hardware User's Manual. Signed-off-by: Fabrizio Castro <[email protected]> Reviewed-by: Biju Das <[email protected]> Reviewed-by: Simon Horman <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2018-09-19clk: renesas: r8a7743: Add r8a7744 supportBiju Das3-2/+18
Add RZ/G1N (R8A7744) Clock Pulse Generator / Module Standby and Software Reset support. Signed-off-by: Biju Das <[email protected]> Reviewed-by: Fabrizio Castro <[email protected]> Reviewed-by: Simon Horman <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2018-09-19clk: renesas: Add r8a7744 CPG Core Clock DefinitionsBiju Das1-0/+39
Add all RZ/G1N Clock Pulse Generator Core Clock Outputs, as listed in Table 7.2b ("List of Clocks [RZ/G1M/N]") of the RZ/G1 Hardware User's Manual. Signed-off-by: Biju Das <[email protected]> Reviewed-by: Fabrizio Castro <[email protected]> Reviewed-by: Simon Horman <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2018-09-19dt-bindings: clock: renesas: cpg-mssr: Document r8a7744 bindingBiju Das1-5/+6
Add binding documentation for the RZ/G1N (R8A7744) Clock Pulse Generator driver. Signed-off-by: Biju Das <[email protected]> Reviewed-by: Fabrizio Castro <[email protected]> Reviewed-by: Simon Horman <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2018-09-19dt-bindings: clock: renesas: Convert to SPDX identifiersKuninori Morimoto15-93/+30
This patch updates license to use SPDX-License-Identifier instead of verbose license text on Renesas related headers. Signed-off-by: Kuninori Morimoto <[email protected]> Reviewed-by: Simon Horman <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2018-09-11clk: renesas: cpg-mssr: Add R7S9210 supportChris Brandt7-14/+300
Add support for the R7S9210 (RZ/A2) Clock Pulse Generator and Module Standby. The Module Standby HW in the RZ/A series is very close to R-Car HW, except for how the registers are laid out. The MSTP registers are only 8-bits wide, there are no status registers (MSTPSR), and the register offsets are a little different. Since the RZ/A hardware manuals refer to these registers as the Standby Control Registers, we'll use that name to distinguish the RZ/A type from the R-Car type. Signed-off-by: Chris Brandt <[email protected]> Acked-by: Rob Herring <[email protected]> # DT bits Signed-off-by: Geert Uytterhoeven <[email protected]>
2018-09-11clk: renesas: r8a77970: Add TMU clocksSergei Shtylyov1-0/+5
The TMU clocks weren't present in the original R8A77970 patch by Daisuke Matsushita, they were added in a later BSP version... Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <[email protected]> Signed-off-by: Sergei Shtylyov <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2018-09-11clk: renesas: r8a77970: Add CMT clocksSergei Shtylyov1-0/+4
Add the R8A77970 CMT module clocks. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <[email protected]> Signed-off-by: Sergei Shtylyov <[email protected]> Reviewed-by: Chris Paterson <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2018-09-11clk: renesas: r9a06g032: Fix UART34567 clock ratePhil Edworthy1-1/+2
The clock for UARTs 0 through 2 is UART012, the clock for UARTs 3 through 7 is UART34567. For UART012, we stop the clock driver from changing the clock rate. This is because the Synopsys UART driver simply sets the reference clock to 16x the baud rate, but doesn't check if the actual rate is within the required tolerance. The RZ/N1 clock divider can't provide this (we have to rely on the UART's internal divider to set the correct clock rate), so you end up with a clock rate that is way off what you wanted. In addition, since the clock is shared between multiple UARTs, you don't want the driver trying to change the clock rate as it may affect the other UARTs (which may not have been configured yet, so you don't know what baud rate they will use). Normally, the clock rate is set early on before Linux to some very high rate that supports all of the clock rates you want. This change stops the UART34567 clock rate from changing for the same reasons. Signed-off-by: Phil Edworthy <[email protected]> Fixes: 4c3d88526eba2143 ("clk: renesas: Renesas R9A06G032 clock driver") Signed-off-by: Geert Uytterhoeven <[email protected]>
2018-09-06clk: samsung: s3c2443: Use generic helper for handling suspend/resumeMarek Szyprowski1-41/+2
Replace common suspend/resume handling code by generic helper. Almost no functional change, the only difference is in handling of hypothetical memory allocation failure on boot. Signed-off-by: Marek Szyprowski <[email protected]> Acked-by: Chanwoo Choi <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
2018-09-06clk: samsung: s3c2412: Use generic helper for handling suspend/resumeMarek Szyprowski1-41/+2
Replace common suspend/resume handling code by generic helper. Almost no functional change, the only difference is in handling of hypothetical memory allocation failure on boot. Signed-off-by: Marek Szyprowski <[email protected]> Acked-by: Chanwoo Choi <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
2018-09-06clk: samsung: s3c2410: Use generic helper for handling suspend/resumeMarek Szyprowski1-41/+2
Replace common suspend/resume handling code by generic helper. Almost no functional change, the only difference is in handling of hypothetical memory allocation failure on boot. Signed-off-by: Marek Szyprowski <[email protected]> Acked-by: Chanwoo Choi <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
2018-09-06clk: samsung: Remove excessive includeMarek Szyprowski2-2/+0
Exynos Audio SubSystem and Exynos3250 clock drivers don't use any syscore function, so don't include linux/syscore_ops.h in their code. Signed-off-by: Marek Szyprowski <[email protected]> Acked-by: Chanwoo Choi <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
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