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2017-04-06drm/amd/amdgpu: cleanup gfx_v9_0_gpu_init()Tom St Denis1-3/+1
Use new WREG32_FIELD15 macro Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-06drm/amd/amdgpu: cleanup gfx_v9_0_rlc_reset()Tom St Denis1-6/+2
Use new WREG32_FIELD15 macro Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-06drm/amd/amdgpu: cleanup gfx_v9_0_rlc_start()Tom St Denis1-3/+1
Use new WREG32_FIELD15 macro Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-06drm/amd/amdgpu: simplify gfx_v9_0_cp_gfx_enable()Tom St Denis1-8/+4
Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-06drm/amd/amdgpu: cleanup gfx_v9_0_kiq_init_register()Tom St Denis1-9/+3
Use new WREG32_FIELD macro Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-06drm/amd/amdgpu: Drop gfx_v9_0_print_status()Tom St Denis1-174/+1
It's not used in gfx 6/7/8 so drop it from gfx 9 as well. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-06drm/amd/amdgpu: cleanup gfx_v9_0_set_gfx_eop_interrupt_state()Tom St Denis1-12/+3
Use new WREG32_FIELD15 macro. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-06drm/amd/amdgpu: cleanup gfx_v9_0_set_priv_reg_fault_state()Tom St Denis1-11/+3
Use new WREG32_FIELD15 macro. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-06drm/amd/amdgpu: cleanup gfx_v9_0_set_priv_inst_fault_state()Tom St Denis1-12/+3
Use new WREG32_FIELD15 macro. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-06drm/amd/amdgpu: cleanup gfx_v9_0_init_queue()Tom St Denis2-8/+6
Introduce WREG32_FIELD15 macro for SOC15 architectures. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-06drm/amdgpu: Move function amdgpu_has_atpx near other similar functionsAlex Xie2-6/+2
Signed-off-by: Alex Xie <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-06drm/amdgpu: fix over allocating of IRQ sourcesChristian König1-3/+4
We need an array of pointers to IRQ sources, not an array of sources. Signed-off-by: Christian König <[email protected]> Reported-by: Dan Carpenter <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-06drm/amd/amdgpu: Clean up psp reload_quirk()Tom St Denis1-8/+4
Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-06drm/amd/amdgpu: Fix psp_v3_1 compare sramTom St Denis1-1/+1
Had the wrong sense in the loop Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-06drm/amdgpu: cleanup get_invalidate_req v2Christian König8-49/+27
The two hubs are just instances of the same hardware, so the register bits are identical. v2: keep the function pointer Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-06drm/amdgpu: fix vm size and block size for VMPT (v5)Zhang, Jerry9-35/+52
Set reasonable defaults per family. v2: set both of them in gmc v3: move vm size and block size in vm manager v4: squash in warning fix from Alex Xie v5: squash in min() warning fix Signed-off-by: Junwei Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-06drm/amd/amdgpu: Fix srbm_indexing in init/inactive hqd codeTom St Denis1-0/+5
Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-06drm/amd/amdgpu: Clean up gfx_v8_0_mqd_init()Tom St Denis1-8/+4
Clean up a toggle with ?:. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-06drm/amd/amdgpu: de-numberify HQD_ACTIVE check.Tom St Denis1-2/+2
Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-06drm/amd/amdgpu: clean up gfx_v8_0_kiq_init_register()Tom St Denis1-9/+3
Swap read/write pattern for WREG32_FIELD() Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-06drm/amd/amdgpu: Clean up gfx_v8_0_inactive_hqd()Tom St Denis1-5/+1
Swap read/write pattern for WREG32_FIELD() Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-06drm/amd/amdgpu: Clean up gfx_v8_0_kiq_set_interrupt_state()Tom St Denis2-28/+15
Use new WREG32_FIELD_OFFSET() to clean up code. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-06drm/amdgpu/gfx8: KIQ is also disabled when MEC is disabledAlex Deucher1-0/+1
Set the ready flag to reflect this. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-06drm/amdgpu: cleanup VMHUB bit definitions v2Christian König4-29/+8
The two hubs are just instances of the same hardware, so the register bits are identical. v2: only remove get_vm_protection_bits for now Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-06drm/amdgpu: handle CPU access for split VRAM buffers (v2)Christian König2-7/+13
This avoids merging them together on page fault. v2: squash in 64-bit division fix Signed-off-by: Christian König <[email protected]> Acked-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-06drm/nouveau/gpio: enable interrupts on cards with 32 gpio linesAdam Borowski1-1/+1
The code attempts to enable them, but hits an undefined behaviour by shifting by the entire register's width: int lines = 32; u32 mask = (1 << lines) - 1; // 00000000 on x86 u32 mask = (1 << lines) - 1; // ffffffff on arm (32) u32 mask = (1 << lines) - 1; // 00000000 on arm64 u32 mask = (1ULL << lines) - 1; // ffffffff everywhere Signed-off-by: Adam Borowski <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2017-04-06drm/nouveau/gr/gp107: initial supportBen Skeggs9-8/+120
Forked from GP106 implementation. Differences: - 1 PPC/GPC - Slightly different grctx magics Signed-off-by: Ben Skeggs <[email protected]>
2017-04-06drm/nouveau/core: recognise GP10B chipsetAlexandre Courbot1-0/+24
Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2017-04-06drm/nouveau/platform: support for probing GP10BAlexandre Courbot1-0/+10
Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2017-04-06drm/nouveau/platform: make VDD regulator optionalAlexandre Courbot3-9/+28
GP10B's power is managed by generic PM domains, so it does not require a VDD regulator. Add this option into the chip function structure. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2017-04-06drm/nouveau/gr: support for GP10BAlexandre Courbot6-2/+77
GR is similar to GP100, with a few unavailable registers. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2017-04-06drm/nouveau/ibus: add GP10B supportAlexandre Courbot3-0/+61
GP10B requires a specific initialization sequence due to the absence of devinit. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2017-04-06drm/nouveau/mc: add GP10B supportAlexandre Courbot5-5/+69
GP10B's MC is compatible with GP100's, but engines need to be explicitly put out of ELPG during init. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2017-04-06drm/nouveau/fb: add GP10B supportAlexandre Courbot3-0/+40
GP10B's FB is largely compatible with the GP100 implementation. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2017-04-06drm/nouveau/fifo: add GP10B supportAlexandre Courbot5-1/+45
GP10B's FIFO is similar to GP100's, but only allows 512 channels. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2017-04-06drm/nouveau/msgqueue: support for GP10B PMU firmwareAlexandre Courbot3-0/+117
The GP10B firmware is very close to GM20B's. The only difference is that it supports booting multiple falcons. In order to avoid having too much functions and structures shared, implement its support in the same source file as GM20B firmware. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2017-04-06drm/nouveau/secboot: add GP10B supportAlexandre Courbot3-0/+95
GP10B's secboot is largely similar to GM20B's. Only differences are MC base address and the fact that GPCCS is also securely managed. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2017-04-06drm/nouveau/secboot/gm20b: specify MC base address as argumentAlexandre Courbot2-8/+12
Allow the MC base address to be specified as an argument for the WPR region reading function. GP10B uses a different address layout as GM20B, so this is necessary. Also export the function to be used by GP10B. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2017-04-06drm/nouveau/secboot: start LS firmware in post-run hookAlexandre Courbot2-49/+47
The LS firmware post-run hook is the right place to start said LS firmware. Moving it here also allows to remove special handling in the ACR code. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2017-04-06drm/nouveau/secboot: let LS post_run hooks return errorAlexandre Courbot4-10/+26
A LS post-run hook can meet an error meaning the failure of secure boot. Make sure this can be reported. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2017-04-06drm/nouveau/secboot: pass instance to LS firmware loadersAlexandre Courbot12-39/+44
Having access to the secboot instance loading a LS firmware can be useful to LS firmware handlers. At least more useful than just having an out-of-context subdev pointer. GP10B's firmware will also need to know the WPR address, which can be obtained from the secboot instance. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2017-04-06drm/nouveau/secboot: allow to boot multiple falconsAlexandre Courbot8-28/+54
Change the secboot and msgqueue interfaces to take a mask of falcons to reset instead of a single falcon. The GP10B firmware interface requires FECS and GPCCS to be booted in a single firmware command. For firmwares that only support single falcon boot, it is trivial to loop over the mask and boot each falcons individually. Signed-off-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2017-04-06drm/nouveau/imem/gk20a: Turn instmem lock into mutexThierry Reding1-11/+8
The gk20a implementation of instance memory uses vmap()/vunmap() to map memory regions into the kernel's virtual address space. These functions may sleep, so protecting them by a spin lock is not safe. This triggers a warning if the DEBUG_ATOMIC_SLEEP Kconfig option is enabled. Fix this by using a mutex instead. Signed-off-by: Thierry Reding <[email protected]> Reviewed-by: Alexandre Courbot <[email protected]> Tested-by: Alexandre Courbot <[email protected]> Signed-off-by: Ben Skeggs <[email protected]>
2017-04-06drm/nouveau: initial support (display-only) for GP107Ben Skeggs1-0/+30
Forked from GP106 implementation. Split out from commit enabling secboot/gr support so that it can be added to earlier kernels. Cc: [email protected] [4.10+] Signed-off-by: Ben Skeggs <[email protected]>
2017-04-06drm/nouveau/kms/nv50: fix double dma_fence_put() when destroying plane stateBen Skeggs1-2/+0
When the atomic support was added to nouveau, the DRM core did not do this. However, later in the same merge window, a commit (drm/fence: add in-fences support) was merged that added it, leading to use-after-frees of the fence object. Cc: [email protected] [4.10+] Signed-off-by: Ben Skeggs <[email protected]>
2017-04-06drm/nouveau/kms/nv50: fix setting of HeadSetRasterVertBlankDmi methodBen Skeggs1-3/+5
Cc: [email protected] [4.10+] Signed-off-by: Ben Skeggs <[email protected]>
2017-04-06drm/nouveau/mmu/nv4a: use nv04 mmu rather than the nv44 oneIlia Mirkin1-1/+1
The NV4A (aka NV44A) is an oddity in the family. It only comes in AGP and PCI varieties, rather than a core PCIE chip with a bridge for AGP/PCI as necessary. As a result, it appears that the MMU is also non-functional. For AGP cards, the vast majority of the NV4A lineup, this worked out since we force AGP cards to use the nv04 mmu. However for PCI variants, this did not work. Switching to the NV04 MMU makes it work like a charm. Thanks to mwk for the suggestion. This should be a no-op for NV4A AGP boards, as they were using it already. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70388 Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected] Signed-off-by: Ben Skeggs <[email protected]>
2017-04-06drm/nouveau/mpeg: mthd returns true on success nowIlia Mirkin2-2/+2
Signed-off-by: Ilia Mirkin <[email protected]> Fixes: 590801c1a3 ("drm/nouveau/mpeg: remove dependence on namedb/engctx lookup") Cc: [email protected] # v4.3+ Signed-off-by: Ben Skeggs <[email protected]>
2017-04-04drm/amdgpu: use TTM_PL_FLAG_CONTIGUOUS v2Christian König2-10/+18
Implement AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS using TTM_PL_FLAG_CONTIGUOUS instead of a placement limit. That allows us to better handle CPU accessible placements. v2: prevent virtual BO start address from overflowing Signed-off-by: Christian König <[email protected]> Acked-by: Michel Dänzer <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-04-04drm/amdgpu: move adjust_mc_addr into amdgpu_gart_funcsChristian König3-23/+9
We should probably rename amdgpu_gart_funcs sooner or later. Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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