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2019-02-21Merge branch 'master' of ↵David S. Miller9-47/+53
git://git.kernel.org/pub/scm/linux/kernel/git/klassert/ipsec Steffen Klassert says: ==================== pull request (net): ipsec 2019-02-21 1) Don't do TX bytes accounting for the esp trailer when sending from a request socket as this will result in an out of bounds memory write. From Martin Willi. 2) Destroy xfrm_state synchronously on net exit path to avoid nested gc flush callbacks that may trigger a warning in xfrm6_tunnel_net_exit(). From Cong Wang. 3) Do an unconditionally clone in pfkey_broadcast_one() to avoid a race when freeing the skb. From Sean Tranchetti. 4) Fix inbound traffic via XFRM interfaces across network namespaces. We did the lookup for interfaces and policies in the wrong namespace. From Tobias Brunner. Please pull or let me know if there are problems. ==================== Signed-off-by: David S. Miller <[email protected]>
2019-02-21Merge branch 'report-erspan-version-field-just-for-erspan-tunnels'David S. Miller2-34/+35
Lorenzo Bianconi says: ==================== report erspan version field just for erspan tunnels Do not report erspan_version to userpsace for non erspan tunnels. Report IFLA_GRE_ERSPAN_INDEX only for erspan version 1 in ip6gre_fill_info ==================== Signed-off-by: David S. Miller <[email protected]>
2019-02-21net: ip6_gre: do not report erspan_ver for ip6gre or ip6gretapLorenzo Bianconi1-18/+18
Report erspan version field to userspace in ip6gre_fill_info just for erspan_v6 tunnels. Moreover report IFLA_GRE_ERSPAN_INDEX only for erspan version 1. The issue can be triggered with the following reproducer: $ip link add name gre6 type ip6gre local 2001::1 remote 2002::2 $ip link set gre6 up $ip -d link sh gre6 14: grep6@NONE: <POINTOPOINT,NOARP,UP,LOWER_UP> mtu 1448 qdisc noqueue state UNKNOWN mode DEFAULT group default qlen 1000 link/gre6 2001::1 peer 2002::2 promiscuity 0 minmtu 0 maxmtu 0 ip6gre remote 2002::2 local 2001::1 hoplimit 64 encaplimit 4 tclass 0x00 flowlabel 0x00000 erspan_index 0 erspan_ver 0 addrgenmode eui64 Fixes: 94d7d8f29287 ("ip6_gre: add erspan v2 support") Signed-off-by: Lorenzo Bianconi <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-02-21net: ip_gre: do not report erspan_ver for gre or gretapLorenzo Bianconi1-16/+17
Report erspan version field to userspace in ipgre_fill_info just for erspan tunnels. The issue can be triggered with the following reproducer: $ip link add name gre1 type gre local 192.168.0.1 remote 192.168.1.1 $ip link set dev gre1 up $ip -d link sh gre1 13: gre1@NONE: <POINTOPOINT,NOARP,UP,LOWER_UP> mtu 1476 qdisc noqueue state UNKNOWN mode DEFAULT group default qlen 1000 link/gre 192.168.0.1 peer 192.168.1.1 promiscuity 0 minmtu 0 maxmtu 0 gre remote 192.168.1.1 local 192.168.0.1 ttl inherit erspan_ver 0 addrgenmode eui64 numtxqueues 1 numrxqueues 1 Fixes: f551c91de262 ("net: erspan: introduce erspan v2 for ip_gre") Signed-off-by: Lorenzo Bianconi <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-02-22Merge branch 'drm-fixes-5.0' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie10-13/+40
into drm-fixes A bit bigger than normal for this week due to fixes for some long standing display issues that are bound for stable. These changes would be going to stable anyway, so I figured it was better via 5.0 than 5.1. - Several display fixes - Fix PX systems due to core changes in runtime pm - Disable bulk moves. They are fixed in 5.1, but fix is too invasive for 5.0 Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-02-21clk: imx: imx8mm: Mark init function __initStephen Boyd1-1/+1
It calls another __init marked function and thus causes a section mismatch if we don't mark it this way. Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm") Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21ARCv2: don't assume core 0x54 has dual issueVineet Gupta2-5/+29
The first release of core4 (0x54) was dual issue only (HS4x). Newer releases allow hardware to be configured as single issue (HS3x) or dual issue. Prevent accessing a HS4x only aux register in HS3x, which otherwise leads to illegal instruction exceptions Signed-off-by: Vineet Gupta <[email protected]>
2019-02-21clk: qcom: gcc-qcs404: Add cfg_offset for blsp1_uart3 clockTaniya Das1-0/+1
The CFG/M/N/D registers are at an offset of 0x20 from the CMD register only for blsp1_uart3 clock, so add it for uart3 only. Signed-off-by: Taniya Das <[email protected]> Signed-off-by: Anu Ramanathan <[email protected]> Signed-off-by: Shawn Guo <[email protected]> Signed-off-by: Vinod Koul <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21clk: qcom: clk-rcg2: Introduce a cfg offset for RCGsTaniya Das2-10/+16
The RCG CFG/M/N/D register base could be at a different offset than the CMD register, so introduce a cfg_offset to identify the offset with respect to the CMD RCGR register. Signed-off-by: Taniya Das <[email protected]> Signed-off-by: Anu Ramanathan <[email protected]> Signed-off-by: Shawn Guo <[email protected]> Signed-off-by: Vinod Koul <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21clk: qcom: remove empty lines in clk-rcg.hVinod Koul1-3/+0
Remove the redundant empty lines crept in. Signed-off-by: Vinod Koul <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21dt-bindings: clock: remove unused definition for stm32mp1Gabriel Fernandez1-3/+0
A copy of LTDC_PX and ETHCK_K (LTDC_K and ETHMAC_K) was introduced in stm32mp1 dt-bindings file by mistake. These bindings are not used and shouldn't be use to be conform with convention name of the stm32mp1 clock IP. Signed-off-by: Gabriel Fernandez <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21clk: stm32mp1: fix bit width of hse_rtc dividerGabriel Fernandez1-1/+1
Fix the bit width of the hse rtc divider because it's off by one. Fixes: 2c87c9d33117 ("clk: stm32mp1: add RTC clock") Signed-off-by: Gabriel Fernandez <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21clk: stm32mp1: remove unnecessary CLK_DIVIDER_ALLOW_ZERO flagGabriel Fernandez1-3/+2
The divisor of ethptp_k and ck_hse_rtc clocks is: 'value register plus one'. Then CLK_DIVIDER_ALLOW_ZERO flag has no effect and is useless here. Signed-off-by: Gabriel Fernandez <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21clk: stm32mp1: fix HSI divider flagGabriel Fernandez1-2/+2
The divider of HSI (clk-hsi-div) is power of two divider. Fixes: 9bee94e7b7da ("clk: stm32mp1: Introduce STM32MP1 clock driver") Signed-off-by: Gabriel Fernandez <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21clk: stm32mp1: fix mcu divider tableGabriel Fernandez1-1/+1
index 8: ck_mcu is divided by 256 (not 512) Fixes: e51d297e9a92 ("clk: stm32mp1: add Sub System clocks") Signed-off-by: Gabriel Fernandez <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21clk: stm32mp1: set ck_csi as critical clockGabriel Fernandez1-1/+3
ck_csi is used for IO compensation so it should be considered as "always-on" and kept on. Signed-off-by: Gabriel Fernandez <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21clk: stm32mp1: add CLK_SET_RATE_NO_REPARENT to Kernel clocksGabriel Fernandez1-5/+7
STM32MP1 clock IP offers lots of Kernel clocks that are shared by multiple IP's at the same time. Then boot loader applies a clock tree that allows to use all IP's at same time and with the maximum of performance. Not change parents on a change rate on kernel clocks ensures the integrity of the system. Signed-off-by: Gabriel Fernandez <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21clk: stm32mp1: parent clocks updateGabriel Fernandez1-5/+5
Fixes parent clock for axi, fdcan, sai and adc12 clocks. Fixes: e51d297e9a92 ("clk: stm32mp1: add Sub System clocks") Signed-off-by: Gabriel Fernandez <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21clk: clk-twl6040: Fix imprecise external abort for pdmclkTony Lindgren1-2/+51
I noticed that modprobe clk-twl6040 can fail after a cold boot with: abe_cm:clk:0010:0: failed to enable ... Unhandled fault: imprecise external abort (0x1406) at 0xbe896b20 WARNING: CPU: 1 PID: 29 at drivers/clk/clk.c:828 clk_core_disable_lock+0x18/0x24 ... (clk_core_disable_lock) from [<c0123534>] (_disable_clocks+0x18/0x90) (_disable_clocks) from [<c0124040>] (_idle+0x17c/0x244) (_idle) from [<c0125ad4>] (omap_hwmod_idle+0x24/0x44) (omap_hwmod_idle) from [<c053a038>] (sysc_runtime_suspend+0x48/0x108) (sysc_runtime_suspend) from [<c06084c4>] (__rpm_callback+0x144/0x1d8) (__rpm_callback) from [<c0608578>] (rpm_callback+0x20/0x80) (rpm_callback) from [<c0607034>] (rpm_suspend+0x120/0x694) (rpm_suspend) from [<c0607a78>] (__pm_runtime_idle+0x60/0x84) (__pm_runtime_idle) from [<c053aaf0>] (sysc_probe+0x874/0xf2c) (sysc_probe) from [<c05fecd4>] (platform_drv_probe+0x48/0x98) After searching around for a similar issue, I came across an earlier fix that never got merged upstream in the Android tree for glass-omap-xrr02. There is patch "MFD: twl6040-codec: Implement PDMCLK cold temp errata" by Misael Lopez Cruz <[email protected]>. Based on my observations, this fix is also needed when cold booting devices, and not just for deeper idle modes. Since we now have a clock driver for pdmclk, let's fix the issue in twl6040_pdmclk_prepare(). Cc: Misael Lopez Cruz <[email protected]> Cc: Peter Ujfalusi <[email protected]> Signed-off-by: Tony Lindgren <[email protected]> Acked-by: Peter Ujfalusi <[email protected]> Cc: <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21net: avoid false positives in untrusted gso validationWillem de Bruijn1-2/+12
GSO packets with vnet_hdr must conform to a small set of gso_types. The below commit uses flow dissection to drop packets that do not. But it has false positives when the skb is not fully initialized. Dissection needs skb->protocol and skb->network_header. Infer skb->protocol from gso_type as the two must agree. SKB_GSO_UDP can use both ipv4 and ipv6, so try both. Exclude callers for which network header offset is not known. Fixes: d5be7f632bad ("net: validate untrusted gso packets without csum offload") Signed-off-by: Willem de Bruijn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-02-21clk: clk-gpio: add support for sleeping GPIOs in gpio-gate-clkThomas Petazzoni1-2/+37
The current implementation of gpio-gate-clk enables/disables the clock using the GPIO in the ->enable() and ->disable() clock callbacks. This requires the GPIO to be configurable in atomic contexts. While it is the case for most memory-mapped GPIO controllers, it is not the case for GPIO expanders on I2C or SPI. This commit extends the gpio-gate-clk to check whether the GPIO calls require sleeping or not. If sleeping is not required, the current implementation based on ->enable()/->disable() is kept. However, if sleeping is needed, we instead implement the logic in the ->prepare() and ->unprepare() hooks. Thanks to this, a gate clock connected to a GPIO on a GPIO expander can be controlled with the existing driver. Signed-off-by: Thomas Petazzoni <[email protected]> [[email protected]: Mark clk ops static] Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21Merge branch 'tipc-improvement-for-wait-and-wakeup'David S. Miller1-5/+6
Tung Nguyen says: ==================== tipc: improvement for wait and wakeup Some improvements for tipc_wait_for_xzy(). ==================== Signed-off-by: David S. Miller <[email protected]>
2019-02-21tipc: improve function tipc_wait_for_rcvmsg()Tung Nguyen1-4/+5
This commit replaces schedule_timeout() with wait_woken() in function tipc_wait_for_rcvmsg(). wait_woken() uses memory barriers in its implementation to avoid potential race condition when putting a process into sleeping state and then waking it up. Acked-by: Ying Xue <[email protected]> Acked-by: Jon Maloy <[email protected]> Signed-off-by: Tung Nguyen <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-02-21tipc: improve function tipc_wait_for_cond()Tung Nguyen1-1/+1
Commit 844cf763fba6 ("tipc: make macro tipc_wait_for_cond() smp safe") replaced finish_wait() with remove_wait_queue() but still used prepare_to_wait(). This causes unnecessary conditional checking before adding to wait queue in prepare_to_wait(). This commit replaces prepare_to_wait() with add_wait_queue() as the pair function with remove_wait_queue(). Acked-by: Ying Xue <[email protected]> Acked-by: Jon Maloy <[email protected]> Signed-off-by: Tung Nguyen <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-02-21clk: qcom: clk-rpmh: Add IPA clock supportDavid Dai2-0/+147
The clk-rpmh driver only supports on and off RPMh clock resources. Let's extend the driver by adding support for clocks that are managed by a different type of RPMh resource known as Bus Clock Manager(BCM). The BCM is a configurable shared resource aggregator that scales performance based on a set of frequency points. The Qualcomm IP Accelerator (IPA) clock is an example of a resource that is managed by the BCM and this a requirement from the IPA driver in order to scale its core clock. Signed-off-by: David Dai <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21clk: mmp2: separate LCDC peripheral clk form the display clockLubomir Rintel1-2/+3
These are in fact two clocks, they shouldn't be exposed as one. One is required for accessing LCD controller registers (peripheral clock), while other (AXI clock) can be optionally used as a pixel clock source for the panel. LCDC can alternatively use different clocks than the Display 1 AXI clock for generating the pixel clock: the second AXI clock (fixed in this commit too), the HDMI PLL, or the AXI bus clock. They should really be controlled independently. Link: https://lists.freedesktop.org/archives/dri-devel/2019-January/203975.html Signed-off-by: Lubomir Rintel <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21dt-bindings: marvell,mmp2: Add clock id for the LCDC clockLubomir Rintel1-0/+1
The peripheral clock is required for access the the LCDC registers. It is in fact separate from the "AXI clock" that is optionally used to generate the pixel clock and as such requires a separate clock id. Link: https://lists.freedesktop.org/archives/dri-devel/2019-January/203975.html Signed-off-by: Lubomir Rintel <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21clk: uniphier: Fix update register for CPU-gearKunihiko Hayashi1-1/+1
Need to set the update bit in UNIPHIER_CLK_CPUGEAR_UPD to update the CPU-gear value. Fixes: d08f1f0d596c ("clk: uniphier: add CPU-gear change (cpufreq) support") Cc: [email protected] Signed-off-by: Kunihiko Hayashi <[email protected]> Acked-by: Masahiro Yamada <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21Merge tag 'ti-clk-for-5.1' of ↵Stephen Boyd15-63/+165
git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into clk-ti Pull TI clock driver updates from Tero Kristo: Contains the CLK_IS_BASIC flag cleanup, getting rid of the flag completely from TI clock driver. Also contains the autoidle clock support series from Andreas Kemnade, which is needed for handling the hdq clocks properly during low power states; at least on gta04 board. * tag 'ti-clk-for-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux: ARM: OMAP2+: hwmod: disable ick autoidling when a hwmod requires that clk: ti: check clock type before doing autoidle ops clk: ti: add a usecount for autoidle clk: ti: generalize the init sequence of clk_hw_omap clocks clk: ti: remove usage of CLK_IS_BASIC clk: ti: add new API for checking if a provided clock is an OMAP clock clk: ti: move clk_hw_omap list handling under generic part of the driver
2019-02-21clk: samsung: s3c2443: Mark expected switch fall-throughGustavo A. R. Silva1-1/+1
In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. This patch fixes the following warnings: drivers/clk/samsung/clk-s3c2443.c: In function ‘s3c2443_common_clk_init’: drivers/clk/samsung/clk-s3c2443.c:390:3: warning: this statement may fall through [-Wimplicit-fallthrough=] samsung_clk_register_alias(ctx, s3c2450_aliases, ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ARRAY_SIZE(s3c2450_aliases)); ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/clk/samsung/clk-s3c2443.c:393:2: note: here case S3C2416: ^~~~ Warning level 3 was used: -Wimplicit-fallthrough=3 Notice that, in this particular case, the code comment is modified in accordance with what GCC is expecting to find. This patch is part of the ongoing efforts to enable -Wimplicit-fallthrough. Signed-off-by: Gustavo A. R. Silva <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21clk: samsung: exynos5: Fix kfree() of const memory on setting driver_overrideKrzysztof Kozlowski1-2/+1
Platform driver driver_override field should not be initialized from const memory because the core later kfree() it. If driver_override is manually set later through sysfs, kfree() of old value leads to: $ echo "new_value" > /sys/bus/platform/drivers/.../driver_override kernel BUG at ../mm/slub.c:3960! Internal error: Oops - BUG: 0 [#1] PREEMPT SMP ARM ... (kfree) from [<c058e8c0>] (platform_set_driver_override+0x84/0xac) (platform_set_driver_override) from [<c058e908>] (driver_override_store+0x20/0x34) (driver_override_store) from [<c031f778>] (kernfs_fop_write+0x100/0x1dc) (kernfs_fop_write) from [<c0296de8>] (__vfs_write+0x2c/0x17c) (__vfs_write) from [<c02970c4>] (vfs_write+0xa4/0x188) (vfs_write) from [<c02972e8>] (ksys_write+0x4c/0xac) (ksys_write) from [<c0101000>] (ret_fast_syscall+0x0/0x28) The clk-exynos5-subcmu driver uses override only for the purpose of creating meaningful names for children devices (matching names of power domains, e.g. DISP, MFC). The driver_override was not developed for this purpose so just switch to default names of devices to fix the issue. Fixes: b06a532bf1fa ("clk: samsung: Add Exynos5 sub-CMU clock driver") Cc: <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21clk: samsung: exynos5: Fix possible NULL pointer exception on ↵Krzysztof Kozlowski1-2/+8
platform_device_alloc() failure During initialization of subdevices if platform_device_alloc() failed, returned NULL pointer will be later dereferenced. Add proper error paths to exynos5_clk_register_subcmu(). The return value of this function is still ignored because at this stage of init there is nothing we can do. Fixes: b06a532bf1fa ("clk: samsung: Add Exynos5 sub-CMU clock driver") Cc: <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21bonding: fix PACKET_ORIGDEV regressionMichal Soltys1-21/+14
This patch fixes a subtle PACKET_ORIGDEV regression which was a side effect of fixes introduced by: 6a9e461f6fe4 bonding: pass link-local packets to bonding master also. ... to: b89f04c61efe bonding: deliver link-local packets with skb->dev set to link that packets arrived on While 6a9e461f6fe4 restored pre-b89f04c61efe presence of link-local packets on bonding masters (which is required e.g. by linux bridges participating in spanning tree or needed for lab-like setups created with group_fwd_mask) it also caused the originating device information to be lost due to cloning. Maciej Żenczykowski proposed another solution that doesn't require packet cloning and retains original device information - instead of returning RX_HANDLER_PASS for all link-local packets it's now limited only to packets from inactive slaves. At the same time, packets passed to bonding masters retain correct information about the originating device and PACKET_ORIGDEV can be used to determine it. This elegantly solves all issues so far: - link-local packets that were removed from bonding masters - LLDP daemons being forced to explicitly bind to slave interfaces - PACKET_ORIGDEV having no effect on bond interfaces Fixes: 6a9e461f6fe4 (bonding: pass link-local packets to bonding master also.) Reported-by: Vincent Bernat <[email protected]> Signed-off-by: Michal Soltys <[email protected]> Signed-off-by: Maciej Żenczykowski <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-02-21net: vrf: remove MTU limits for vrf deviceHangbin Liu1-0/+3
Similiar to commit e94cd8113ce63 ("net: remove MTU limits for dummy and ifb device"), MTU is irrelevant for VRF device. We init it as 64K while limit it to [68, 1500] may make users feel confused. Reported-by: Jianlin Shi <[email protected]> Signed-off-by: Hangbin Liu <[email protected]> Reviewed-by: David Ahern <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-02-21clk: renesas: r8a774c0: Fix LAST_DT_CORE_CLKFabrizio Castro1-1/+1
Enum LAST_DT_CORE_CLK needs updating as R8A774C0_CLK_CANFD was recently added and it's the core clock with the highest index. Signed-off-by: Fabrizio Castro <[email protected]> Reviewed-by: Chris Paterson <[email protected]> Fixes: 2a6efbc6da5d248c ("clk: renesas: r8a774c0: Add missing CANFD clock") Reviewed-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21clk: imx8mq: Add the missing ARM clockAbel Vesa1-0/+6
Add the ARM clock as imx_clk_cpu type. Will be used by cpufreq. Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Lucas Stach <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21dt-bindings: imx8mq-clock: Add the missing ARM clockAbel Vesa1-1/+2
Add the missing ARM clock which will be used by cpufreq Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Lucas Stach <[email protected]> [[email protected]: Fixed numbering in dt header] Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21clk: imx: imx8mq: Fix the rate propagation for arm pllAbel Vesa1-1/+1
The arm pll bypass needs to propagate the rate upwards in order for the cpufreq to work. Fixes: b80522040cd3f ("clk: imx: Add clock driver for i.MX8MQ CCM") Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Lucas Stach <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21clk: imx8mq: Add support for the CLKO1 clockFabio Estevam2-1/+6
Add the entry for the CLKO1 clock. Signed-off-by: Fabio Estevam <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21MAINTAINERS: mark CAIF as orphanJann Horn1-2/+1
The listed address for the CAIF maintainer bounces with "553 5.3.0 <[email protected]>... No such user here", and the only existing email address of the maintainer in git history hasn't responded in a week. Therefore, remove the listed maintainer and mark CAIF as orphan. Signed-off-by: Jann Horn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-02-21clk: imx8mq: Fix the CLKO2 source select listFabio Estevam1-2/+2
The CLKO2 clock source select list is the following as per the i.MX8M Reference Manual: 000 - 25M_REF_CLK 001 - SYSTEM_PLL2_DIV5 010 - SYSTEM_PLL1_DIV2 011 - SYSTEM_PLL2_DIV6 100 - SYSTEM_PLL3_CLK 101 - AUDIO_PLL1_CLK 110 - VIDEO_PLL1_CLK 111 - 32K_REF_CLK However, in imx8mq_clko2_sels[] only the first four entries are correct. Fix it by adding the missing "sys3_pll2_out" entry in order to match the description from the manual. Fixes: b80522040cd3f ("clk: imx: Add clock driver for i.MX8MQ CCM") Reported-by: Rogerio Pimentel <[email protected]> Signed-off-by: Fabio Estevam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21clk: imx8mq: Add missing M4 clocksCarlo Caione1-0/+7
The clocks list is missing the clocks for the M4 core. Signed-off-by: Carlo Caione <[email protected]> Reviewed-by: Fabio Estevam <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21clk: imx: Add clock driver support for imx8mmBai Ping3-0/+682
Add clock driver support for i.MX8MM SOC. Signed-off-by: Bai Ping <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21dt-bindings: imx: Add clock binding doc for imx8mmBai Ping2-0/+273
Add the clock binding doc for i.MX8MM. Signed-off-by: Bai Ping <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21clk: imx: Add PLLs driver for imx8mm socBai Ping3-1/+418
New PLLs are introduced on i.MX8M Mini SOC. PLL1416X is Integer PLL, PLL1443X is a Frac PLL. Signed-off-by: Bai Ping <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21clk: imx5: add imx5_SCC2_IPG_GATEMichael Grzeschik2-1/+3
This adds the missing clock for the SCC2 peripheral unit. Signed-off-by: Michael Grzeschik <[email protected]> Signed-off-by: Lucas Stach <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21clk: imx: scu: add set parent supportAisheng Dong2-3/+100
Add clk scu set parents support. Cc: Stephen Boyd <[email protected]> Cc: Shawn Guo <[email protected]> Cc: Sascha Hauer <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Michael Turquette <[email protected]> Signed-off-by: Dong Aisheng <[email protected]> [[email protected]: Remove le32_to_cpu() on get_parent op] Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21clk: imx: scu: add fallback compatible string supportAisheng Dong1-0/+1
SCU clock can be used in a similar way by IMX8QXP and IMX8QM SoCs. Make the driver support "fsl,scu-clk" fallback compatible string to allow other SoCs to reuse the common part. Cc: Shawn Guo <[email protected]> Cc: Sascha Hauer <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Stephen Boyd <[email protected]> Cc: Michael Turquette <[email protected]> Signed-off-by: Dong Aisheng <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21clk: imx8mq: Make parent names arrays const pointersAbel Vesa1-97/+97
The arrays containing the mux selectors need to be of const pointer to const char. Signed-off-by: Abel Vesa <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21clk: imx: Make parents const pointer in mux wrappersAbel Vesa1-1/+2
The parents needs to be pointer to const pointer to const char. Signed-off-by: Abel Vesa <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
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