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2020-07-28MIPS: Loongson64: Add ISA node for LS7A PCHJiaxun Yang1-0/+7
Although currently we're not enabling any ISA device in devicetree, but this node is required to express the ranges of address reserved for ISA. Signed-off-by: Jiaxun Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-28MIPS: Loongson64: DTS: Fix ISA and PCI I/O ranges for RS780E PCHJiaxun Yang1-2/+2
Ranges should express the actual physical address on bus. Also enlarge the PCI I/O size to the actual hardware limit. Signed-off-by: Jiaxun Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-28MIPS: Loongson64: Enlarge IO_SPACE_LIMITJiaxun Yang3-4/+5
It can be very big on LS7A PCH systems. Signed-off-by: Jiaxun Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-28MIPS: Loongson64: Process ISA Node in DeviceTreeJiaxun Yang1-25/+62
Previously, we're hardcoding reserved ISA I/O Space in, now we're processing it I/O via DeviceTree directly. The ranges property if ISA node is used to determine the size and address of reserved I/O space. Signed-off-by: Jiaxun Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-28of_address: Add bus type match for pci ranges parserJiaxun Yang2-12/+21
So the parser can be used to parse range property of ISA bus. As they're all using PCI-like method of range property, there is no need start a new parser. Signed-off-by: Jiaxun Yang <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-28memory: jz4780-nemc: Do not build by defaultKrzysztof Kozlowski1-1/+0
Enabling the JZ4780_NEMC driver makes sense only for specific hardware - the Ingenic SoC architecture. It is not an essential driver for the SoC support so do not enable it by default. Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-28MIPS: ingenic: Enable JZ4780_NEMC manuallyKrzysztof Kozlowski3-0/+3
The CONFIG_JZ4780_NEMC was previously a default on MIPS but now it has to be enabled manually. Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Paul Cercueil <[email protected]> Acked-by: Thomas Bogendoerfer <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-28MIPS: qi_lb60: Fix routing to audio amplifierPaul Cercueil1-1/+1
The ROUT (right channel output of audio codec) was connected to INL (left channel of audio amplifier) instead of INR (right channel of audio amplifier). Fixes: 8ddebad15e9b ("MIPS: qi_lb60: Migrate to devicetree") Cc: [email protected] # v5.3 Signed-off-by: Paul Cercueil <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-28MIPS: Remove legacy MIPS_MACHINE optionPaul Cercueil4-112/+0
The CONFIG_MIPS_MACHINE option is dead code that hasn't been used in years. The Kconfig option is not selected anywhere, and the <asm/mips_machine.h> is not included anywhere either. To make things worse, for years it co-existed with a separate MIPS machine implementation as <asm/machine.h>. The two defined the 'mips_machine' structure with different fields, and the 'MIPS_MACHINE' macro with different parameters. The two used the same memory area (defined by the linker script) to store data, and you could totally use the two at the same time for all kinds of funny results. Signed-off-by: Paul Cercueil <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-28MIPS: ath79: Remove unused include <asm/mips_machine.h>Paul Cercueil1-1/+0
Since commit 3a77e0d75eed ("MIPS: ath79: drop machfiles"), this header is not used anymore. Signed-off-by: Paul Cercueil <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-28MIPS: cpu-feature-overrides: Remove not needed overridesThomas Bogendoerfer4-8/+0
Clean up cpu-feature-overrides, which only repeat the default. Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-26MIPS: Fix unable to reserve memory for Crash kernelJinyang He1-1/+1
Use 0 as the align parameter in memblock_find_in_range() is incorrect when we reserve memory for Crash kernel. The environment as follows: [ 0.000000] MIPS: machine is loongson,loongson64c-4core-rs780e ... [ 1.951016] crashkernel=64M@128M The warning as follows: [ 0.000000] Invalid memory region reserved for crash kernel And the iomem as follows: 00200000-0effffff : System RAM 04000000-0484009f : Kernel code 048400a0-04ad7fff : Kernel data 04b40000-05c4c6bf : Kernel bss 1a000000-1bffffff : pci@1a000000 ... The align parameter may be finally used by round_down() or round_up(). Like the following call tree: mips-next: mm/memblock.c memblock_find_in_range └── memblock_find_in_range_node ├── __memblock_find_range_bottom_up │ └── round_up └── __memblock_find_range_top_down └── round_down \#define round_up(x, y) ((((x)-1) | __round_mask(x, y))+1) \#define round_down(x, y) ((x) & ~__round_mask(x, y)) \#define __round_mask(x, y) ((__typeof__(x))((y)-1)) The round_down(or round_up)'s second parameter must be a power of 2. If the second parameter is 0, it both will return 0. Use 1 as the parameter to fix the bug and the iomem as follows: 00200000-0effffff : System RAM 04000000-0484009f : Kernel code 048400a0-04ad7fff : Kernel data 04b40000-05c4c6bf : Kernel bss 08000000-0bffffff : Crash kernel 1a000000-1bffffff : pci@1a000000 ... Signed-off-by: Jinyang He <[email protected]> Reviewed-by: Jiaxun Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-26MIPS: CPU#0 is not hotpluggableHuacai Chen1-1/+1
Now CPU#0 is not hotpluggable on MIPS, so prevent to create /sys/devices /system/cpu/cpu0/online which confuses some user-space tools. Cc: [email protected] Signed-off-by: Huacai Chen <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-26MIPS: ingenic: JZ4725B: Add IPU nodePaul Cercueil2-1/+35
Add a devicetree node for the Image Processing Unit (IPU) found in the JZ4725B. Connect it with graph nodes to the LCD node. The LCD driver will expect the IPU node to be accessed through graph port #8, as stated in the bindings documentation. Signed-off-by: Paul Cercueil <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-26mips: octeon: octeon.h: delete duplicated wordRandy Dunlap1-1/+1
Delete the repeated word "as". Signed-off-by: Randy Dunlap <[email protected]> Cc: Thomas Bogendoerfer <[email protected]> Cc: [email protected] Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-26mips: octeon: cvmx-pow.h: fix duplicated wordsRandy Dunlap1-4/+4
Delete the repeated words "Returns" and convert to kernel-doc notation by adding a ':'. Signed-off-by: Randy Dunlap <[email protected]> Cc: Thomas Bogendoerfer <[email protected]> Cc: [email protected] Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-26mips: octeon: cvmx-pkoh: fix duplicated wordsRandy Dunlap1-4/+3
Delete the repeated word "command". Delete the repeated words "returns" and convert to kernel-doc notation by adding a ':'. Signed-off-by: Randy Dunlap <[email protected]> Cc: Thomas Bogendoerfer <[email protected]> Cc: [email protected] Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-26mips: octeon: cvmx-pip.h: delete duplicated wordRandy Dunlap1-1/+1
Delete the repeated word "the". Signed-off-by: Randy Dunlap <[email protected]> Cc: Thomas Bogendoerfer <[email protected]> Cc: [email protected] Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-26mips: octeon: cvmx-l2c.h: delete duplicated wordRandy Dunlap1-1/+1
Delete the repeated word "Returns". Signed-off-by: Randy Dunlap <[email protected]> Cc: Thomas Bogendoerfer <[email protected]> Cc: [email protected] Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-26mips: io.h: delete duplicated wordRandy Dunlap1-1/+1
Delete the repeated word "on". Signed-off-by: Randy Dunlap <[email protected]> Cc: Thomas Bogendoerfer <[email protected]> Cc: [email protected] Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-24mips: traps, add __init to parity_protection_initJiri Slaby1-1/+1
It references __initdata and is called only from an __init function: trap_init. This avoids section mismatches (which I am seeing with gcc 10). Signed-off-by: Jiri Slaby <[email protected]> Cc: Thomas Bogendoerfer <[email protected]> Cc: [email protected] Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-24MIPS: BCM63xx: improve CFE version detectionÁlvaro Fernández Rojas1-4/+18
There are some CFE variants that start with 'cfe-vd' instead of 'cfe-v', such as the one used in the Huawei HG556a: "cfe-vd081.5003". In this case, the CFE version is stored as is (string vs number bytes). Some newer devices have an additional version number, such as the Comtrend VR-3032u: "1.0.38-112.118-11". Finally, print the string as is if the version doesn't start with "cfe-v" or "cfe-vd", but starts with "cfe-". Signed-off-by: Álvaro Fernández Rojas <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-24MIPS: X2000: Add X2000 system type.周琰杰 (Zhou Yanjie)4-2/+20
1.Add "PRID_COMP_INGENIC_13" and "PRID_IMP_XBURST2" for X2000. 2.Add X2000 system type for cat /proc/cpuinfo to give out X2000. Signed-off-by: 周琰杰 (Zhou Yanjie) <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-24MIPS: OCTEON: add missing put_device() call in dwc3_octeon_device_init()Yu Kuai1-1/+4
if of_find_device_by_node() succeed, dwc3_octeon_device_init() doesn't have a corresponding put_device(). Thus add put_device() to fix the exception handling for this function implementation. Fixes: 93e502b3c2d4 ("MIPS: OCTEON: Platform support for OCTEON III USB controller") Signed-off-by: Yu Kuai <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-24MIPS: Retire kvm paravirtJiaxun Yang16-1017/+3
paravirt machine was introduced for Cavium's partial virtualization technology, however, it's host side support and QEMU support never landed in upstream. As Cavium was acquired by Marvel and they have no intention to maintain their MIPS product line, also paravirt is unlikely to be utilized by community users, it's time to retire it if nobody steps in to maintain it. Signed-off-by: Jiaxun Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-21MAINTAINERS: Add maintainers for MIPS core driversSerge Semin1-0/+11
Add Thomas and myself as maintainers of the MIPS CPU and GIC IRQchip, MIPS GIC timer and MIPS CPS CPUidle drivers. Signed-off-by: Serge Semin <[email protected]> Acked-by: Marc Zyngier <[email protected]> Acked-by: Daniel Lezcano <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-21bus: cdmm: Add MIPS R5 arch supportSerge Semin1-1/+1
CDMM may be available not only on MIPS R2 architectures, but also on newer MIPS R5 chips. For instance our P5600 chip has one. Let's mark the CDMM bus being supported for that MIPS arch too. Signed-off-by: Serge Semin <[email protected]> Reviewed-by: Thomas Bogendoerfer <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-21mips: cdmm: Add mti,mips-cdmm dtb node supportSerge Semin1-0/+15
Since having and mapping the CDMM block is platform specific, then instead of just returning a zero-address, lets make the default CDMM base address search method (mips_cdmm_phys_base()) to do something useful. For instance to find the address in a dedicated dtb-node in order to support of-based platforms by default. Signed-off-by: Serge Semin <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-21dt-bindings: bus: Add MIPS CDMM controllerSerge Semin1-0/+35
It's a Common Device Memory Map controller embedded into the MIPS IP cores, which dts node is supposed to have compatible and reg properties. Signed-off-by: Serge Semin <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-21dt-bindings: interrupt-controller: Convert mti,gic to DT schemaSerge Semin2-67/+148
Modern device tree bindings are supposed to be created as YAML-files in accordance with DT schema. This commit replaces MIPS GIC legacy bare text binding with YAML file. As before the binding file states that the corresponding dts node is supposed to be compatible with MIPS Global Interrupt Controller indicated by the "mti,gic" compatible string and to provide a mandatory interrupt-controller and '#interrupt-cells' properties. There might be optional registers memory range, "mti,reserved-cpu-vectors" and "mti,reserved-ipi-vectors" properties specified. MIPS GIC also includes a free-running global timer, per-CPU count/compare timers, and a watchdog. Since currently the GIC Timer is only supported the DT schema expects an IRQ and clock-phandler charged timer sub-node with "mti,mips-gic-timer" compatible string. Signed-off-by: Serge Semin <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-21dt-bindings: power: Convert mti,mips-cpc to DT schemaSerge Semin2-8/+35
It's a Cluster Power Controller embedded into the MIPS IP cores. Currently the corresponding dts node is supposed to have compatible and reg properties. Signed-off-by: Serge Semin <[email protected]> Reviewed-by: Rob Herring <[email protected]> Cc: Alexey Malahov <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16MIPS: Prevent READ_IMPLIES_EXEC propagationTiezhu Yang1-0/+1
In the MIPS architecture, we should clear the security-relevant flag READ_IMPLIES_EXEC in the function SET_PERSONALITY2() of the file arch/mips/include/asm/elf.h. Otherwise, with this flag set, PROT_READ implies PROT_EXEC for mmap to make memory executable that is not safe, because this condition allows an attacker to simply jump to and execute bytes that are considered to be just data [1]. In mm/mmap.c: unsigned long do_mmap(struct file *file, unsigned long addr, unsigned long len, unsigned long prot, unsigned long flags, vm_flags_t vm_flags, unsigned long pgoff, unsigned long *populate, struct list_head *uf) { [...] if ((prot & PROT_READ) && (current->personality & READ_IMPLIES_EXEC)) if (!(file && path_noexec(&file->f_path))) prot |= PROT_EXEC; [...] } By the way, x86 and ARM64 have done the similar thing. After commit 250c22777fe1 ("x86_64: move kernel"), in the file arch/x86/kernel/process_64.c: void set_personality_64bit(void) { [...] current->personality &= ~READ_IMPLIES_EXEC; } After commit 48f99c8ec0b2 ("arm64: Preventing READ_IMPLIES_EXEC propagation"), in the file arch/arm64/include/asm/elf.h: #define SET_PERSONALITY(ex) \ ({ \ clear_thread_flag(TIF_32BIT); \ current->personality &= ~READ_IMPLIES_EXEC; \ }) [1] https://insights.sei.cmu.edu/cert/2014/02/feeling-insecure-blame-your-parent.html Reported-by: Juxin Gao <[email protected]> Co-developed-by: Juxin Gao <[email protected]> Signed-off-by: Juxin Gao <[email protected]> Signed-off-by: Tiezhu Yang <[email protected]> Reviewed-by: Kees Cook <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16mips/vdso: Fix resource leaks in genvdso.cPeng Fan1-0/+10
Close "fd" before the return of map_vdso() and close "out_file" in main(). Signed-off-by: Peng Fan <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16MIPS: CU1000-Neo: Refresh defconfig to support LED.周琰杰 (Zhou Yanjie)1-0/+4
Refresh CU1000-Neo's defconfig to support LED. Tested-by: 周正 (Zhou Zheng) <[email protected]> Signed-off-by: 周琰杰 (Zhou Yanjie) <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16MIPS: Ingenic: Fix bugs and add missing LED node for X1000.周琰杰 (Zhou Yanjie)2-122/+118
1.The CU1000-Neo board actually uses X1000E instead of X1000, so the wrongly written "ingenic,x1000" in compatible should be changed to "ingenic,x1000e". 2.Adjust the order of nodes according to the corresponding address value. 3.Drop unnecessary node in "wlan_pwrseq". 4.Add the leds node to "cu1000-neo.dts". Tested-by: 周正 (Zhou Zheng) <[email protected]> Signed-off-by: 周琰杰 (Zhou Yanjie) <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16MIPS: Ingenic: Add YSH & ATIL CU Neo board support.周琰杰 (Zhou Yanjie)4-0/+296
Add a device tree and a defconfig for the Ingenic X1830 based YSH & ATIL CU Neo board. Tested-by: 周正 (Zhou Zheng) <[email protected]> Signed-off-by: 周琰杰 (Zhou Yanjie) <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16dt-bindings: MIPS: Add X1830 based CU1830-Neo and fix bug in CU1000-Neo.周琰杰 (Zhou Yanjie)1-3/+9
1.Add bindings for Ingenic X1830 based board, prepare for later dts. 2.The CU1000-Neo board actually uses X1000E instead of X1000, so the wrongly written "ingenic,x1000" in bindings should be changed to "ingenic,x1000e", the corresponding dts file modification will be made in a patch later in this series. Tested-by: 周正 (Zhou Zheng) <[email protected]> Signed-off-by: 周琰杰 (Zhou Yanjie) <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16MIPS: Ingenic: Add Ingenic X1830 support.周琰杰 (Zhou Yanjie)2-0/+306
Support the Ingenic X1830 SoC using the code under arch/mips/jz4740. This is left unselectable in Kconfig until a X1830 based board is added in a later commit. Tested-by: 周正 (Zhou Zheng) <[email protected]> Signed-off-by: 周琰杰 (Zhou Yanjie) <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16MIPS: fix vdso different address spacesSunguoyun1-1/+1
sparse report build warning as follows: arch/mips/vdso/vdso-n32-image.c:13:35: incorrect type in assignment (different address spaces) @@ expected void *[usertype] vdso @@ got void [noderef] <asn:1> * @@ Reported-by: kernel test robot <[email protected]> Signed-off-by: Sunguoyun <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16mips: Replace HTTP links with HTTPS onesAlexander A. Klimov2-2/+2
Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by: Alexander A. Klimov <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16MIPS: Loongson64: Load LS7A dtbsJiaxun Yang1-22/+34
Load correct devicetree according to PRID and PCH type. Signed-off-by: Huacai Chen <[email protected]> Signed-off-by: Jiaxun Yang <[email protected]> Tested-by: Tiezhu Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16MIPS: Loongson64: DeviceTree for LS7A PCHJiaxun Yang6-1/+512
Add DeviceTree files for Classic Loongson64 Quad Core + LS7A boards and Generic Loongson64 Quad Core + LS7A boards. Signed-off-by: Huacai Chen <[email protected]> Signed-off-by: Jiaxun Yang <[email protected]> Tested-by: Tiezhu Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16MIPS: Loongson64: Fix machine namingHuacai Chen2-2/+2
From previous commits, the machine names with "loongson3-" prefix have renamed to "loongson64c-" prefix in documents, but the .dts files have not been updated as well. So fix it. Signed-off-by: Huacai Chen <[email protected]> Tested-by: Tiezhu Yang <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16MIPS: Loongson: Fix boot warning about hwmon_device_register()Zhi Li1-20/+2
Replace hwmon_device_register() with hwmon_device_register_with_info() to fix the following boot warning : [ 9.029924] Loongson Hwmon Enter... [ 9.106850] (NULL device *): hwmon_device_register() is deprecated. Please convert the driver to use hwmon_device_register_with_info(). Signed-off-by: Zhi Li <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16MIPS: Loongson: Reduce possible loop times and add log in do_thermal_timer()Tiezhu Yang1-7/+6
Once the temperature of any CPUs is too high, it can power off immediately, no need to check the rest of CPUs, and it is better to print a log before power off, this is useful when analysis the abnormal issues. Signed-off-by: Tiezhu Yang <[email protected]> Signed-off-by: Zhi Li <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16MIPS: Loongson: Cleanup cpu_hwmon.cTiezhu Yang1-15/+18
Fix the following checkpatch warnings and errors: ERROR: do not initialise statics to 0 +static int csr_temp_enable = 0; WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(name, S_IRUGO, get_hwmon_name, NULL, 0); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, get_cpu_temp, NULL, 1); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, cpu_temp_label, NULL, 1); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, get_cpu_temp, NULL, 2); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, cpu_temp_label, NULL, 2); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, get_cpu_temp, NULL, 3); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, cpu_temp_label, NULL, 3); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp4_input, S_IRUGO, get_cpu_temp, NULL, 4); WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. +static SENSOR_DEVICE_ATTR(temp4_label, S_IRUGO, cpu_temp_label, NULL, 4); WARNING: Missing a blank line after declarations + int id = (to_sensor_dev_attr(attr))->index - 1; + return sprintf(buf, "CPU %d Temperature\n", id); WARNING: Missing a blank line after declarations + int value = loongson3_cpu_temp(id); + return sprintf(buf, "%d\n", value); ERROR: spaces required around that '=' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '<' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '=' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '<' (ctx:VxV) + for (i=0; i<nr_packages; i++) ^ ERROR: spaces required around that '=' (ctx:VxV) + for (i=0; i<nr_packages; i++) { ^ ERROR: spaces required around that '<' (ctx:VxV) + for (i=0; i<nr_packages; i++) { ^ WARNING: line over 80 characters + csr_temp_enable = csr_readl(LOONGSON_CSR_FEATURES) & LOONGSON_CSRF_TEMP; Signed-off-by: Tiezhu Yang <[email protected]> Signed-off-by: Zhi Li <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16MIPS: ingenic: RS90: Added defconfigPaul Cercueil1-0/+182
Add a basic default config for the RS-90 RetroMini board. Signed-off-by: Paul Cercueil <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16MIPS: ingenic: Add support for the RS90 boardPaul Cercueil3-0/+316
The RS-90, better known as RetroMini, is a small and pocketable handheld gaming console from YLMChina. It has little more than a JZ4725B SoC, a NAND, a screen, some buttons and a speaker. Signed-off-by: Paul Cercueil <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16MIPS: ingenic: Add support for the JZ4725B SoCPaul Cercueil3-0/+342
Add preliminary support for boards based on the JZ4725B SoC from Ingenic. The JZ4725B SoC is supposed to be older than the JZ4740 SoC, but its internals are much closer to what can be found on the JZ4750 and newer SoCs. It is low-power SoC with a MIPS32r1 SoC running at ~360 MHz, and no FPU. Signed-off-by: Paul Cercueil <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-07-16MIPS: ingenic: Use enum instead of macros for Ingenic SoCsPaul Cercueil1-6/+16
Use an enum instead of macros to represent the various versions of the Ingenic SoCs, and add some of the SoC versions that were previously missing. Signed-off-by: Paul Cercueil <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
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