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2017-07-04Merge branch 'pci/host-vmd' into nextBjorn Helgaas1-2/+5
* pci/host-vmd: PCI: vmd: Move SRCU cleanup after bus, child device removal PCI: vmd: Correct comment: VMD domains start at 0x10000, not 0x1000
2017-07-04Merge branch 'pci/host-versatile' into nextBjorn Helgaas1-9/+9
* pci/host-versatile: PCI: versatile: Add local struct device pointers
2017-07-04Merge branch 'pci/host-tegra' into nextBjorn Helgaas1-12/+21
* pci/host-tegra: PCI: tegra: Do not allocate MSI target memory PCI: tegra: Support MSI 64-bit addressing
2017-07-04Merge branch 'pci/host-rockchip' into nextBjorn Helgaas2-26/+100
* pci/host-rockchip: PCI: rockchip: Use normal register bank for config accessors PCI: rockchip: Use local struct device pointer consistently PCI: rockchip: Check for clk_prepare_enable() errors during resume MAINTAINERS: Remove Wenrui Li as Rockchip PCIe driver maintainer PCI: rockchip: Configure RC's MPS setting PCI: rockchip: Reconfigure configuration space header type PCI: rockchip: Split out rockchip_pcie_cfg_configuration_accesses() PCI: rockchip: Move configuration accesses into rockchip_pcie_cfg_atu() PCI: rockchip: Rename rockchip_cfg_atu() to rockchip_pcie_cfg_atu() PCI: rockchip: Control vpcie0v9 for system PM
2017-07-04Merge branch 'pci/host-rcar' into nextBjorn Helgaas2-2/+2
* pci/host-rcar: PCI: rcar-gen2: Make of_device_ids const PCI: rcar: Use proper name for the R-Car SoC
2017-07-04Merge branch 'pci/host-qcom' into nextBjorn Helgaas2-59/+396
* pci/host-qcom: PCI: qcom: Limit TLP size to 2K to work around hardware issue PCI: qcom: Fix spelling mistake: "asser" -> "assert" PCI: qcom: Reorder to put v0 functions together, v1 functions together, etc PCI: qcom: Add support for IPQ4019 PCIe controller
2017-07-04Merge branch 'pci/host-mediatek' into nextBjorn Helgaas5-0/+704
* pci/host-mediatek: dt-bindings: PCI: Add documentation for MediaTek PCIe PCI: mediatek: Add MediaTek PCIe host controller support
2017-07-04Merge branch 'pci/host-kirin' into nextBjorn Helgaas4-0/+536
* pci/host-kirin: PCI: kirin: Add HiSilicon Kirin SoC PCIe controller driver
2017-07-03PCI: rockchip: Use normal register bank for config accessorsShawn Lin1-4/+9
Rockchip's RC has two banks of registers for the root port: a normal bank that is strictly compatible with the PCIe spec, and a privileged bank that can be used to change RO bits of root port registers. When probing the RC driver, we use the privileged bank to do some basic setup work as some RO bits are hw-inited to wrong value. But we didn't change to the normal bank after probing the driver. This leads to a serious problem when the PME code tries to clear the PME status by writing PCI_EXP_RTSTA_PME to the register of PCI_EXP_RTSTA. Per PCIe 3.0 spec, section 7.8.14, the PME status bit is RW1C. So the PME code is doing the right thing to clear the PME status but we find the RC doesn't clear it but actually setting it to one. So finally the system trap in pcie_pme_work_fn() as PCI_EXP_RTSTA_PME is true now forever. This issue can be reproduced by booting kernel with pci=nomsi. Use the normal register bank for the PCI config accessors. The privileged bank is used only internally by this driver. Fixes: e77f847d ("PCI: rockchip: Add Rockchip PCIe controller support") Signed-off-by: Shawn Lin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Cc: [email protected] Cc: Jeffy Chen <[email protected]> Cc: Brian Norris <[email protected]>
2017-07-03dt-bindings: PCI: Add documentation for MediaTek PCIeRyder Lee1-0/+130
Add documentation for PCIe host driver available in MT7623 series SoCs. Signed-off-by: Ryder Lee <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Rob Herring <[email protected]>
2017-07-03Merge branch 'pci/host-imx6' into nextBjorn Helgaas2-1/+40
* pci/host-imx6: PCI: imx6: Add regulator support
2017-07-03Merge branch 'pci/host-hv' into nextBjorn Helgaas2-81/+370
* pci/host-hv: PCI: hv: Use vPCI protocol version 1.2 PCI: hv: Add vPCI version protocol negotiation PCI: hv: Temporary own CPU-number-to-vCPU-number infra PCI: hv: Use page allocation for hbus structure PCI: hv: Fix comment formatting and use proper integer fields
2017-07-03Merge branch 'pci/host-faraday' into nextBjorn Helgaas2-0/+63
* pci/host-faraday: PCI: faraday: Add clock handling PCI: faraday: Add clock bindings
2017-07-03Merge branch 'pci/host-dra7xx' into nextBjorn Helgaas2-2/+3
* pci/host-dra7xx: PCI: dwc: dra7xx: Use RW1C for IRQSTATUS_MSI and IRQSTATUS_MAIN PCI: dwc: dra7xx: Depend on appropriate SoC or compile test
2017-07-03Merge branch 'pci/host-designware' into nextBjorn Helgaas12-16/+19
* pci/host-designware: PCI: dwc: Constify dw_pcie_host_ops structures PCI: host: Mark PCIe/PCI (MSI) cascade ISR as IRQF_NO_THREAD
2017-07-03Merge branch 'pci/irq-fixups' into nextBjorn Helgaas31-295/+579
* pci/irq-fixups: arm64: PCI: Drop DT IRQ allocation from pcibios_alloc_irq() PCI: xilinx-nwl: Move to struct pci_host_bridge IRQ mapping functions PCI: rockchip: Move to struct pci_host_bridge IRQ mapping functions PCI: xgene: Move to struct pci_host_bridge IRQ mapping functions PCI: altera: Drop pci_fixup_irqs() PCI: versatile: Drop pci_fixup_irqs() PCI: generic: Drop pci_fixup_irqs() PCI: faraday: Drop pci_fixup_irqs() PCI: designware: Drop pci_fixup_irqs() PCI: iproc: Drop pci_fixup_irqs() PCI: rcar: Drop pci_fixup_irqs() PCI: xilinx: Drop pci_fixup_irqs() PCI: tegra: Drop pci_fixup_irqs() ARM/PCI: Remove pci_fixup_irqs() call for bios32 host controllers PCI: Add a call to pci_assign_irq() in pci_device_probe() OF/PCI: Update of_irq_parse_and_map_pci() comment PCI: Add pci_assign_irq() function and have pci_fixup_irqs() use it PCI: Add IRQ mapping function pointers to pci_host_bridge struct PCI: Build setup-irq.o on all arches PCI: Remove pci_scan_root_bus_msi() PCI: xilinx-nwl: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: rockchip: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: generic: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: xgene: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: xilinx: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: altera: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: versatile: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: iproc: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: rcar: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: aardvark: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: designware: Convert PCI scan API to pci_scan_root_bus_bridge() ARM/PCI: Convert PCI scan API to pci_scan_root_bus_bridge() PCI: Make pci_register_host_bridge() PCI core internal PCI: Add pci_scan_root_bus_bridge() interface PCI: tegra: Fix host bridge memory leakage PCI: faraday: Fix host bridge memory leakage PCI: Add devm_pci_alloc_host_bridge() interface PCI: Add pci_free_host_bridge() interface PCI: Initialize bridge release function at bridge allocation PCI: faraday: Convert IRQ masking to raw PCI config accessors PCI: iproc: Convert link check to raw PCI config accessors PCI: xilinx-nwl: Remove nwl_pcie_enable_msi() unused bus parameter
2017-07-03Merge branch 'pci/virtualization' into nextBjorn Helgaas11-164/+245
* pci/virtualization: PCI: Remove __pci_dev_reset() and pci_dev_reset() PCI: Split ->reset_notify() method into ->reset_prepare() and ->reset_done() PCI: Protect pci_error_handlers->reset_notify() usage with device_lock() PCI: Protect pci_driver->sriov_configure() usage with device_lock() PCI: Mark Intel XXV710 NIC INTx masking as broken PCI: Restore PRI and PASID state after Function-Level Reset PCI: Cache PRI and PASID bits in pci_dev
2017-07-03PCI: Remove __pci_dev_reset() and pci_dev_reset()Christoph Hellwig1-56/+52
Implement the reset probing / reset chain directly in __pci_probe_reset_function() and __pci_reset_function_locked() respectively. Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Christoph Hellwig <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-07-03PCI: Split ->reset_notify() method into ->reset_prepare() and ->reset_done()Christoph Hellwig5-81/+82
The pci_error_handlers->reset_notify() method had a flag to indicate whether to prepare for or clean up after a reset. The prepare and done cases have no shared functionality whatsoever, so split them into separate methods. [bhelgaas: changelog, update locking comments] Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Christoph Hellwig <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-07-02Merge branch 'pci/switchtec' into nextBjorn Helgaas2-2/+41
* pci/switchtec: switchtec: Add device IDs for additional Switchtec products switchtec: Add "running" status flag to fw partition info ioctl
2017-07-02Merge branch 'pci/resource' into nextBjorn Helgaas2-1/+33
* pci/resource: PCI: Work around poweroff & suspend-to-RAM issue on Macbook Pro 11 PCI: Do not disregard parent resources starting at 0x0 Conflicts: arch/x86/pci/fixup.c
2017-07-02Merge branch 'pci/portdrv' into nextBjorn Helgaas2-35/+76
* pci/portdrv: PCI/portdrv: Allocate MSI/MSI-X vector for Downstream Port Containment PCI/portdrv: Support multiple interrupts for MSI as well as MSI-X
2017-07-02Merge branch 'pci/pm' into nextBjorn Helgaas10-38/+86
* pci/pm: PCI/PM: Avoid using device_may_wakeup() for runtime PM x86/PCI: Avoid AMD SB7xx EHCI USB wakeup defect PCI/PM: Restore the status of PCI devices across hibernation drm/radeon: make MacBook Pro d3_delay quirk more generic drm/amdgpu: remove unnecessary save/restore of pdev->d3_delay PCI/PM: Add needs_resume flag to avoid suspend complete optimization PCI: imx6: Fix config read timeout handling switchtec: Fix minor bug with partition ID register switchtec: Use new cdev_device_add() helper function PCI: endpoint: Make PCI_ENDPOINT depend on HAS_DMA
2017-07-02Merge branch 'pci/msi' into nextBjorn Helgaas3-15/+16
* pci/msi: PCI/MSI: Ignore affinity if pre/post vector count is more than min_vecs
2017-07-02Merge branch 'pci/misc' into nextBjorn Helgaas8-31/+14
* pci/misc: x86/PCI: Simplify Dell DMI B1 quirk PCI: Add domain number check to find_smbios_instance_string() x86/PCI: Fix whitespace in set_bios_x() printk PCI: Correct PCI_STD_RESOURCE_END usage efi/fb: Correct PCI_STD_RESOURCE_END usage MIPS: PCI: Remove unused busn_offset MIPS: Loongson: Remove unused PCI_BAR_COUNT definition
2017-07-02Merge branch 'pci/enumeration' into nextBjorn Helgaas5-47/+242
* pci/enumeration: PCI: Enable ECRC only if device supports it PCI: Add sysfs max_link_speed/width, current_link_speed/width, etc PCI: Test INTx masking during enumeration, not at run-time
2017-07-02Merge branch 'pci/dpc' into nextBjorn Helgaas1-2/+2
* pci/dpc: PCI/DPC: Fix control register setting PCI/DPC: Skip DPC event if device is not present
2017-07-02PCI: vmd: Move SRCU cleanup after bus, child device removalJon Derrick1-1/+1
Recent __call_srcu() changes have exposed that we need to cleanup SRCU structures after pci_stop_root_bus() calls into vmd_msi_free(). Fixes: 3906b91844d6 ("PCI: vmd: Use SRCU as a local RCU to prevent delaying global RCU") Signed-off-by: Jon Derrick <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Keith Busch <[email protected]> Cc: <[email protected]> # 4.11
2017-07-02PCI: vmd: Correct comment: VMD domains start at 0x10000, not 0x1000Bjorn Helgaas1-1/+4
VMD domains are allocated starting at 0x10000, not 0x1000 as the comment said. Correct the comment and add a reference to the ACPI spec for _SEG. Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Keith Busch <[email protected]>
2017-07-02PCI: versatile: Add local struct device pointersBjorn Helgaas1-9/+9
Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <[email protected]>
2017-07-02PCI: tegra: Do not allocate MSI target memoryThierry Reding1-6/+16
The PCI host bridge found on Tegra SoCs doesn't require the MSI target address to be backed by physical system memory. Writes are intercepted within the controller and never make it to the memory pointed to. Since no actual system memory is required, remove the allocation of a single page and hardcode the MSI target address with a special address that maps to the last 4 KiB page within the range that is reserved for system memory and memory-mapped I/O in the FPCI address map. Signed-off-by: Thierry Reding <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Stephen Warren <[email protected]>
2017-07-02PCI: tegra: Support MSI 64-bit addressingThierry Reding1-7/+6
The MSI target address can reside beyond the 32-bit boundary on devices with more than 2 GiB of system memory. The PCI host bridge on Tegra can easily support 64-bit addresses, so make sure to pass the upper 32 bits of the target address to endpoints when allocating MSI entries. Signed-off-by: Thierry Reding <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Stephen Warren <[email protected]>
2017-07-02PCI: rockchip: Use local struct device pointer consistentlyShawn Lin1-3/+2
We have a local "struct device *dev" in rockchip_pcie_probe(). Use it consistently throughout the function. No functional change intended. Signed-off-by: Shawn Lin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-07-02PCI: rockchip: Check for clk_prepare_enable() errors during resumeArvind Yadav1-6/+28
clk_prepare_enable() can fail here and we must check its return value. Signed-off-by: Arvind Yadav <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Heiko Stuebner <[email protected]> Acked-by: Shawn Lin <[email protected]>
2017-07-02MAINTAINERS: Remove Wenrui Li as Rockchip PCIe driver maintainerShawn Lin1-1/+0
Wenrui Li changed his employer and is no longer able to maintain the Rockchip PCIe driver, so remove his email address from this file. Signed-off-by: Shawn Lin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-07-02PCI: rockchip: Configure RC's MPS settingShawn Lin1-0/+8
The default value of MPS for RC is 128 bytes, but actually it could support 256 bytes. So this patch fixes this issue. Signed-off-by: Shawn Lin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-07-02PCI: rockchip: Reconfigure configuration space header typeShawn Lin1-0/+14
Per PCIe base specification (Revision 3.1a), section 7.5.3, type 1 configuration space header should be used when accessing PCIe switch. So we need to reconfigure the header according to the bus number we are accessing. Otherwise we could not visit the buses behind the switch. Signed-off-by: Shawn Lin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-07-02PCI: rockchip: Split out rockchip_pcie_cfg_configuration_accesses()Shawn Lin1-10/+25
We need to reconfigure the header type later, so split out a new function. Signed-off-by: Shawn Lin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-07-02PCI: rockchip: Move configuration accesses into rockchip_pcie_cfg_atu()Shawn Lin1-10/+11
Configuration accesses is also part of ATU settings, so let's keep all of them inside rockchip_pcie_cfg_atu(). Signed-off-by: Shawn Lin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-07-02PCI: rockchip: Rename rockchip_cfg_atu() to rockchip_pcie_cfg_atu()Shawn Lin1-3/+3
Rename rockchip_cfg_atu() to keep the name consistent with other functions in pcie-rockchip.c. Signed-off-by: Shawn Lin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-07-02PCI: rockchip: Control vpcie0v9 for system PMShawn Lin1-0/+11
vpcie0v9 is used for PHY, so we could disable it as we don't need PHY to work then in S3 if folks assign it DT. But we should note that there is a side effect that we could not support beacon wakeup if we disable vpcie0v9 for aggressive power-saving. Signed-off-by: Shawn Lin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Cc: Brian Norris <[email protected]> Cc: Jeffy Chen <[email protected]>
2017-07-02PCI: rcar-gen2: Make of_device_ids constArvind Yadav1-1/+1
of_device_ids are not supposed to change at runtime. All functions working with of_device_ids provided by <linux/of.h> work with const of_device_ids. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Simon Horman <[email protected]> Acked-by: Geert Uytterhoeven <[email protected]>
2017-07-02PCI: rcar: Use proper name for the R-Car SoCWolfram Sang1-1/+1
It is 'R-Car', not 'RCar'. No code or binding changes, only descriptive text. Signed-off-by: Wolfram Sang <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Geert Uytterhoeven <[email protected]> Acked-by: Simon Horman <[email protected]>
2017-07-02PCI: qcom: Limit TLP size to 2K to work around hardware issueSrinivas Kandagatla1-0/+13
Limit TLP size to 2K to work around a hardware bug in the v0 version of PCIe IP. When using default TLP size of 4K, the internal buffer gets corrupted due to this hardware bug. This bug was originally noticed during ssh session between APQ8064-based board and PC. Network packets got corrupted randomly and terminated the ssh session due to this bug. Signed-off-by: Srinivas Kandagatla <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-07-02PCI: qcom: Fix spelling mistake: "asser" -> "assert"Colin Ian King1-1/+1
Trivial fix to spelling mistake in dev_err message. Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-07-02PCI: qcom: Reorder to put v0 functions together, v1 functions together, etcBjorn Helgaas1-61/+61
Previously the v0, v1, and v2 functions were not grouped together in a consistent order. Reorder them to make them consistent. Signed-off-by: Bjorn Helgaas <[email protected]>
2017-07-02PCI: qcom: Add support for IPQ4019 PCIe controllerJohn Crispin2-1/+325
Add support for the IPQ4019 PCIe controller. IPQ4019 supports Gen 1/2, one lane, one PCIe root complex with support for MSI and legacy interrupts, and it conforms to PCI Express Base 2.1 specification. The core init is the same as for the MSM8996, however the clocks and reset lines differ. [bhelgaas: fix qcom_pcie_get_resources_v3(), qcom_pcie_init_v3() compile issues] Signed-off-by: John Crispin <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Stanimir Varbanov <[email protected]> Acked-by: Rob Herring <[email protected]> # binding
2017-07-02PCI: mediatek: Add MediaTek PCIe host controller supportRyder Lee4-0/+574
Add support for the MediaTek PCIe Gen2 controller which can be found on MT7623 series SoCs. [bhelgaas: fold in mtk_pcie_parse_and_add_res() bugfix from http://lkml.kernel.org/r/[email protected]] [bhelgaas: fold in MAINTAINERS update from http://lkml.kernel.org/r/[email protected]] [bhelgaas: fold in pci_scan_root_bus_bridge() update and leak fix from http://lkml.kernel.org/r/[email protected]] [bhelgaas: fold in powerup fixes from http://lkml.kernel.org/r/[email protected]] [bhelgaas: fold in poweroff when link down fixes from http://lkml.kernel.org/r/[email protected]] [bhelgaas: fold in optional property fixes from http://lkml.kernel.org/r/[email protected]] [bhelgaas: set host->map_irq and host->swizzle_irq and drop pci_fixup_irqs(), remove unnecessary "return", rename mtk_pcie_link_is_up() to mtk_pcie_link_up() for consistency, add local struct device pointer] [bhelgaas: fold in pci_add_flags() removal from http://lkml.kernel.org/r/[email protected]] Signed-off-by: Ryder Lee <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-07-02PCI: kirin: Add HiSilicon Kirin SoC PCIe controller driverXiaowei Song4-0/+536
Hisilicon PCIe driver shares the common functions for PCIe dw-host. The poweron functions are developed on hi3660 SoC, while other functions are common for Kirin series SoCs. Low power mode (L1 sub-state and Suspend/Resume), hotplug and MSI feature are not supported currently. Signed-off-by: Xiaowei Song <[email protected]> [bhelgaas: fold in MAINTAINERS update from http://lkml.kernel.org/r/[email protected]] Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Jingoo Han <[email protected]> Cc: Guodong Xu <[email protected]>
2017-07-02PCI: imx6: Add regulator supportQuentin Schulz2-1/+40
Some boards might require to control a regulator to power the PCIe port. Add support for an optional regulator defined in Device Tree linked in the PCIe controller under `vpcie-supply`. If present, the regulator will be disabled and then enabled as part of the PCIe host initialization process and will be disabled when shutting down. Signed-off-by: Quentin Schulz <[email protected]> [bhelgaas: use dev_err() instead of pr_err() in imx6_pcie_assert_core_reset()] Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Rob Herring <[email protected]> Acked-by: Richard Zhu <[email protected]>
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